Abstract: The present disclosure provides a shift register unit including a pull-up module, an input module, a reset module, a first pull-down module, a second pull-down module, a first control module, a second control module, a first state clearing module, and a second state clearing module. The shift register unit utilizes a first clock signal and a second clock signal to cause the first and second pull-down modules to pull down alternately, in order to maintain the stability of the output signal. Furthermore, each of the TFTs in the circuit structure has a duty cycle smaller than 50%, so that the lifetime of TFTs is greatly increased. The present disclosure further provides a gate driving device and a display device using the shift register unit.

Abstract: A data transmission system comprises an operation apparatus and a matrix display apparatus. The matrix display apparatus includes a display panel and a control unit. The control unit receives a data stream and transmits at least a part of the data stream to an electrode on the display panel. When the operation apparatus operates on a display surface of the matrix display apparatus, at least a part of the data stream is coupled to the operation apparatus from the matrix display apparatus. Thereby, the data stream such as data or file can be transmitted to the operation apparatus from the matrix display apparatus through a wireless communication. The data transmission system of the invention can be combined with the application of the near field communication, and the data or file can be transmitted to another electronic apparatus through the display apparatus so that the application can be expanded.

Abstract: A pixel structure including an active device and a pixel electrode is provided. The pixel electrode is electrically connected to the active device and includes a main trunk portion and branch portions. The main trunk portion includes a first extending part and a second extending part that cross each other. The plurality of branching portions is connected to the main trunk portion, and each branching portions is separated by the main trunk portion. The branching portions include a plurality of first branching part and a plurality of second branching part. The first extending part separates the first and second branching part. An included angle of at least part of the first branching part and the second extending part is ?1, an included angle of at least part of the second branching part and the second extending part is ?2, and ?1 is not equal to ?2.

Abstract: A GOA circuit for an LCD includes GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to a scan line. The scan line includes a nth scan line, a (n+1)th scan line, and a (n+2)th scan line. The GOA unit at the an nth stage includes a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. The improved GOA circuit at one stage corresponds to the output of three gate lines. So a number of the stages of the GOA circuit is reduced. Only ? stage of the conventional GOA circuit is needed. Because of the decrease in the number of the stages, more flexibility of design is given to the GOA circuit at each stage. It is beneficiary for the design in narrow bezels.

Abstract: A driver circuit driving a display device comprises: a gradation voltage generating circuit for generating m gradation voltages (m is an integer larger than or equal to 2) indicative of m stages of gradation levels; n decoder circuits each configured to select, out of the m gradation voltages, n drive voltages (n is an integer larger than or equal to 2) corresponding to n data pieces on the basis of n input gradation signals; m gradation voltage wirings each for transferring the m gradation voltages to the n decoder circuits, respectively; and a charge supplementing circuit for supplementing each of the m gradation voltage wirings with an amount of electric charge when a voltage drop occurs in the gradation voltage wirings.

Abstract: The present disclosure discloses a linear motor system. The system includes a linear motor and a drive module which drives the linear motor to vibrate. The linear motor includes a housing having an accommodating space, a vibrating module accommodated in the accommodating space and an elastic part for supporting the vibrating module in the accommodating space elastically. The drive module includes a drive unit for driving the vibrating module to vibrate and a tuning unit for regulating the resonant frequency of the vibrating module. Moreover, the linear motor system of the present disclosure can meet vibration requirements of various application programs and scenes.

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

Abstract: Different full screen content is displayed on the same television at the same time from the perspective of the viewer by displaying as the content as two full screen sequential frames. The different full screen content may be provided as a single combined frame signal such as a side-by-side, top-bottom, or checkerboard signal which is then displayed as two sequential full screen frames. Configured glasses such as polarized or shutter are used to view the different content as full screen content where one pair of configured glasses views an initial one of the sequential frames but blocks the subsequent one and another pair of configured glasses blocks the initial one of the sequential frames and views the subsequent one. Shutter glasses have both lenses open during the initial frame and both closed during the subsequent one. For polarized glasses, the initial frame has a polarization matching both lenses of one pair of glasses while the subsequent frame has a polarization that differs from both lenses.

Abstract: The gate driving circuit includes an (m?1)-th stage externally receiving a first dummy signal for a first time period to control a turn-off, an m-th stage externally receiving a second dummy signal for the first time period to control the turn-off, an (m?2)-th stage receiving an m-th carry signal for a second time period from the m-th stage and externally receiving the second dummy signal for the second time period to control the turn-off, and an (m?3)-th stage receiving an (m?1)-th carry signal for the second time period from the (m?1)-th stage and externally receiving the first dummy signal for the first time period to control the turn-off, wherein the first time period is longer than the second time period.

Abstract: The present invention provides a pixel circuit, a driving method thereof, an array substrate, and a display device. The pixel circuit comprises: a reset unit, configured to output a reference signal; a data writing unit, configured to output a data signal; a compensation unit, which is connected to the reset unit and the data writing unit as well as an output node, and receives a power voltage signal, and a light-emitting unit, which is connected to the output node and a cathode of a power supply and configured to emit light under the drive of the light emission drive signal in a light emission phase.

Abstract: A data driver includes a digital-to-analog converter, a control signal output circuit, and an output buffer. The digital-to-analog converter generates first data voltages and second data voltages based on image data and a polarity control signal. Each first data voltage has a positive polarity, and each second data voltage has a negative polarity. The control signal output circuit outputs a first output control signal and a second output control signal based on the polarity control signal. A phase of the second output control signal is different from a phase of the first output control signal. The output buffer outputs the first data voltages based on the first output control signal and outputs the second data voltages based on the second output control signal.

Abstract: The present invention provides a display device with reduced power consumption and that reduces changes in luminance, and perceptibility of flicker, and a driving method thereof. A display device according to an exemplary embodiment comprises: a display panel configured to display a still image and a motion picture; a signal controller configured to control signals for driving the display panel; and a graphics processing unit configured to transmit input image data to the signal controller, wherein the signal controller comprises a frame memory configured to store the input image data, and the display panel is driven at a first frequency when the motion picture is displayed and the display panel is driven at a second frequency that is lower than the first frequency when the still image is displayed.

Abstract: A light module comprises first excitation radiation source emitting first excitation radiation having a first optical property value, second excitation radiation source emitting second excitation radiation having a second optical property value which differs from the first value. At irradiation region (P), a phosphor and an optical element, which is at least partly reflective with maintenance of the optical property, are arranged alternately or simultaneously. A first dichroic mirror is arranged between the first excitation radiation source and irradiation region (P), and a second dichroic mirror is arranged between the second excitation radiation source and irradiation region (P). The first optical path proceeding from the first excitation radiation source successively comprises the first dichroic mirror, irradiation region (P) and the second dichroic mirror.

Abstract: In a liquid crystal device according to the invention, a pre-tilt angle of a liquid crystal layer is greater on an opposing electrode side than on a pixel electrode side. A high potential and a low potential relative to an opposing electrode potential are alternately applied to pixel electrodes through switching elements; and the opposing electrode potential is higher than a standard potential, the standard potential being a potential in which the average potential between the high potential and the low potential has been shifted by an amount equivalent to the average value of the amount of change in the potential of the pixel electrodes caused by parasitic capacitance in the switching elements when the high potential is applied to the pixel electrodes and the amount of change in the potential of the pixel electrodes caused by parasitic capacitance when the low potential is applied to the pixel electrodes.

Abstract: A liquid crystal display device includes: a first substrate for which a single pixel includes: first, second and third thin film transistors on the first substrate; a pixel electrode including a first subpixel electrode and a second subpixel electrode which are connected to the first thin film transistor and the second thin film transistor, respectively; and a divided reference voltage line connected to the third thin film transistor; a second substrate facing the first substrate; a common electrode on the second substrate; and a liquid crystal layer between the pixel electrode and the common electrode and including liquid crystal molecules. The third thin film transistor includes an electrically floating gate electrode, a source electrode defined by an extended portion of a terminal of the second thin film transistor, and a drain electrode defined by an extended portion of the divided reference voltage line.

Abstract: A testing apparatus to establish a fault by a process of elimination includes an input unit, a signal converting unit, a switch unit, and a display unit. The input unit receives an input signal and outputs a switch signal. The signal converting unit receives the switch signal and outputs a control signal. The switch unit receives the control signal and outputs a test signal. The display unit receives the test signal and runs a built in self test (BIST) program to test the proper functioning of the display unit. The signal converting unit outputs a data signal and a clock signal to the display unit when the display unit works normally. The signal converting unit not output the data signal and the clock signal to the display unit when the input signal and resulting control signal are repeated.

Abstract: A pixel circuit, an organic electroluminescent display panel and a display device are provided. The pixel circuit includes a light emitting element, a first capacitor, a reset control module, a drive control module, a compensation control module, and a light emission control module. In a reset phase, the reset control module writes a reset signal at a reset signal end into a second end of the first capacitor. In a compensation phase, the reset control module writes a data signal at a data signal end into a first end of the first capacitor, and the drive control module charges the first capacitor through the compensation control module. In a light emission phase, both the light emission control module and the first capacitor enable the drive control module to drive the light emitting element with a stable current for emission of light.

Abstract: A display panel including a display part including a plurality of sub-pixels configured to display a plurality of colors, and a plurality of data lines connected with the sub-pixels; a first test part configured to supply a test signal to (2K?1)th data lines (‘K’ is an integer above 0) by each color for the sub-pixels among the plurality of data lines; and a second test part configured to supply a test signal to 2Kth data lines by each color for the sub-pixels among the plurality of data lines when the first test part supplies the test signal. Further, a polarity of the test signal supplied by the second test part is opposite to a polarity of the test signal supplied by the first test part.

Abstract: Disclosed is a luminance compensation apparatus of an organic light emitting diode panel including a reference pixel element unit that is installed at an outer peripheral portion of a display area on an organic light emitting diode panel and operate corresponding to a pixel element aligned in the display area, and a driving chip that is provided in an area including the reference pixel element unit of the outer peripheral portion of the display area, compares a luminance value of light incident from the reference pixel element unit with a reference luminance value to calculate a luminance deviation value based on a comparison result, controls driving of pixel elements aligned in the display area according to the luminance deviation value, and allows light, luminance deviation of which has been compensated, to be irradiated.

Abstract: The present disclosure relates to a field of display technology. Provided are a shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit includes an input module, a pull-up module, a pull-down control module and a pull-down module. The turn-on duty ratio of transistors in the shift register unit may be reduced, and the power consumption of the display device product may be reduced.

Abstract: A method of operating a display including loading image data to pixels in multiple rows of pixels in an array of pixels during a data loading phase, actuating the pixels in the multiple rows during an update phase, and illuminating at least one lamp during an lamp illumination phase to illuminate the actuated pixels to form an image on the display, in which each of the loading, actuating and illuminating phases partially overlap in time.

Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.

Abstract: Aspects of embodiments of the present invention include a display device including: a display unit comprising a plurality of scan lines that extend in a row direction, a plurality of data lines that extend in a column direction, and a plurality of pixels coupled to the scan lines and the data lines; a scan driver configured to sequentially apply a scan signal of a gate-on voltage to the scan lines during a writing period for applying a data voltage to the pixels; and a data driver configured to apply a data voltage to the data lines during the writing period, wherein a first power source voltage supplying a driving current of the pixels is applied to the data lines during a period other than the writing period.

Abstract: A display device includes a timing controller and a data driver. The timing controller to output a first control value including information on low gray scale values, a second control value including information on high gray scale values, and a third control value including information on subfields, corresponding to input data. The data driver to control the gray scale value of a pixel in a plurality of subfields in one frame based on the first, second and third control values. The pixel is driven in an analog manner when the gray scale value based on whether the first or second control value is output, and is driven in a digital manner when the gray scale value corresponds to an emission time during a predetermined subfield among the plurality of subfields.

Abstract: The present invention discloses a pixel driving circuit of OLED display, which comprises: a scanning transistor TFT1, the source thereof being connected to the data line, the gate thereof being connected to a current row scanning control line, the drain thereof being connected to a first terminal of a storage capacitor C1; a precharging transistor TFT3, the source thereof being connected to the data line, the gate thereof being connected to a previous row scanning control line, and the drain thereof being connected to the first terminal of the storage capacitor C1; a driving transistor TFT2; and an organic light emitting diode; wherein, the scanning time of the current row scanning control line at least partially overlaps that of the previous row scanning control line. The embodiment of the present invention can improve the charging efficiency of the storage capacitor in each pixel unit and then improve the display effects.

Abstract: A pixel circuit, an organic electroluminescent display panel and a display device are provided. The pixel circuit includes a light emitting element, a first capacitor, a reset control module, a drive control module, a compensation control module, and a light emission control module. In a reset phase, the reset control module writes a reset signal at a reset signal end into a second end of the first capacitor. In a compensation phase, the reset control module writes a data signal at a data signal end into a first end of the first capacitor, and the drive control module charges the first capacitor through the compensation control module. In a light emission phase, both the light emission control module and the first capacitor enable the drive control module to drive the light emitting element with a stable current for emission of light.

Abstract: A folded cascode amplifier (FCA) including cascode stages coupled in a stacked cascode configuration, an input stage, and a switch circuit. The stages may include first and second P-type stages and first and second N-type stages, in which the first N-type stage and the input stage receive first and second bias voltages, respectively. The switch circuit couples a first cascode bias voltage to the second P-type stage and couples a second cascode bias voltage to the first N-type stage in a high power state, and decouples the first and second cascode bias voltages in a low power state. A non-switched low current bias generator provides the first and second bias and cascode bias voltages, which remain substantially stable in the low and high power states. Only low parasitic capacitance nodes are switched between power states so that the gain of the FCA recovers very quickly for the high power state.

Abstract: The present invention relates to a signal detection system of a touch screen, and more particularly to a signal detection system of a large-sized mutual capacitive multi touch screen that is capable of effectively reducing RC time delay, signal distortion, an effect of noise, parasitic resistance, and parasitic capacitance.

Abstract: Disclosed is a display device which includes: a plurality of gate lines arranged in a first direction; a plurality of data lines arranged in a second direction crossing the first direction; a plurality of jumping electrodes each disposed a first edge portion of each of the data lines; and a plurality of shield portions disposed between the jumping electrodes. Such a display device allows the shield portions to be disposed between the jumping electrodes. As such, the display device can prevent a light leak phenomenon due to an electric field which is generated by the shortened distance between the front edge portions of the data lines.

Abstract: A liquid crystal display (LCD) that includes a plurality of segments, and a plurality of control lines to activate the plurality of segments. Each of the plurality of segments is associated with an intersection of two of the control lines, and each of the plurality of control lines intersects with each of the other plurality of control lines.

Abstract: Driver circuits (20) for driving light circuits (21) comprising light emitting diodes are provided with converters (22) for converting input signals into output signals comprising pulses per cycle. The converters (22) comprise adapters (33) for, in response to differences between measured amplitude values of the input/output signals and nominal amplitude values of the input/output signals, adapting widths of the pulses. Then, signals having relatively precise amplitudes are no longer required. Said adapting may comprise increasing/decreasing the widths in case the measured amplitude value is smaller/larger, respectively, than the nominal amplitude value. The measured amplitude value divided by the nominal amplitude value is equal to a correction value. An adjusted duty cycle of the output signal may be made equal to a nominal duty cycle of the output signal divided by the correction value. Said adapting may be performed in a production/testing process environment.

Abstract: A display substrate includes a first display substrate comprising a display area having an array of switching elements and a peripheral area surrounding the display area, a second display substrate facing the first display substrate, a color filter disposed on the display area of the first display substrate, a first backflow-blocking pattern including a material substantially the same as the color filter and disposed on the peripheral area and an insulation layer covering the color filter and the first backflow-blocking pattern, the insulation layer having a hole exposing, for outgas testing purposes, a corresponding portion of the first backflow-blocking pattern.

Abstract: A shift register includes series-connection circuits to transmit a shift pulse. The series-connection circuits include a continuous stage group with continuous stages. Each stage of the continuous stage group includes a first output transistor, a first capacitor, an input gate, a first switching element, a second switching element, a third switching element, and a fourth switching element.

Abstract: An LCD apparatus has a first scan line transmitting a first scan signal, a second scan line transmitting a second scan signal, a data line intersecting the first and second scan lines, a switch element electrically coupled to the first scan line and the data line, a pixel electrode electrically coupled to the switch element, a coupling capacitance electrically coupled to the pixel electrode and the second scan line. The second scan line has three different voltage levels. When the first scan line enables the switch element, the pixel electrode receives a data signal through the data line. When the second scan signal switches to the third voltage level from the second voltage level, the pixel electrode is negative polarity, and when the second scan signal switches to the second voltage level from the third voltage level, the pixel electrode is positive polarity.

Abstract: To provide a signal processing device which enable the user to rapidly repeat an operation of changing to a different resolution with a fingertip touch in the line of sight to a displayed graph. A display unit 31 that displays a graph, a touch panel 32 that is provided so as to correspond to a display screen 31a and includes a touch sensor for outputting positional information associated with a touch operation, and a parameter data table 44 that stores a plurality of processing parameters corresponding to each positional information item. A control unit 50 includes a processing parameter output unit 54 that reads the processing parameter corresponding to the positional information from the parameter data table 44 and outputs the processing parameter to the processing parameter setting unit 21, if the positional information is input.

Abstract: DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2^n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A?1+2^n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A?4+2^n) and (A+2^n), and an at most {?4+2^(n?2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {?3+2^(n?2)} reference voltages that are other than the four number of reference voltages from the {1+2^(n?2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2^(n?2).

Abstract: When the degree of reliability of a motion vector is equal to or higher than a threshold, an interpolated image is generated, and the image of a frame of interest and the interpolated image are output to a panel in the order named. Every time the image is output, a backlight is turned on. When the degree of reliability is lower than the threshold, the image of the frame of interest is output twice to the panel. Every time the image is output, the backlight is controlled to alternately set its light amount to the first light amount and the second light amount smaller than the first light amount.

Abstract: An array substrate, a display device and a method for fabricating an array substrate are disclosed.

Abstract: The present disclosure relates to a shift register, a gate driving circuit and a display apparatus, wherein the shift register outputs an output signal of each stage in a forward direction according to a forward scanning signal and outputs the output signal of each stage in a reverse direction according to a reverse scanning signal, each stage of the shift register includes a forward scanning switch module, a reverse scanning switch module, a pull-up driving module; a pull-up module; a pull-down driving module; a first pull-down module; and a second pull-down module. A bi-directional scanning can be achieved by using the forward scanning switch module and the reverse scanning switch module to control to input different signals to different modules.

Abstract: When there are a plurality of rows with the same display content, a scanning order calculating portion (23) provided in a display control circuit (200) determines addresses sequentially such that scanning signal lines corresponding to the rows are selected at the same time. A scanning order setting portion (24) controls an address output portion (26) such that the scanning signal lines are selected in such an order, and also controls digital image signals DV outputted by output frame memory (22). In this case, the number of changes in potential for video signal lines can be reduced by the number of rows selected at the same time, resulting in reduced power consumption for driving the video signal lines.

Abstract: First and second scanning signal line drive circuits provided in this liquid crystal display device perform interlacing drive. Gate clock signals, gate start pulse signals, and clear signals provided to these drive circuits are supplied through two trunk lines corresponding to two shift register circuits included in each of the drive circuits. Accordingly, when compared to a typical conventional scanning signal line drive circuit including one shift register circuit, the number of bistable circuits connected to one trunk line is halved and the clock signals have lower frequencies, whereby it is possible to further reduce power consumption.

Abstract: The described technology relates to a liquid crystal display and a driving method thereof. The liquid crystal display includes a plurality of pixels arranged in a matrix form. The pixels include a liquid crystal capacitor including a pixel electrode and a common electrode as two terminals. A plurality of data lines transfer data to the plurality of pixels. The pixels include a first pixel and a second pixel, which are adjacent to each other. First and second common signals are applied to the common electrode of the first and second pixels, respectively. The second common signal is inverted to the first common signal. The first and second common signals swing between a first voltage and a second voltage. The polarity of the data voltage transferred by a data line with respect to the first common signal or the second common signal is constant during one frame.

Abstract: A display device includes multiple pixels, a gate driver and a data driver. Each pixel includes a transistor and a pixel capacitor electrically coupled to the transistor. The gate driver is configured to turn on the transistor of a first pixel for one time during a first turn-on period of multiple turn-on cycles of a frame cycle of a frame displayed by the display device. The data driver is configured to charge the pixel capacitor of the first pixel via the transistor of the first pixel to a first over-charge voltage and a data voltage during an over-charge period and a recovery period of the first turn-on period. The first over-charge voltage is different from the data voltage. A method for driving the display device is also provided.

Abstract: A gate driver includes a precharge signal generating part configured to generate a precharge signal which varies based on a previous data signal corresponding to a previous gate line and a data signal corresponding to a gate line, and a signal adding part configured to add the precharge signal and a non-precharge signal to generate a gate signal.

Abstract: A system and method for driving a three-dimensional liquid crystal display (3D LCD) device uses a target frequency, where the target frequency is double of a monocular frequency of an input picture of the 3D LCD device, and the monocular frequency is in the range of 62 Hz-118 Hz. The system and method converts a frame rate of the input picture of the 3D LCD device into (62 Hz-118 Hz)×2, and monocular frequency through the 3D glasses is in the range of 62 Hz-118 Hz.

Abstract: In the present invention, after the corresponding thin-film transistor is turned on by a first scan line, charging is achieved through a pixel electrode. After that, the corresponding thin-film transistor is turned on by a second scan line. The common voltage starts to be applied to the pixel electrode. In such a manner, the insertion of grey-scale pictures is carried out. Moreover, the embodiments of the present invention control the duration of time of a second scan signal on the second scan line so as to pull down the voltage of the pixel electrode to different voltage levels, thereby achieving the insertion of grey-scale pictures with varied brightness.

Abstract: An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

Abstract: The present disclosure provides a power saving method for a LCD comprising a plurality of scan lines. The power saving method comprises segregating the scan lines into a plurality of scan line groups; and individually performing a waveform-shaping function on each of the scan-line groups at different time points.

Abstract: A scan driver is coupled to a plurality of scan lines and includes a plurality of stages. Each of the stages is configured to sequentially receives clock signals that are phase delayed by two horizontal cycles or more from three of a plurality of clock lines, and output a scan signal having a pulse width of two horizontal cycles or more to a corresponding scan line. The scan signals are overlapped with each other by one horizontal cycle or more.

Abstract: A display device includes: a pixel array section having pixels arranged in a form of a matrix on a display panel; a first terminal group disposed on the display panel so as to correspond to each control line of a first control line group arranged in each pixel row of the pixel array section; a first wiring group for electrically connecting each terminal of the first terminal group to each control line of the first control line group; a second terminal group disposed on the display panel for a second control line group arranged in each pixel row of the pixel array section with a plurality of control lines as a unit; and a second wiring group for electrically connecting each terminal of the second terminal group to each control line of the second control line group through parts between the terminals of the first terminal group.