Abstract: Provided is a graphics rendering device that includes a frame data generation unit, access pattern setting unit, and frame data writing unit. The frame data generation unit generates, from part of stencil data, a part of frame data composed of a piece of second pixel information corresponding to a predetermined number of pixels in accordance with a first access pattern and an anti-alias pattern used in generating pieces of second pixel information. The access pattern setting unit sets, in accordance with the first access pattern and the anti-alias pattern, a second access pattern indicating pieces of second pixel information accessible by a single access to the frame buffer. The frame data writing unit writes in the frame buffer, when the frame data generation unit has generated a number of pieces of second pixel information indicated by the second access pattern, a part of the frame data corresponding to the number of pieces of second pixel information in accordance with the second access pattern.

Abstract: Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines.

Abstract: An apparatus and method for converting an object from viewpoint-relative coordinates to object-relative coordinates are provided. The method includes obtaining an object identifier from an object record of the object, obtaining a minimum x-coordinate and a maximum x-coordinate of the object from the object record, obtaining a minimum y-coordinate and a maximum y-coordinate of the object from the object record, obtaining the x-coordinates and the y-coordinates of the object to be transformed from the viewpoint-relative coordinates to the object-relative coordinates, storing the object identifier of the object to a first channel of an auxiliary buffer, transforming the x-coordinates of the object and storing the transformed x-coordinates to a second channel of the auxiliary buffer, and transforming the y-coordinates of the object and storing the transformed y-coordinates to a third channel of the auxiliary buffer.

Abstract: A display comprises a front-end component having light shutters and a plurality of backlight devices, wherein the display operates in a full screen video display mode and partial screen energy-saving auxiliary mode. In the full screen video display mode, the backlight devices are activated and in the partial screen energy-saving auxiliary mode, at least one backlight device is not activated. In the auxiliary mode, the light shutters can control luminance or the light shutters along with attenuating the backlight device control luminance. In the auxiliary mode, the backlight devices are driven via enabled inputs, a digital bus system, or an analog control signal.

Abstract: A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

Abstract: A semiconductor apparatus pertaining to one embodiment has: a first processor that operates by a first program and reads pixel data from a storage unit; a second processor that operates by a second program, performs processing to the pixel data, and writes the processed pixel data back to the storage unit; and a buffer circuit that transfers the pixel data from the first processor to the second processor.

Abstract: A system, method, and computer program product are provided for modifying a pixel value as a function of a display duration estimate. In use, a value of a pixel of an image frame to be displayed on a display screen of a display device is identified, wherein the display device is capable of handling updates at unpredictable times. Additionally, the value of the pixel is modified as a function of an estimated duration of time until a next update including the pixel is to be displayed on the display screen. Further, the modified value of the pixel is transmitted to the display screen for display thereof.

Abstract: Some embodiments provide a system that executes a web application. During operation, the system loads the web application in a web browser and loads a native code module associated with the web application into a secure runtime environment. Next, the system writes a set of rendering commands to a command buffer using the native code module and concurrently reads the rendering commands from the command buffer. Finally, the system renders an image for use by the web application by executing the rendering commands using a graphics-processing unit (GPU).

Abstract: Some aspects pertain to ray data storage for ray tracing rendering. Attribute data for a first ray can be stored. To define a second ray, data defining such can comprise a reference to the first ray (in one example) and attribute source information indicative of shared attributes between the first and second rays. The attribute source information can be shared among many rays, and can be selected based on ray type. Definition data for unshared attributes can be explicit with the second ray. A plurality of rays can reference one ray for shared attribute data. Referencing rays can be counted and decremented as referencing rays complete. Shared attributes can be indicated with masks. Interface modules can service ray data read and write requests made by shaders, and shaders can explicitly reference attributes of rays, without using such interfacing modules.

Abstract: The present invention provides an image processing device, including a buffering unit, a minifying unit, a synchronous dynamic random access memory (SDRAM), an overdriving unit, a comparing unit, a restoring unit, and an output controlling unit. The present invention further provides an image processing method and a liquid crystal display incorporated with the image processing device. The image processing device, the image processing method, and the liquid crystal display incorporated with the image processing device will not only directly perform the overdrive-processing of an input high-resolution image, but will also, on the one hand caches an input high-resolution image by the buffering unit, and on the other hand minifies an input high-resolution image. As a result, the image data is already reduced when the overdrive-processing performs, and the consumption of the space of the SDRAM is also accordingly reduced.

Abstract: A scaling device for receiving and scaling a digital image signal includes a scaling module and a data quantity control logic. The scaling module scales the digital image signal and then outputs a scaled output signal according to a scaling ratio. The data quantity control logic controls output quantity of the scaled output signal according to a scaling ratio. Thus, when the data quantity outputted from the scaling module is controlled within the data quantity that may be processed by the post stage of the scaling module per unit time, the data quantities that may be processed per unit time in the post stage processing devices of the scaling module approximate a constant value such that the post stage processing speed of the scaling module may be increased.

Abstract: The present application relates to method of driving an image display device comprising inserting a black data frame displaying black data between neighboring data frames alternately displaying left-eye data and right-eye data; comparing an nth frame corresponding to a current frame and an (n?2)th frame corresponding to a previous frame with each other when the data frames are input, reading a compensation value according to the comparison result from a lookup table and modulating input data of the nth frame using the read compensation value to output a modulated data; and bypassing data corresponding to the black data without modulating the data when the black data is input to output a bypass data, the application also relates to said image display device.

Abstract: A method is provided in one example and includes receiving overlay data at a dual frame buffer module, which interacts with a video data buffer and an alpha data buffer. The method can also include storing the overlay data as a first video data in the video data buffer if an indicator is not present in the overlay data; and storing the overlay data as a second video data in the alpha data buffer if the indicator is present. In more specific implementations, the indicator is a pixel in a non-viewable area of the overlay data.

Abstract: Embodiments of partial update for a wireless display device include providing an update information message identifying a location of the partial update and the changed image data. A display source identifies changes in image data stored in a frame buffer, generates an update information message to identify the location of the changed image data and to provide the changed image data. A display sink receives the update information message and merges the changed image data with image data stored in a local frame buffer.

Abstract: In one embodiment, a display device comprises a graphics interface, an image processing system, an input device coupled to the image processing system to receive a screen capture signal and transmit the screen capture signal to the image processing system, and a storage subsystem coupled to the image processing system to store, in response to the screen capture signal, screen capture data generated by the image processing system.

Abstract: A scanning image display apparatus includes a light source unit (1) that emits a laser beam, a scanning mirror (3) that two-dimensionally scans the laser beam in a first direction and in a second direction that crosses the first direction at predetermined scanning frequencies, respectively, a frame buffer (5) that temporarily stores image data corresponding to images to be displayed on a display screen frame by frame, and a display controller (4) that generates display data used to modulate an intensity of the laser beam at a predetermined frame frequency using the read image data and causes the light source unit to emit the laser beam intensity-modulated based on the display data. The frame buffer is so configured that the respective image data of a plurality of different frames can be temporarily stored therein and read therefrom.

Abstract: Systems, apparatus, methods and computer program products are described below for rendering a graphical user interface by selectively compositing display contents. In general for each of one or more content producers, where each content producer is associated with content storage containing display content, display content for output is identified depending on the content consumer to which the graphical user interface is being rendered.

Abstract: A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source for supplying a first potential level; a second power source for supplying a second potential level, a third power source for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.

Abstract: The graphics co-processing technique includes rendering a frame of red, green, blue (RGB) data on a graphics processing unit on an unattached adapter. The frame of RGB data are converted on the graphics processing unit on the unattached adapter to luminance-color difference (YUV) data. The YUV data is copied from frame buffers of the graphics processing unit on the unattached adapter to buffers in system memory. The YUV data is copied from the buffers in the system memory to texture buffers of a graphics processing unit on a primary adapter. A frame of RGB data is recovered from the YUV data in the texture buffer of the graphics processing unit on the primary adapter. The recovered frame of RGB data may then be presented by the graphics processing unit on the primary adapter on the primary display.

Abstract: A multi-display apparatus includes a first body mounted with a first display, a second body mounted with a second display, a hinge connecting the first body and the second body, a first frame buffer corresponding to a first display, a second frame buffer corresponding to a second display, and a controller which manages the first and second frame buffers with a separate storing method which separately manages the first and second frame buffers and stores data or a united storing method which manages the first and second frame buffers as one virtual united frame buffer and stores data. The controller stores data on the first and second frame buffers by converting the managing method according to data features displayed on the first and second displays, and the first and second displays display the data stored in the first and second frame buffers respectively.

Abstract: A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. The method can also include performing a prioritized ordering of difference data. Furthermore, the method can include performing packing that includes utilizing varying sized bit fields to produce a lossy compressed representation.

Abstract: A method for dynamically adjusting a frame buffer resolution, the method comprising calculating a target scaling factor based upon a calculated average frame rate and incrementally changing a current scaling factor to reach the target scaling factor. The method includes calculating the target scaling factor based upon the average frame rate and a current scaling factor. The method includes adjusting a resolution of a frame of data rendered to the frame buffer according to the current scaling factor.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.

Abstract: One embodiment of the present invention sets forth a technique for using a shared memory to store hardware-managed virtual buffers. A circular buffer is allocated within a general-purpose multi-use cache for storage of primitive attribute data rather than having a dedicated buffer for the storage of the primitive attribute data. The general-purpose multi-use cache is also configured to store other graphics data sinces the space requirement for primitive attribute data storage is highly variable, depending on the number of attributes and the size of primitives. Entries in the circular buffer are allocated as needed and released and invalidated after the primitive attribute data has been consumed. An address to the circular buffer entry is transmitted along with primitive descriptors from object-space processing to the distributed processing in screen-space.

Abstract: Embodiments provide techniques for generation and outputting of display data. For instance, embodiments provide features involving frame data storage within display devices. Also, embodiments provide features involving the isolation of different user contexts to different frame buffers. Further, embodiments provide efficient techniques for saving frame data upon the transitioning between power states. Moreover, embodiments provide techniques for flexibly and dynamically allocating multiple display content to a physical display.

Abstract: A system implements rate control for encoding and decoding operations, for example, operations performed on slices of data such as image data. The system implements fine-grained bit rate control allowing for non-integer bit rates to be specified for the system. The non-integer values may allow the system to more accurately characterize a data rate of a communication link between a source and sink. The more accurate characterization may facilitate improved utilization of the communication link capacity.

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

Abstract: A method for controlling a display device that displays a frame buffer on a plurality of screens is provided. The method includes receiving a multi-screen mode execution command to display a single frame buffer on a plurality of screens, acquiring the frame buffer, splitting the frame buffer into a plurality of frame buffers to correspond to the plurality of screens, setting an offset for each of the plurality of split frame buffers, and displaying each of the plurality of split frame buffers on an associated one of the plurality of screens based on the set offset.

Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.

Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.

Abstract: Disclosed are a timing controller, a driving method thereof, and a display device using the same. The timing controller includes a memory configured to sequentially store input video data of respective frames, a determiner configured to compare the input video data of respective frames to determine whether a scene is changed, and a converter configured to, when it is determined by the determiner that the scene is changed, in the same scene section until the scene is changed and then changed to another scene, reduce luminance of the input video data included in the scene section, and output image data with reduced luminance.

Abstract: A technique for enhancing the efficiency and speed of data transmission within and across multiple, separate computer systems includes the use of an MPI library/engine. The MPI library/engine is configured to facilitate the transfer of data directly from one location to another location within the same computer system and/or on separate computer systems via a network connection. Data stored in one GPU buffer may be transferred directly to another GPU buffer without having to move the data into and out of system memory or other intermediate send and receive buffers.

Abstract: A first look-up table (10) outputs a result of dividing a horizontal component of a pixel address in the block by number of pixels in a horizontal component of the cell. A second look-up table (12) outputs a result of dividing a vertical component of a pixel address in the block by number of pixels in a vertical component of the cell. A third look-up table (14) outputs a residue as a result of dividing a horizontal component of a pixel address in the block by number of pixels in a horizontal component of the cell. A fourth look-up table (16) outputs a residue as a result of dividing a vertical component of a pixel address in the block by number of pixels in a vertical component of the cell. The output values of the first and second look-up tables (10,12) are addresses of the cell for burst access to the memory. The output values of the third and fourth look-up tables (14,16) are used as pixel addresses in the cell.

Abstract: The disclosed embodiments provide a system that drives a first display and a second display mirrored to the first display from a computer system. During operation, the system obtains a framebuffer update for a first framebuffer associated with the first display. Next, the system performs a color-correction operation on the framebuffer update to obtain a color-corrected framebuffer update that enables color output from the second display to substantially match color output from the first display. Finally, the system uses the framebuffer update to drive the first display, and uses the color-corrected framebuffer update to drive the second display.

Abstract: A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.

Abstract: The disclosed embodiments provide a system that facilitates driving a display in a computer system. During operation, the system receives an input video stream from a graphics source. The system directs the input video stream through a front memory buffer and a back memory buffer to produce an output video stream. While directing the input video stream through the set of memory buffers, the system writes a video frame from the input video stream into the back buffer, and concurrently drives the output video stream from a preceding video frame in the front buffer. When the writing of the video frame completes, the system switches buffers so that the back buffer becomes the front buffer, which drives the output video stream, and the front buffer becomes either a spare buffer or the back buffer, which receives a subsequent frame from the input video stream.

Abstract: A method and apparatus for displaying images is disclosed. The method of the invention includes the steps of: transferring a content of a first one of the display buffers to the display device; overwriting a second one of the display buffers with first image data, wherein the first image data represent data of updated pixels between two corresponding adjacent frames; obtaining a bit-map mask according to the updated pixels, wherein the bit-map mask indicates altered pixels for the two corresponding adjacent frames; and, then overwriting the second one of the display buffers with second image data from the other display buffers according to at least one bit-map mask.

Abstract: Real-time scanning and display of images is synchronized for ultrasound imaging. The scanning rate requirements for obtaining a frame of ultrasound data are determined. The video rate for imaging is adjusted as a function of the scanning rate.

Abstract: The subject matter of this specification can be embodied in, among other things, a method that includes computer-implemented graphics frame buffer process that establishes on a computing device a graphics frame buffer accessible to be written by an application process and to be read by a graphics server process. The method further comprises generating a plurality of control bits whose value or values control access to the frame buffer by the application process and the graphics server process and reading frames from the frame buffer using the value or values in the plurality of control bits.

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.

Abstract: Provided is a display control device capable of coping with high-resolution display readily in terms of conducting data write and read on a frame buffer memory in time for the timing of display. The display control device has a plurality of line buffers, and is arranged so that a writing process for writing, into part of the line buffers, display lines of display data from outside, and a reading process for reading out written display lines of display data from other line buffers can be conducted in parallel. In the display control device, display-line data read out from the line buffers are compressed and stored in the frame buffer memory. The compression-display data read out from the frame buffer memory are read out for each line, and decompressed into display lines of display data. The decompressed display data are used to drive signal electrodes of a display device.

Abstract: A display driver circuit comprises a frame memory comprising m main rows (m>1) and n dummy rows (0<n<m) corresponding to m horizontal display lines of a panel and configured to store received first frame data in m rows among the m main rows and the n dummy rows, and a memory control unit configured to control write and scan operations of the frame memory such that the first frame data is written from a write start row selected from among the m main rows and the n dummy rows.

Abstract: One embodiment of the present invention sets forth a technique for managing buffer entries in a tile-based architecture. The technique includes receiving a first plurality of graphics primitives and a first buffer address at which attributes associated with the first plurality of graphics primitives are stored. The technique further includes, for each tile included in a plurality of tiles, transmitting the first plurality of graphics primitives and the first buffer address to a screen space pipeline and receiving an acknowledgement from the screen space pipeline indicating that processing the first plurality of graphics primitives has completed. The technique further includes determining that processing the first plurality of graphics primitives has completed for a last tile included in the plurality of tiles and that the acknowledgement has been received for each tile included in the plurality of tiles, and, in response, releasing a buffer entry associated with the first buffer address.

Abstract: One embodiment of the present invention sets forth a technique for managing graphics processing resources in a tile-based architecture. The technique includes storing a release packet associated with a graphics processing resource in a buffer and initiating a replay of graphics primitives stored in the buffer and associated with the graphics processing resource. The technique further includes, for each tile included in a plurality of tiles and processed during the replay, reading the release packet and determining whether the tile is a last tile processed during the replay. The technique further includes determining not to transmit the release packet to a screen-space pipeline and continuing to read graphics data stored in the buffer if the tile is not the last tile to be processed during the replay, or transmitting the release packet to the screen-space pipeline if the tile is the last tile to be processed during the replay.

Abstract: One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released.

Abstract: A circuit device for preventing radiation emission in a portable terminal with two cameras is provided. The device includes a first camera, a second camera, a processor, and a 3-state buffer. The processor outputs a first control signal controlling an operation of the first camera and a second control signal controlling an operation of the second camera. The 3-state buffer electrically connects between the first camera and the processor, and connects or disconnects between the first camera and the processor depending on the first control signal.

Abstract: An apparatus, program product and method reuse static image data generated during rasterization of static geometry to reduce the processing overhead associated with rasterizing subsequent image frames. In particular, static image data generated one frame may be reused in a subsequent image frame such that the subsequent image frame is generated without having to re-rasterize the static geometry from the scene, i.e., with only the dynamic geometry rasterized. The resulting image frame includes dynamic image data generated as a result of rasterizing the dynamic geometry during that image frame, and static image data generated as a result of rasterizing the static image data during a prior image frame.

Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.

Abstract: An apparatus for buffering a signal delay between display devices in a multi-display environment includes: a delay setting unit for storing a delay time value and providing the delay time value to a signal input controller; a storage unit for storing and outputting an image signal according to the control of the signal input controller; and the signal input controller for controlling an input of an image signal from an image processor to a display module, the signal input controller controlling the image signal input from the image processor to be stored in the storage unit and then input to the display module after a delay as much as the delay time value. Since an image signal input time difference of all display devices is buffered to offset a display time difference of the display devices, it is possible to prevent image quality from deteriorating.