Abstract: In embodiments of display region refresh, a display panel has addressable display regions that display at different display refresh rates. Display data is buffered to update the addressable display regions, and subsequent display data is received to further update the addressable display regions. A display controller can determine display update deltas that indicate pending display updates based on a comparison of the display data to the subsequent display data. A first addressable display region can then be refreshed at display refresh rate based on a first display update delta that corresponds to the first addressable display region, and a second addressable display region can be refreshed at a different display refresh rate based on a second display update delta that corresponds to the second addressable display region.

Abstract: The embodiments of the present disclosure teach overlaying videos on a display device. The technique involves one or more buffers at input such as a first buffer (Primary Buffer) and an overlay buffer, a blitting module, a second buffer(Frame Buffer), and a display screen. The first buffer provides a first image data to the blitting module and the overlay buffer provides a second image data to the blitting module. The embodiments of the present disclosure demonstrate overlaying the second image on the first image with enhanced configurable functionality (like stretching, clipping, color keying, Alpha Blending and Raster Operation) if required, without modifying the Primary Buffer without the need of any overlay support in hardware.

Abstract: A graphics animation and compositing operations framework has a layer tree for interfacing with the application and a render tree for interfacing with a render engine. Layers in the layer tree can be content, windows, views, video, images, text, media, or other types of objects for an application's user interface. The application commits state changes to the layers of the layer tree. The application does not need to include explicit code for animating the changes to the layers. Instead, an animation is determined for animating the change in state by the framework which can define a set of predetermined animations based on motion, visibility, and transition. The determined animation is explicitly applied to the affected layers in the render tree. A render engine renders from the render tree into a frame buffer. Portions of the render tree changing relative to prior versions can be tracked to improve resource management.

Abstract: A method for monitoring a user's activities, wherein the activities comprising an output via a graphics device having a frame buffer. The method includes retrieving image data from the frame buffer, examining the image data, identifying an offensive attribute within the image data, and reacting to the attribute in a predefined way.

Abstract: A system and method are provided for changing a display refresh rate. A first register is provided for storing at least one first refresh parameter in association with a first refresh rate. Additionally, a second register is provided for storing at least one second refresh parameter in association with a second refresh rate. Furthermore, logic is in communication with the first register and the second register. Such logic is adopted for selecting the first refresh parameter or the second refresh parameter, for the purpose of reducing artifacts resulting from a change from the first refresh rate and the second refresh rate.

Abstract: A measurement tool overlay program that after initial placement in or around the object field, automatically identifies (in ‘expand’ mode) any distance between objects by other programs that are displayed on the screen relative to a starting point between the objects. Measures is provided of the dimensions of any object, or group of objects by accessing the picture elements (pixels) in the memory associated with the display screen. Alternate embodiments according to the present invention operate in ‘contract’ mode. In ‘contract’ mode, the present invention also provides the measurements of an end user-placed rectangular boundary around any given object(s), or distance between outside edges of clusters of object(s) immediately. The box will contract to the size (edge) of the area as defined by pixels, which may be part of one or more objects within the area and provide the dimensions automatically.

Abstract: Systems, apparatus, methods and computer program products for rendering a graphical user interface by selectively compositing display contents are described. In general, for each of one or more content producers, where each content producer is associated with content storage containing display content, display content for output is identified depending on the content consumer to which the graphical user interface is being rendered.

Abstract: Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.

Abstract: Provided is a screen display control device including: a compression unit which compresses image data; a rewritable video memory in which the data compressed by the compression unit of image data of one frame including line data (Y (Y: natural number) pixels/one line) of X (X: natural number) lines is written asynchronously with reading; an expansion unit which expands the compressed data which is periodically read from the video memory in synchronization with a frame period of a screen display, and restores original image data; a display unit which displays an image of the image data expanded and restored by the expansion unit; an input image data holding unit which holds input image data of one frame including line data (X pixels/one line) of Y lines by M (M: natural number, M<Y) lines; and a data replacement control unit which performs a replacement process.

Abstract: Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available.

Abstract: A display apparatus, and a display controller and an operating method thereof are provided. The display controller includes a controller, a buffer, and a compression/decompression unit. The controller receives an original frame from a host. The controller controls a display module to display the original frame provided by the host in a non-still frame mode. The compression/decompression unit is coupled between the buffer and the controller. The controller compresses the original frame to the buffer through the compression/decompression unit. If the controller operates in a still frame mode, the controller decompresses a compressed frame in the buffer to obtain a decompressed frame through the compression/decompression unit, and controls the display module to display the decompressed frame.

Abstract: An arbitration device receives a plurality of requests from a plurality of circuits, and grants access to one of the plurality of circuits. The arbitration device includes a sorter and an arbitrator. The sorter receives position information of an image signal including a plurality of image layers, and determines an access priority including a first group and a second group according to the position information. The arbitrator receives the access priority and at least one of the plurality of requests, and grants the access to one of the plurality of circuits according to the access priority and the at least one of the plurality of requests. In addition, each of the plurality of circuits generates data for each of the image layers correspondingly.

Abstract: A buffered scene-based non-uniformity correction method includes receiving a plurality of frames of video image data from an image detector; determining relative movement of a current image frame with respect to a previous image frame and responsive to a determination of substantial movement, adding the current image frame to a buffer memory sized to store a predetermined number of video frames; averaging pixel values of the frames in the buffer to determine a mean (or weighted mean) value for each pixel of a reference image; determining correction terms for each pixel of the current image frame by determining the difference between the current image frame pixel values and the corresponding reference image pixels; and correcting the current image frame using the correction terms. A scene-based non-uniformity correction system is also disclosed.

Abstract: A refresh rate adjustment method automatically adjusts a refresh rate of a monitor connected to a computer to a default refresh rate, in response that a detected keystroke signal is a predefined keystroke signal. The method further detects a refresh rate range that is supported by the monitor, detects a new refresh rate input signal from the input device, and determines if the new refresh rate falls within the refresh rate range that is supported by the monitor. If the new refresh rate falls within the refresh rate range that is supported by the monitor, the method automatically adjusts the refresh rate of the monitor with the new refresh rate. Otherwise, the method prompts a user to input the new refresh rate again by displaying a dialog box on the monitor.

Abstract: A computer-program product may have instructions that, when executed, cause a processor to perform operations including managing execution of application functions that access data in a shared buffer; determining if a first instruction that is stored at a first memory location causes, upon execution, data to be read from or written to the shared buffer; and when it is determined that the first instruction causes data to be read from or written to the shared buffer, 1) identify one or more replacement instructions to execute in place of the first instruction; 2) store the one or more replacement instructions; and 3) replace the first instruction at the first memory location with a second instruction that, when executed, causes the stored one or more replacement instructions to be executed.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: Modification to frame buffer memory information associated with a first display may be used to update information displayed on a second display. The first display may be mapped to a matrix of display areas. The modification to the frame buffer memory information may be detected be detecting write memory address. One or more display areas affected by the modification to the frame buffer memory information may be identified based on display parameters associated with the first display. Frame buffer memory information associated with the one or more affected display areas may be retrieved and compressed before being transmitted over a communication link to be displayed on the second display.

Abstract: A graphic processing apparatus includes a chunk assignment unit which assigns a block in which a maximum N number of polygons are located, out of a plurality of polygons drawn in a frame buffer which is divided into a plurality of blocks, to a maximum M number of chunk buffers; a chunk generation unit which generates pixel data of a polygon located in a block assigned to the chunk buffer, out of the N number of polygons, and writes the pixel data to the chunk buffer; and a chunk writing unit which writes the pixel data written in the chunk buffer to the frame buffer, wherein a processing phase, including processing by the chunk assignment unit, processing by the chunk generation unit, and processing by the chunk writing unit, is repeatedly executed for the plurality of polygons.

Abstract: Disclosed herein is a display device in which input data is written to a RAM as current frame data and read from the RAM as preceding frame data. Then, the current frame data and the preceding frame data are added up in a correction circuit and the result is subjected to an overdriving processing. After this, the processed (over-driven) data is assumed as current frame corrected data, which is then written to the RAM. The written corrected data is read from the RAM and subjected to a double-speed driving processing.

Abstract: A drawing control method, a drawing control apparatus, and a drawing control system for embedded system are provided. The present invention adopts an independent drawing control apparatus to control a drawing unit to draw a frame, and move the drawn frame to an external frame buffer in advance, and therefore the number of lines that can be drawn is not restricted by the capacity of the memory of the drawing unit. Further, the present invention employs a counter to accumulate a counting number upon each time completion of drawing frame or moving frame. Whenever the counting number is accumulated, the drawing unit is controlled to perform a next stage of frame drawing or frame moving. In this concern, the present invention eliminates the time for external accessing, and thus achieving parallel processing, and instant displaying.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A framework for performing graphics animation and compositing operations has a layer tree for interfacing with the application and a render tree for interfacing with a render engine. Layers in the layer tree can be content, windows, views, video, images, text, media, or any other type of object for a user interface of an application. The application commits change to the state of the layers of the layer tree. The application does not need to include explicit code for animating the changes to the layers. Instead, an animation is determined for animating the change in state. In determining the animation, the framework can define a set of predetermined animations based on motion, visibility, and transition. The determined animation is explicitly applied to the affected layers in the render tree. A render engine renders from the render tree into a frame buffer for display on the computer system.

Abstract: The present invention executes color correction that improves the feeling of depth of a 2D image with ease and by using a preexisting device. Input image data is first converted into brightness information by a brightness information calculation portion. The interest level within the image is then estimated by an interest level estimation portion based on that information. The vanishing point is then estimated by a vanishing point estimation portion. Next, a depth estimation portion estimates the degree of depth based on the distance from the vanishing point to a pixel i and the interest level of the pixel i, and calculates a depth correction gain value. A corrected image, obtained by controlling a depth correction image process based on the depth correction gain value, is converted to a predetermined image format and outputted by an output portion.

Abstract: Apparatus, systems and methods for low latency remote display rendering using tile-based rendering systems are disclosed. In one implementation, a system includes a network interface and a content source coupled to the network interface. The content source being capable of rendering at least one tile of a tiled image, encoding the at least one tile, and providing the at least one encoded tile to the network interface before all tiles of the tiled image are rendered.

Abstract: The invention described in this application is an image file system for the acquisition and storage of streaming digital image data onto persistent storage media in real time and for full-rate playback of streaming digital image data stored on persistent storage media. Input/output of non-streaming digital image data is processed in system memory with write/read operations buffered by native operating system input/output support. Input/output of streaming digital data is processed in high-speed streaming digital image data I/O memory with write/read operations buffered by a high-performance image buffer thread.

Abstract: An image processing apparatus including a frame doubling processing part for generating a doubled image signal, a false impulse drive processing part for outputting a current image signal after dividing the doubled image signal, a first frame memory for outputting the current image signal as a previous image signal delayed by one sub-frame, a correction processing part for correcting a gradation level of the current image signal after the previous image signal and the current image signal being input thereto, a second frame memory for outputting a delayed doubled image signal from the doubled image signal, and a movement detector for outputting a movement detection signal after the delayed doubled image signal and the doubled image signal being input thereto is provided, wherein the correction processing part corrects the gradation level of the current image signal when the movement detection signal is a signal indicating a dynamic image.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Abstract: A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of registers. A set of multiplexers has first data inputs coupled to the first set of registers, second data inputs coupled to the second set of registers, and select inputs. Logic circuitry is coupled to the output of the set of multiplexers and to the control inputs of the multiplexers, the control circuitry providing select information to the set of multiplexers and providing waveforms to the display panel to selectively display data from the first set of registers and the second set of registers in accordance with the select information.

Abstract: In a mobile device with a mobile device video driver that can be interdicted, such as a display telephone or PDA, a method and system for display on a remote video display device is provided involving forming an enhanced display image in an enhanced video frame buffer and reconstructing the display image in a duplicate enhanced video frame buffer in the remote video display device.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: A device includes a memory storing a persistence bit for each of a plurality of pixels of a display device, the persistence bit having a first value when a corresponding pixel should be illuminated for displaying a persistent image, and having a second value when the corresponding pixel should not be illuminated for the persistent image; a pseudorandom pixel value generator which during each video frame receives a seed value and generates pseudorandom pixel values for the plurality of pixels, each pseudorandom pixel value being not greater than a specified variable persistence value; a frame value generator outputting a frame value for each video frame; and a match detector which, during each video frame, compares the frame value to the pseudorandom pixel values for the plurality of pixels, and for each pixel where the comparison indicates a match, makes the persistence bit for the corresponding pixel have the second value.

Abstract: A computer system comprising a processor including a display controller operative to output display data and a clock signal, and a programmable logic device communicatively connected to the processor, the programmable logic device including a first FIFO (first in first out) module operative to receive display data from the display controller and output display data to a display device, a second FIFO module, a scaler module communicatively connected to the first FIFO module and the second FIFO module operative to scale the display data received from the first FIFO module and output the scaled display data to the second FIFO module, and a synchronization generator operative to receive the clock signal from the display controller and to control the first FIFO and the second FIFO.

Abstract: A dynamically reconfigurable heterogeneous systolic array is configured to process a first image frame, and to generate image processing primatives from the image frame, and to store the primatives and the corresponding image frame in a memory store. A characteristic of the image frame is determined. Based on the characteristic, the array is reconfigured to process a following image frame.

Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Abstract: A voltage initialization circuit for recording a preferred voltage includes a first terminal, a second input terminal, a first buffer circuit connected to a first node, a second buffer circuit connected to a second node, a ground connected to the first buffer circuit via the first node and connected to the second buffer circuit via the second node, a first resistor, and a second resistor. The first resistor is connected between the first input terminal and ground. The second resistor is connected between the second input terminal and ground.

Abstract: A memory section provides an input buffer capable of holding image data being a processing target of each processing by an image processing unit, and an output buffer capable of holding image data being a processing result. Through an input section, a user selects a plurality of kinds of processing to be executed by the image processing unit, and an execution sequence of the plurality of kinds of processing. A controller section reserves, based on information selected by a user through the input section, an input buffer and an output buffer for each processing in the memory section, sets an input-output connection relation between the buffers, and notifies, based on the set connection relation, the image processing unit of address information of the input buffer in the memory section and the output buffer for each processing sequentially executed by the image processing unit.

Abstract: Systems and methods for assembling pixel shader program threads for execution based on resource limitations of a multithreaded processor may improve processing throughput. Pixels to be processed by the pixel shader program are assembled into a launch group for processing by the multithreaded processor as multiple shader program threads. The pixels are assembled based on parameter storage resource limitations of the multithreaded processor so that common parameters shared by multiple pixels are not stored separately for each pixel. Therefore, the limited parameter storage resources are efficiently used, allowing more shader program threads to execute simultaneously.

Abstract: Change image detecting devices and methods are disclosed. In one example, a change image detecting device includes a change image detecting unit that selects a reference image and an image to be processed and a determination unit that compares an Na-th (‘Na’ is a natural number equal to or smaller than N) partial region of N (‘N’ is an integer equal to or larger than 2) partial regions. If the determination unit determines that there is a change, the change image detecting unit selects the image to be processed or an image, which is temporally later than the image to be processed, as a new reference image and detects the image to be processed or the image, which is temporally later than the image to be processed, as the change image.

Abstract: A driver and a driving method of a display device that includes a signal controller that processes image data input from an external circuit and a memory that is connected to the signal controller, wherein the signal controller includes a data converter that converts the image data and outputs the converted image data to the memory, and the data converter includes a data output unit that converts and outputs the image data and a data input unit that restores the image data input from the memory. Accordingly, the number of data transitions between the signal controller and the memory can be minimized to reduce current consumption and to reduce EMI.

Abstract: A system and method for resolving the blank screen issue when switching between graphics processing units. The system and method provide a graphics adapter LCD timing controller (Tcon) with a frame buffer specifically dedicated to storing previously presented screen data for use when switching graphic processing units. The system further includes a protocol comparator unit within a serial-to-parallel converter and a memory controller coupled to the protocol comparator.

Abstract: A system, method, and computer program product are provided for preventing display of unwanted content stored in a frame buffer. In use, unwanted content stored in a frame buffer is identified. Furthermore, display of the unwanted content is prevented based on the identification of the unwanted content.

Abstract: In the instant invention an improved method and device is described for utilizing the frame buffer of and electronic device with a display. The frame buffer is enlarged well beyond the dimensions of the display and the user is unable to change which region of the frame buffer is visible on the display. An application of the electronic device is allocated a region for its exclusive use that is within the portion of the frame buffer which is not visible to the user, and draws into it. The application may also take full advantage of accelerated drawing operations offered by the GPU. Compositing may be done by the application or by a window manager between regions of the enlarged frame buffer, visible on-screen, the portion off-screen, or any combination.

Abstract: A driver for driving a display panel and a method for reading/writing in a memory thereof and thin film transistor liquid crystal display (TFT-LCD) using the same are provided. The method of the present invention is a reading timing of memory which different than the prior reading timing of memory, so that, if using the method of the present invention in the driver even having only one memory, the tearing effect of the prior TFT-LCD can be solved and the whole power consumption thereof can also be reduced.

Abstract: A method for providing a combined TV/PC video stream for TV display is provided. A TV video chip having a video input port for receiving a PC monitor display signal and an input for receiving a TV broadcast signal is provided, as well as a PC graphics chip. A PC monitor display signal is sent from the PC graphics chip to the TV video chip. The TV video chip mixing the PC monitor display signal with the TV broadcast signal to generate a combined TV/PC video stream in a format for TV display. A method for generating a combined TV/PC video stream in a format for TV display is further provided. A stream of encoded TV frames is received and the encoded frames are decoded to provide a stream of decoded TV frames. The stream of decoded TV frames is stored into a memory. A PC monitor display signal is provided and is converted into a stream of PC frames. The stream of PC frames are stored into the memory.

Abstract: In a double buffering technique, a display controller refreshes a display from a first frame buffer by default and a processor draws into a second frame buffer. When the processor finishes drawing the second frame buffer, the processor signals the display controller that a new frame is ready in the second frame buffer. In response, the display controller refreshes the display from the second frame buffer and concurrently copies each line into the first frame buffer. After the display controller refreshes one entire frame, a complete copy of the frame is available in the first frame buffer so the display controller returns to refreshing the display from the first frame buffer and the processor is able to draw to the second frame buffer.

Abstract: A graphics processing apparatus 2 includes graphics processing pipelines 8. The graphics processing pipelines 8 include a programmable hardware stage 12, a pipeline memory 22 and writeback circuitry 16. Programmable resolving circuitry 18 is provided by the programmable hardware stage 12 within each pipeline and is responsive to one or more graphics program instructions to read pixel values at a first resolution generated within the pipeline memory 22 by pixel value generating circuitry 18 provided by the programmable hardware stage 12 and to perform a resolving operation upon these pixels values so as to generate pixel values at a second resolution. These pixel values at the second resolution are then written back to a frame buffer memory 6.

Abstract: The present application relates to method of driving an image display device comprising inserting a black data frame displaying black data between neighboring data frames alternately displaying left-eye data and right-eye data; comparing an nth frame corresponding to a current frame and an (n?2)th frame corresponding to a previous frame with each other when the data frames are input, reading a compensation value according to the comparison result from a lookup table and modulating input data of the nth frame using the read compensation value to output a modulated data; and bypassing data corresponding to the black data without modulating the data when the black data is input to output a bypass data, the application also relates to said image display device.

Abstract: A framework for performing graphics animation and compositing operations has a layer tree for interfacing with the application and a render tree for interfacing with a render engine. Layers in the layer tree can be content, windows, views, video, images, text, media, or any other type of object for a user interface of an application. The application commits change to the state of the layers of the layer tree. The application does not need to include explicit code for animating the changes to the layers. Instead, an animation is determined for animating the change in state. In determining the animation, the framework can define a set of predetermined animations based on motion, visibility, and transition. The determined animation is explicitly applied to the affected layers in the render tree. A render engine renders from the render tree into a frame buffer for display on the computer system.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.