Abstract: A method of operation of a texturing/shading unit in a GPU pipeline is used for efficient convolution operations. The method uses texture hardware to collectively fetch all the texels required to calculate properties for a group of output pixels without any duplication. The method then bypasses bilinear filter hardware in the texture hardware and passes the fetched and unfiltered texel data from the texture hardware unit to shader hardware in the texturing/shading unit. The shader hardware uses the fetched texel data to perform a plurality of convolution operations to calculate the properties of each of the output pixel.

Abstract: One or more shader processor inputs (SPIs) provide work items from a thread group for execution on one or more shader engines. A command processor selectively dispatches the work items to the SPIs based on a size of the thread group and a format of cache lines of a cache implemented in the one or more shader engines. The command processor operates in a tile mode in which the command processor schedules the work items in multidimensional blocks that correspond to the format of the cache lines. In some cases, the format of the cache lines is determined by a texture surface format and a swizzle mode for storing texture data. The SPIs (or corresponding drivers) adaptively select wave size, tile size, and wave walk mode based on thread group size, UAV surface format. The SPIs adaptively launch and schedule waves in a thread group based on selected file size, wave walk mode, and wave size to improve cache locality, reduce memory access, and create address pattern to improve memory efficiency.

Abstract: Techniques are disclosed herein for interleaving textures. In the disclosed techniques, multiple textures that would otherwise be accessed separately are interleaved into a single, interleaved texture that can be used to access the multiple textures together. The interleaved texture can include alternating blocks from the multiple textures. The interleaved texture can be generated when the multiple textures are being loaded into memory. Further, the interleaved texture can be accessed using multiple texture headers that are associated with different textures in the interleaved texture. Each of texture headers includes a stride indicating the distance between two blocks from a same texture in the interleaved texture.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may modify at least one texture memory object to support a data structure for one or more tensor objects. The apparatus may also determine one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object. Additionally, the apparatus may access data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction. The apparatus may also execute the at least one data instruction based on the accessed data associated with the one or more tensor objects.

Abstract: In implementations of path-constrained drawing with visual properties based on a drawing tool, a digital artwork editing system includes a user interface in which a constraint path can be designated in a digital artwork. A stroke input can be sampled as it is drawn with a drawing tool and for each processing interval of the stroke input, a start point of the stroke input and a tangent line to the constraint path is determined. An end point of the stroke input is projected onto a parallel line that is through the start point and parallel to the tangent line, and a stroke is rendered along this line. Hence, the stroke is rendered based on the stroke input in a piecewise linear fashion, simultaneously constrained by the constraint path and rendered based on how the drawing tool is used.

Abstract: There are disclosed various methods, apparatuses and computer program products for volumetric video encoding and decoding. In some embodiments, projection data generated from a projection geometry of an object in a texture picture of volumetric video data is obtained. One or more property of the projection data is examined to determine whether at least one predetermined condition is fulfilled and if the examining reveals that at least one predetermined condition is fulfilled, at least one compression parameter for the projection data is adapted. The projection data is compressed by using the at least one compression parameter.

Abstract: The invention relates to methods, apparatuses, systems and computer program products for coding volumetric video. A first texture picture coded, said first texture picture comprising a first projection of first volumetric texture data of a first source volume of a scene model and a second projection of second volumetric texture data of said first source volume of said scene model, said first projection being from said first source volume to a first projection surface, and said second projection being from said first source volume to a second projection surface, said second volumetric texture data having been obtained by removing at least a part of said first volumetric texture data that has been successfully projected in said first projection. A a first geometry picture is coded, said geometry picture representing a mapping of said first projection surface to said first source volume and a mapping of said second projection surface to said first source volume.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for processing a video frame. A specific embodiment of the method includes: receiving a video frame set; selecting a video frame from the video frame set, and performing following processing: creating a pixel buffer object newly; reading pixel data of the selected video frame from a frame buffer corresponding to a central processing unit, and writing the read pixel data into the newly created pixel buffer object; storing the written pixel buffer object into a pixel buffer object queue; determining whether an unselected video frame is present in the video frame set; and storing the video frame set in response to determining no unselected video frame being present in the video frame set.

Abstract: A system and method for abstracting objects in a virtual universe (VU) deployment is provided. The system and method abstracts VU objects for editing in a common abstraction utility and for deploying to one or more VU grids containing one or more VU architectures and/or platforms (servers). The method can be implemented in a computer infrastructure having programming instructions operable to: obtain an object associated with a first virtual universe server; translate the object with syntax specific to at least a second virtual universe server, the syntax being different than that used with the first virtual universe server; and deploy the translated object to the second virtual universe server.

Abstract: Techniques for improving memory utilization for communication between stages of a graphics processing pipeline are disclosed. The techniques include analyzing output instructions of a first shader program to determine whether any such output instructions output some data that is not used by a second shader program. The compiler performs data packing if gaps exist between used output data to reduce memory footprint. The compiler generates optimized output instructions in the first shader program and optimized input instructions in the second shader program to output the used data from the first shader program and input that data in the second shader program in a packed format based on information about usage of output data and data packing. If needed, the compiler inserts instructions to perform runtime checking to identify unused output data of the first shader program based on information not known at compile-time.

Abstract: An image processing apparatus includes a correcting unit and a pasting unit. The correcting unit corrects a dynamic range of a second image in accordance with pixel information of a region. The second image is pasted on a first image serving as a destination for pasting. The region is in the first image and is to be in contact with the second image. The pasting unit pastes the second image on the first image after the correction of the dynamic range. The second image has pixel information. The pixel information is corrected in such a manner that a boundary with the first image is inconspicuously viewed.

Abstract: Systems, apparatuses, and methods for implementing a tag accelerator cache are disclosed. A system includes at least a data cache and a control unit coupled to the data cache via a memory controller. The control unit includes a tag accelerator cache (TAC) for caching tag blocks fetched from the data cache. The data cache is organized such that multiple tags are retrieved in a single access. This allows hiding the tag latency penalty for future accesses to neighboring tags and improves cache bandwidth. When a tag block is fetched from the data cache, the tag block is cached in the TAC. Memory requests received by the control unit first lookup the TAC before being forwarded to the data cache. Due to the presence of spatial locality in applications, the TAC can filter out a large percentage of tag accesses to the data cache, resulting in latency and bandwidth savings.

Abstract: In some examples, a media controller includes a buffer and controller circuitry. The controller circuitry may receive, from a memory device linked to the media controller, an indication of a number of memory subunits that the memory device is divided into. The controller circuitry may also allocate, within the buffer, a number of logical memory buffers for the memory device greater than the number of memory subunits and indicate to a memory controller that a number of memory units accessible for the memory device is the number of logical memory buffers.

Abstract: Systems, apparatus, articles, and methods are described including operations to transpose image data between a linear-type storage format and a Y-tiled-type storage format.

Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.

Abstract: Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.

Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.

Abstract: In various embodiments, methods and systems for intelligent streaming of game content based on the level of interactivity of the game content are provided. The level of interactivity of game content is determined using techniques that classify the level of interactivity. The level of interactivity is defined for different components of game content. Streaming techniques are associated with game content having specific levels of interactivity. An edge computing infrastructure may facilitate intelligent streaming in that game assets classified as prefetch game assets or stream game assets are associated with prefetch instructions. The prefetch instructions are communicated from a game server to a game platform to instruct the game platform to prefetch a prefetch game asset to the edge computing infrastructure in advance of an anticipated game context in which the prefetch game asset is used. During the anticipated game context, the assets are retrieved for output at the game platform.

Abstract: A tile identifier may be assigned to tiles processed in order in a pixel shader. When the tiles are processed out of order in the pixel shader, the tile identifier may be used to determine when rendering is complete and a tile may be discarded.

Abstract: A method of variable rate compression of image data in an image pipeline of a graphics processing system, the method includes identifying, by a processor of the graphics processing system, a set of cTiles associated with the image data, each cTile including a plurality of pixels, for each cTile of the set of cTiles identifying, by the processor, a pivot pixel from among the plurality of pixels, identifying, by the processor, a compression type of the cTile by comparing, bit-by-bit , pixels within the cTile with the pivot pixel, and compressing, by the processor, the cTile based on the identified compression type, and generating, by the processor, a metadata entry associated with the set of cTiles, the metadata entry indicating the compression type of each one of the set of cTiles and defining a mapping between an uncompressed address space of the set of cTiles and a compressed address space.

Abstract: Cache controller (120) for use in a system (180) comprising an image client (100) and an image server (140), the image client enabling a user to navigate through image data having at least three spatial dimensions by displaying views of the image data that are obtained from the image server in dependence on navigation requests of the user, and the cache controller comprising a processor (122) configured for obtaining content data indicative of a content shown in a current view of the image client (100), the current view representing a first viewpoint in the three spatial dimensions of the image data, the processor being further configured for predicting a view request of the image client in dependence on the content data, the view request corresponding to a view representing a second viewpoint in the three spatial dimensions of the image data, and a communication means (124) for obtaining the view from the image server in dependence on the view request, and for caching the view in a cache (130).

Abstract: A palette compressed representation may be stored in the index bits, when that is possible. The savings are considerable in some embodiments. In uncompressed mode, the data uses 2304 (2048+256) bits, and in compressed mode, the data uses 1280 bits. However, with this technique, the data only uses the index bits, (e.g. 256 bits) with a 5:1 compression improvement over the already compressed representation, and with respect to the uncompressed representation it is a 9:1 compression ratio.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: The avionics display system is for displaying a scene in an aircraft cockpit. The avionics display system includes a central processing unit CPU, a graphics processing unit GPU operably coupled to the CPU, and a display. The GPU comprises at least one vertex shader, and the CPU is configured to provide vertex data representing at least one graphics primitive to the at least one vertex shader and to call the at least one vertex shader in order to render the at least one graphics primitive, representing at least a part of the scene, into a frame buffer. The display is operably coupled to the frame buffer and displays the scene. The system architecture of the avionics display system simplifies the coding process for the developer and also speeds up image processing in comparison to conventional systems.

Abstract: According to some embodiments, a graphics processor may abort a workload without requiring changes to the kernel code compilation or intruding upon graphics processing unit execution. Instead, it is possible to only read the predicate state once before starting and once before restarting a workload that has been preempted because the user wishes to abort the work. This avoids the need to read from each execution unit, reducing the drain on memory bandwidth and increasing power and performance in some embodiments.

Abstract: Systems and methods for reducing the amount of texture cache memory needed to store a texture atlas by using uniquely grouped refined triangles to create each texture atlas.

Abstract: A method of event-based down sampling includes receiving multiple sensor events corresponding to addresses and time stamps. The method further includes spatially down sampling the addresses based on the time stamps and the addresses. The method may also include updating a pixel value for each of the multiple sensor events based on the down sampling.

Abstract: Systems and methods for rendering 2D grids using texture mapping and fragment shaders.

Abstract: A signal processing system for motion pictures includes a signal processing module, a cache, an analysis module and a control module. The signal processing module performs a signal processing process on motion picture data. The cache temporarily stores a set of reference data that is required for processing the motion picture during the signal processing process. The analysis module generates cache miss analysis information associated with the signal processing process and the cache. The control module determines an index content configuration of the cache according to the cache miss analysis information.

Abstract: An apparatus and method are described for implementing flexible finite differences in a graphics processor. For example, one embodiment of a graphics processor comprises: pixel shading logic to perform pixel shading operations on pixels associated with a rasterized primitive using covered pixels and uncovered pixels; and helper pixel selection logic to select helper pixels in the rasterized primitive, the helper pixels to be used by the pixel sharing logic for gradient computations, wherein for one or more of the covered pixels, the helper pixel selection logic attempts to identify one or more suitable covered helper pixels and, if no suitable covered helper pixels exist, identifies one or more uncovered helper pixels.

Abstract: A system and method for performing computer algorithms. The system includes a graphics pipeline operable to perform graphics processing and an engine operable to perform at least one of a correlation determination and a convolution determination for the graphics pipeline. The graphics pipeline is further operable to execute general computing tasks. The engine comprises a plurality of functional units operable to be configured to perform at least one of the correlation determination and the convolution determination. In one embodiment, the engine is coupled to the graphics pipeline. The system further includes a configuration module operable to configure the engine to perform at least one of the correlation determination and the convolution determination.

Abstract: An engine decompresses texture data belonging to a virtual texture stored in processor readable memory so that decompressed texture data may be used to update a selected sub-image of a large texture image used to render a CGI. The updated sub-image may be at any location in the larger texture image. A processor executes an application to provide control information to the engine. The control information may include commands to decode compressed texture data at source addresses and provide a stream of decompressed virtual texture data to selected sub-image destination addresses in a texture buffer used for rendering a CGI. Similarly, the engine may compress texture sub-image information and store the compressed result at a destination address.

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Abstract: A graphics processing pipeline includes a vertex transformation stage 14 having a vertex transformation cache 20. If a request to transform vertex data is received and the vertex transformation cache 20 indicates that the transformed vertex data for that received request has already been generated, then a pointer to that previously generated transformed vertex data is output within a result data stream in place of the transform vertex data. The transform vertex data is stored to a memory 10 before being retrieved as required by a rasterization stage 16.

Abstract: A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit also stores the first set of the attributes in a first portion of a memory system that can be read by the downstream shader unit and any shader units that are downstream in the processing pipeline relative to the upstream shader unit. In one embodiment, the processing unit is coupled between the upstream shader unit and the downstream shader unit.

Abstract: An apparatus and method are provided. A hierarchical navigation database with multiple levels including tiles is defined. Link data records representative of a road segments are stored in the hierarchical navigation database. A lower level tile containing a starting point data record of a route is identified. A link data record crossing the lower level tile border is identified. Whether the identified link data record also crosses a tile border of a higher level tile is determined. If the identified link data record crosses a tile border of a higher level tile, whether the higher level tile includes a destination point record is determined. Unless the higher level tile is determined to include the destination point record, a next link data record is determined in the route from the higher level.

Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.

Abstract: According to the present invention, even when the operation requested through the second transmission path (or first transmission path) cannot be performed, it is possible to perform the requested operation by using the function of the device coupled to the first transmission path (or second transmission path).

Abstract: The present document describes a method and system for expediting bilinear filtering of textures, by reducing the number of data load operations. The method expands the original data layout with additional borders containing replicated texels. The replicated texels correspond either to wrapped-around texels for two-dimensional textures or neighboring faces in cube textures. Therefore, a 2×2 filter kernel for bilinear filtering is built which requires only one texel address to be computed, with all texel data readable with two load operations which are a predetermined stride apart. Different addressing modes are implemented by adjusting the sampling locus.

Abstract: Systems, apparatus, articles, and methods are described including operations to communicate synchronization notifications between a co-processor graphic data producer and a co-processor graphic data consumer via a direct link without passing such communications through the central processing unit.

Abstract: Exemplary embodiments disclose a method of projecting an image onto a surface of a three-dimensional (3D) electronic map. The method includes: extracting nearest intersecting points for each of a plurality of virtual view angle vectors with respect to a position of a virtual photographing apparatus and a plurality of polygons that constitute the 3D electronic map; comparing 3D coordinates of the extracted nearest intersecting points and 3D coordinates of a plurality of pixels constituting the plurality of polygons to select pixels that are within a range of the 3D coordinates of the extracted nearest intersecting points; converting 3D coordinates of the selected pixels to two-dimensional (2D) coordinates to display the selected pixels on a 2D display; and superimposing an input image on top of the selected pixels to output the superimposed image in real-time.

Abstract: A device selectively loads map tiles into its memory while re-using others. As a user chooses different sections of a master map to be displayed, the device determines an intersection between the formerly and currently viewed sections. The device copies selected references to map tiles in the intersection, with some re-indexing, from an array for the formerly displayed section into an array for the newly displayed section. The view of the map might be a three-dimensional perspective view of a two-dimensional surface. The device can create bounding boxes around polygonal perimeters of the viewed areas. The bounding boxes are divided into rectangles corresponding to the tiles located on the master map. The device determines which rectangles within the bounding boxes both (a) contain portions of their respective polygons and (b) overlap each other respective to their locations on the master map. The device already stores map tiles for those rectangles.

Abstract: FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table.

Abstract: Various embodiments for improving hash index key lookup caching performance in a computing environment are provided. In one embodiment, for a cached fingerprint map having a plurality of entries corresponding to a plurality of data fingerprints, reference count information is used to determine a length of time to retain the plurality of entries in cache. Those of the plurality of entries having a higher reference counts are retained longer than those having lower reference counts.

Abstract: A method and system for reconstructing an image displayed on an electronic device connected to a network, to be a high resolution image. The method of reconstructing a selected area of the image displayed on the electronic device connected to a network, to be a high resolution image, includes: receiving a request to expand the selected area; collecting images including the selected area from the Internet; correcting the selected area to have a high resolution while expanding the selected area based on the collected images; and displaying the image expanded to have a high resolution on the electronic device.

Abstract: Each block of texture data elements is encoded as a block of texture data that includes a set of integer values to be used to generate a set of base data values for the block, and a set of index values indicating how to use the base data values to generate data values for the texture data elements that the block represents. The integer values and the index values are both encoded in an encoded texture data block using a combination of base-n values, where n is greater than two, and base-2 values. Predefined bit representations are used to represent plural base-n values (n>2) collectively, and the bits of the bit representations representing the base-n values are interleaved with bits representing the base-2 values in the encoded texture data block.

Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.

Abstract: A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.

Abstract: Methods are provided for reordering operations in execution of an effect graph by graphics processing unit. Memory availability is evaluated for storing images rendered using the effect graph. Memory is allocated for multiple parallel intermediate textures that store images. Operations that write to these textures are executed. It is then determined that there is not sufficient memory to perform additional parallel operations. The memory currently allocated is flushed, and memory for an upper-level texture is allocated. The operations that write pixels to the upper-level texture are executed.

Abstract: A system, method, and computer program product are provided for mapping tiles to physical memory locations. In use, a plurality of virtual tiles associated with a texture is identified. Additionally, a request to perform a mapping of the plurality of virtual tiles to one or more physical memory locations is received. Further, the plurality of virtual tiles is mapped to the one or more physical memory locations, utilizing a page table.