Abstract: A method and apparatus for angular invariant texture level of detail calculation is disclosed. The method includes a determination for a LOD that determines angular invariant LODs that result in efficient ASIC hardware implementation.

Abstract: A method for a computer system including receiving a file comprising textures including a first and a second texture, and metadata, wherein the first texture need not have a predetermined geometric relationship to the second texture, wherein the metadata includes identifiers associated with textures and includes adjacency data, associating the first texture with a first location on an object in response to an identifier associated with the first texture, associating the second texture with a second location on the object in response to an identifier associated with the second texture, determining an edge of the first texture is adjacent to an edge of the second texture in response to the adjacency data, and performing a rendering operation with respect to the first and the second surface on the object to determine rendering data in response to the first texture and to the second texture.

Abstract: An apparatus for providing enhanced radar video processing may include a processing element. The processing element may be configured to receive, from a state table that is oriented in a fixed orientation, data based on a radar return, to store a texture corresponding to an image based on the received data, the texture being oriented with respect to a center of a radar sweep, to define a plurality of adjacent vertex buffers, and to map the texture to at least one of the vertex buffers in which portions of the texture are capable of being scrambled within at least one of the vertex buffers.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of color values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colors of the individual texture elements using that generated set of colors. As well as the individual texture data blocks, a header data block encoding a base set of colors is generated. This base color set defines a set of colors that is used to generate the colors to be used when reproducing each individual encoded texture data block.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A texture sampler is implemented using a shader language. The shader compiler is used to compile the texture sampler to a target machine based on sampler state, sampler operation, and other static factors input values provided to the texture sampler. The shaders such as a vertex shader, geometry shader, pixel shader, hull shader, domain shader, and a compute shader may call one or more texture samplers while the shaders are invoked. The one or more texture samplers, which are a piece of software code may generate texture samples from the texture data and provide such texture samples to the shaders. The shaders generate shading effects on graphics elements using a texture samples. The graphics elements along with the shading effects are then rendered on a display device.

Abstract: Methods, apparatuses, and systems for sketch-based design, construction, and modification of three-dimensional geometry, including a computer drawing system, comprising a two dimensional input device, a display device, and a processor connected to the input device and the display device. The processor includes memory containing computer readable instructions which, when executed, cause the processor to define a three dimensional shape model, receive from the two dimensional input device an input indicative of a two dimensional hand drawn element, map the two dimensional hand drawn element to a corresponding portion of the three dimensional shape model, and modify the corresponding portion of the three dimensional shape model to resemble the two dimensional hand drawn element.

Abstract: Apparatus, systems and methods for the simplification of 3D texture address computations based on aligned, non-perspective objects are disclosed. For example, a method is disclosed including receiving a texture address of a first pixel and determining a texture address of a second pixel by applying at least one offset to the texture address of the first pixel. Other implementations are also disclosed.

Abstract: Methods and apparatuses for scheduling and storing media creation are described. Methods and apparatuses for rendering a plurality of vector graphic objects on a display are also described.

Abstract: Methods and apparatus for subdividing a shader program into regions or “phases” of instructions identifiable by phase identifiers (IDs) inserted into the shader program are provided. The phase IDs may be used to constrain execution of the shader program to prohibit texture fetches in later phases from being executed before a texture fetch in a current phase has completed. Other operations (e.g., math operations) within the current phase, however, may be allowed to execute while waiting for the current phase texture fetch to complete.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A texture synthesis device, which has a determinator for determining a prioritization among regions to be synthesized of an area to be synthesized, as a function of image information in an area adjacent to the area to be synthesized, and a synthesizer for synthesizing the regions to be synthesized in an order that depends on the prioritization.

Abstract: Embodiments of the invention provide a renderer-agnostic method for representing materials independently from an underlying rendering engine. Advantageously, materials libraries may be extended with new materials for rendering with an existing rendering engine and implementation. Also, new rendering engines and implementations may be added for existing materials. Thus, at run-time, rather than limiting the rendering to being performed on a pre-determined rendering engine, the rendering application may efficiently and conveniently manage rendering a graphics scene on a plurality of rendering engines or implementations.

Abstract: A method for assisting in data calculation by using a display card: In the present method, input data stored in a system memory is transformed into texture data, which is then stored in a display memory of the display card. Then, a Graphic processing unit (GPU) of the display card is used for executing a texture calculation to the texture data, and a result of the texture calculation is stored in a display target of the display memory. Finally, the display target is outputted to the system memory as the output data. Accordingly, a part of calculation tasks of a central processing unit (CPU) can be given to the GPU of the display card when the CPU is in a high usage rate, so as to reduce a calculation burden of the CPU.

Abstract: A computer graphics rendering apparatus according to an embodiment of the present invention generates a screen image, using plural texture images having different mipmap levels. The apparatus generates a normalized texture coordinate of a texture image, generates, from the normalized texture coordinate of the texture image, a texel coordinate of a texel in the texture image, according to a mipmap level of the texture image, and generates, regarding an image block in the texture image, an index value indicating a cache line corresponding to the image block, using a texel coordinate of a texel in the image block. The apparatus generates the index value such that index values of image blocks in the same position are different, between two texture images having mipmap levels adjacent to each other.

Abstract: A processing pipeline employs one or more bypass caches to allow a transaction that is dependent on the results of a prior transaction to be processed before the prior transaction has completed processing. Each bypass cache is coupled to the input and the output of one of the sections of the processing pipeline so that results of a transaction from that section can be written into or read from the bypass cache as soon as that transaction has been completely processed through that section. With such a configuration, more transactions can be processed by the processing pipeline in a shorter amount of time. This is especially true for very deep pipelines.

Abstract: A method comprises encoding information in a texture map, and enhancing texturing utilizing the information, where the information identifies at least one region in at least one texture. Additionally, a texture data structure is embodied on a non-transitory computer readable medium and comprises a texture map with encoded information that identifies at least one region in at least one texture. In addition, an apparatus comprises a processor for encoding information in a texture map to enhance texturing, where the information identifies at least one region in at least one texture.

Abstract: A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of color values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colors of the individual texture elements using that generated set of colors. As well as the individual texture data blocks, a header data block encoding a base set of colors is generated. This base color set defines a set of colors that is used to generate the colors to be used when reproducing each individual encoded texture data block.

Abstract: A method for a computer system including receiving a file comprising textures including a first and a second texture, and metadata, wherein the first texture need not have a predetermined geometric relationship to the second texture, wherein the metadata includes identifiers associated with textures and includes adjacency data, associating the first texture with a first location on an object in response to an identifier associated with the first texture, associating the second texture with a second location on the object in response to an identifier associated with the second texture, determining an edge of the first texture is adjacent to an edge of the second texture in response to the adjacency data, and performing a rendering operation with respect to the first and the second surface on the object to determine rendering data in response to the first texture and to the second texture.

Abstract: A method for multiple queue output buffering in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels related to the graphics primitive. Each tile is then rasterized to determine related sub-portions of each tile. The related sub-portions are transferred to a plurality of output queues. The related sub-portions are subsequently output on a per queue basis and on a per clock cycle basis.

Abstract: Textures are transferred between different object models using a point cloud. In a first phase, a point cloud in 3-D space is created to represent a texture map as applied to a first, or “source,” object model. In a second phase, a value for a target texel of a texture map associated with a second, or “target,” object model, is determined by identifying the 3-D location on a surface defined by the target object model that maps to the location of the target texel and assigning a value based on the nearest point (or points) to that location in the 3-D point cloud. To the extent that differences between the source and target object models are minor, the texture transfer can be accomplished without loss of information or manual cleanup.

Abstract: Techniques for dynamically configuring a texture cache are disclosed. During a texture mapping process of a three-dimensional (3D) graphics pipeline, if the batch is for single texture mapping, the texture cache is configured as a n-way set-associative texture cache. However, if the batch is for multi-texture mapping the n-way set-associated texture cache is divided into at n/M-way set-associative sub-caches where n and M are integers greater than 1 and n is divisible by M.

Abstract: A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.

Abstract: A method for recording media generated within a virtual world from user selectable locations that chosen by a participant of the virtual world without requiring a link with a location of their avatar. The media may be audio or video or still images generated or rendered within the virtual world. The method allows a user to insert independent movie recorders in a virtual world with the cameras associated with such recorders being independent from the avatar and each other. A virtual world generator may include a movie recorder module that allows a participant of the virtual world to insert a movie recorder into the world. The user may also change its position to selectively position a camera on the front portion of the movie recorder body and change the orientation of the movie recorder to allow the user to determine the scene within the world recorded by the camera.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.

Abstract: Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.

Abstract: One embodiment of the present invention sets forth a technique for improving the flexibility and programmability of a graphics pipeline by enabling full access to integer texture maps within a graphics processing unit (GPU). A new mechanism for loading and unloading integer texture images is disclosed that enables the shader units within the GPU to have full access to integer values stored within an integer image buffer in a GPU local memory. New integer formats are added to the graphics API that indicate that data should be loaded and processed without the prior art conversion to a floating-point representation, thereby enabling the use of these new integer data types.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.

Abstract: A graphics processing unit calculates transformation matrices for changes to the position and orientation of objects. The graphics processing unit applies the transformation matrices to vertices of objects to be rendered.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at least one mip level. Furthermore, the graphics processing system comprises a texture cache, wherein the texture cache is coupled to the texture management unit and configured to receive the organized texture map data from the texture management unit.

Abstract: Systems and methods are provided for variable source rate sampling in connection with image rendering, which accumulate and resolve over all samples forward mapped to each pixel bin. In accordance with the invention, the textured surface to be rendered is sampled, or oversampled, at a variable rate that reflects variations in frequency among different regions, taking into account any transformation that will be applied to the surface prior to rendering and the view parameters of the display device, thus ensuring that each bin of the rendering process receives at least a predetermined minimum number of samples. A variety of image processing applications are contemplated wherein variable rate source sampling, and accumulation and resolution of forward mapped point samples can be applied, ranging from 3-D graphics applications to applications wherein images recorded in a recording/storage environment are mapped to the arbitrary requirements of a display environment.

Abstract: An automatic 3D modeling system and method are described in which a 3D model may be generated from a picture or other image. For example, a 3D model for a face of a person may be automatically generated. The system and method also permits gestures/behaviors associated with a 3D model to automatically generated so that the gestures/behaviors may be applied to any 3D models.

Abstract: Circuits, methods, and apparatus that store a large number of texture states in an efficient manner. A level-one texture cache includes cache lines that are distributed throughout a texture pipeline, where each cache line stores a texture state. The cache lines can be updated by retrieving data from a second-level texture state cache, which in turn is updated from a frame buffer or graphics memory. The second-level texture state cache can prefetch texture states using a list of textures that are needed for a shader program or program portion.

Abstract: A multi-threaded graphics processor is configured to use to extrapolate low resolution mipmaps stored in physical memory to produce extrapolated texture values while high resolution nonresident mipmaps are retrieved from a high latency storage resource and converted into resident mipmaps. The extrapolated texture values provide an improved image that appears sharper compared with using the low resolution mipmap level texture data in place of the temporarily unavailable high resolution mipmap level texture data. An extrapolation threshold LOD is used to determine when extrapolated magnification or minification texture filtering is used. The extrapolation threshold LOD may be used to smoothly transition from using extrapolated filtering to using interpolated filtering when a nonresident mipmap is converted to a resident mipmap.

Abstract: A graphics processor 1 includes after its tile rendering logic 40, a transaction elimination unit 5 that includes data block generation logic 41 and block comparison logic 43. The block generation logic 41 generates data blocks from the rendered tiles produced by the tile rendering logic 40. The data blocks are then stored in buffers 42. Comparison logic 43 then compares a new data block with the previous data block (which will already be stored in the buffers 42), and generates an output metadata bit indicating whether the blocks can be considered to be the same or not, on the basis of the comparison. The meta-data output bits are stored appropriately in a meta-data bitmap 45 in main memory 2 that is associated with the output data array in question. If the blocks are determined to be different by the comparison logic then the new data block is written from the buffers 42 to the frame buffer 44 in the main memory 2.

Abstract: An object collation method comprising a registration procedure for registering the registered data of a registered object in a database, and a collation procedure for collating the input image of a target object with the registered data. The registration procedure includes a step of storing the three-dimensional shape of the registered object and a texture space defined by a texture group indicating the luminance and/or color information of each position of the object surface under various illumination conditions. The collation procedure includes the steps of: generating an illumination fluctuation space defined by the image group under the various illumination conditions, at the location and position of the target object in the input image from the three-dimensional shape and the texture space; and collating the target object and the registered object based on the distance between the illumination fluctuation space and the input image.

Abstract: A method and system for implementing transfers of texture data in a computer system. The method includes the step of accessing a first block of texture data in a low latency memory, the first block having a predetermined size and accessing a second block of texture data in high latency memory, the second block having the predetermined size. The first block of texture data is copied from the low latency memory to a transfer space in high latency memory having the predetermined size. The second block of texture data is written from the high latency memory to the low latency memory, wherein the second block overwrites the first block. What used to be the transfer space is now treated as the first block now placed in high latency memory, and what used to be the second block is now treated to be the new transfer space.

Abstract: A method and system for performing a texture operation with user-specified offset positions are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of deriving a first destined texel position based on an original sample position associated with a pixel projected in a texture map and a first offset position specified by a user and fetching texel attributes at the first destined texel position for the texture operation.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: Circuits, methods, and apparatus that provide for partial texture load instructions. Instead of one instruction that may take several shader passes to complete, several instructions are issued, where each instruction is an instruction to retrieve a part or portion of a texture. While each instruction is performed, the other shader circuits can perform other instructions, thus increasing the utilization of the shader circuits when large textures are read from memory. Since several shader passes may be required to read a texture, if a particular instruction needs the texture, one exemplary embodiment reorders instructions such that other instructions are performed before the particular instruction that needs the texture.

Abstract: Systems and methods for producing anti-aliased images use a sub-pixel sample pattern set that includes two or more unique sub-pixel sample patterns that are complementary. The sub-pixel sample patterns are offset from each pixel center and used to produce images that are combined to produce the anti-aliased image. In addition to providing sub-pixel coverage information, the sub-pixel sample pattern sets may be used to produce sub-pixel shading information. Furthermore, the sub-pixel sample pattern sets may be used in single processor systems or in multiprocessor systems to produce anti-aliased images.

Abstract: One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.

Abstract: A display device includes a wavelet transform unit for transforming an original image into wavelet coefficients using a Harr wavelet transform formula, a level obtaining unit for obtaining a mipmap level of a mipmap image. The display device also includes an inverse wavelet transform unit for receiving and subjecting at least a portion of the wavelet coefficients obtained by the transformation by the wavelet transform unit, to an inverse transform using an inverse Harr wavelet transform formula until an order having a value equal to the mipmap level is obtained, and outputting an image represented by at least a portion of a low-frequency component of wavelet coefficients having the order having the value equal to the mipmap level. Additionally, the display device includes a polygon drawing unit for drawing the image output by the inverse wavelet transform unit, as a mipmap image, on the polygon image.

Abstract: One embodiment of the present invention sets forth a method for accessing texture objects stored within a texture memory. The method comprises the steps of receiving a texture bind request from an application program, wherein the texture bind request includes an object identifier that identifies a first texture object stored in the texture memory and an image identifier that identifies a first image unit, binding the first texture object to the first image unit based on the texture bind request, receiving, within a shader engine, a first shading program command from the application program for performing a first memory access operation on the first texture object, wherein the memory access operation is a store operation or atomic operation to an arbitrary location in the image, and performing, within the shader engine, the first memory access operation on the first texture object via the first image unit.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a method for reducing bank collisions within a level 2 (L2) cache comprising the following: reading texture data from external memory configured to store texture data used for texture filtering within the graphics processing unit, partitioning the texture data into banks, performing a bank swizzle operation on the banks, and writing the banks of data to the L2 cache.

Abstract: Transparency groups or other images may be rendered on graphics hardware using a GPU utilizing only a single frame buffer and without the need to switch contexts to another frame buffer. A single frame buffer may be allocated and the overall background image may be rendered to the frame buffer. In order to render a foreground image to be combined with the background image, a sub-image of the background image is copied from the frame buffer to a texture atlas. The foreground image may then be rendered to the portion of the frame buffer from which sub-image was copied. The foreground image may then be copied from the frame buffer into the texture atlas. Additionally, both the sub-image of the background image and the foreground image may be merged and copied from the texture atlas into the frame buffer.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Abstract: A graphics system supports arrays of cube map textures. In one implementation, a cube map texture is utilized as an index into a set of cube map textures. The set of cube map textures may further be arranged into an atlas of two-dimensional textures.