Abstract: Disclosed subject matter relates generally to graphics processing, and relates more particularly to processing graphics vertex content.

Abstract: Patient identification is transmitted to a health care provider prior to the patient arriving at the health care provider. The patient identification may be a driver's license, health insurance card, or other identification, and may be used to pre-register the patient. The transmission may include other information, such as health status, purpose of visit, intended procedures, symptoms, or other information. The transmission may be made via a device, such as a cellular telephone, where the information may be encrypted and transmitted using a secure mechanism. The system may be used by ambulance personnel, paramedics, or other emergency responders to notify a hospital, for example, of an inbound patient, as well as by patients prior to an appointment. The system may also be used by clinicians or other health care providers to prepare for emergent or non-emergent patients prior to arrival.

Abstract: A texture cache comprises at least two banks of cache storage to cache texels for processing in texture mapping operations. Access to the cached texels corresponding to a given chunk of texels of a given texture image is controlled according to a selected bank mapping selected from two or more bank mappings supported by the texture cache access control circuitry. Each bank mapping corresponds to a different mapping of the respective texels within the given chunk to the banks of cache storage. In at least one operating mode, the selected bank mapping is selected for the given chunk of texels of the given texture image depending on: at least one of first/second chunk position coordinates associated with the given chunk of texels; and at least one further texture attribute associated with the given texture image.

Abstract: Apparatuses, systems, and techniques to process packet data in parallel. In at least one embodiment, packet data is processed by (e.g., one or more algorithms expressed in CUDA code executing on) a Graphics Processing Unit (“GPU”).

Abstract: The total memory space that is logically available to a processor in a general-purpose graphics processing unit (GPGPU) module is increased to accommodate terabyte-sized amounts of data by utilizing the memory space in an external memory module, and by further utilizing a portion of the memory space in a number of other external memory modules.

Abstract: Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

Abstract: A computer system is provided for converting images through use of a trained neural network. A source image is divided into blocks and context data is added to each pixel block. The context blocks are split into channels and each channel from the same context block is added to the same activation matrix. The action matrix is then executed against a trained neural network to produce a changed activation matrix. The changed activation matrix is then used to generate a converted image.

Abstract: The media stream delivery system encodes and fragments media streams into numerous media stream fragments maintained on fragment servers. Devices obtain fragments to reconstruct media streams including live real-time media streams for playback on the devices. A device may perform caching of media stream fragments so that particular fragments need not be accessed again from a fragment server. A fragment server or even a content provider can analyze and monitor characteristics of media streams, viewing behavior, content popularity, etc., to identify fragments for caching at the playback devices. Caching indicators along with time period indicators may be included in the media stream fragments.

Abstract: A cache for use in a tile-based rendering graphics processing system for storing transformed primitive blocks, the graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated, the graphics processing system comprising rasterization logic that rasterizes primitives on a per tile basis in a plurality of stages, the cache comprising: memory configured to store a plurality of transformed primitive blocks in the cache, each transformed primitive block comprising transformed geometry data for one or more primitives; control logic configured to: maintain a counter for each of the plurality of transformed primitive blocks stored in the cache that indicates a number of tiles of the plurality of tiles that are currently being processed by the rasterization logic and require access to that transformed primitive block, the counter being updated when any stage of the rasterization logic indicates a tile no longer requires access to the transformed primiti

Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

Abstract: One embodiment provides a graphics processor including a plurality of processing clusters, each processing cluster including a plurality of multiprocessors and a data interconnect coupled to the plurality of multiprocessors. At least one multiprocessor of the plurality of multiprocessors is configured to share data with another multiprocessor over the data interconnect.

Abstract: The embodiments provide a register file device which increases energy efficiency using a spin transfer torque-random access memory for a register file used to compute a general purpose graphic processing device, and hierarchically uses a register cache and a buffer together with the spin transfer torque-random access memory, to minimize leakage current, reduce a write operation power, and solve the write delay.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: In an example, a method to display a graphical diagram includes receiving source data that includes multiple nodes arranged in a directed acyclic graph (DAG) in which each child node of a set of child nodes has multiple DAG parent nodes. The nodes include the DAG parent nodes. The method includes converting the DAG to a tree in which each of the nodes has no more than one tree parent node. The method includes displaying, based on the tree, a graphical diagram in which child graphical objects that represent child nodes that each has multiple DAG parent nodes are positioned in intersection areas of container graphical objects that represent the DAG parent nodes.

Abstract: The invention discloses a data structure-aware prefetching method and device on a graphics processing unit. The method comprises the steps of acquiring information for a memory access request in which a monitoring processor checks a graph data structure and read data, using a data structure access mode defined by a breadth first search and graph data structure information to generate four corresponding vector prefetching requests and store into a prefetching request queue. The device comprises a data prefetching unit distributed into each processing unit, each data prefetching unit is respectively connected with an memory access monitor, a response FIFO and a primary cache of a load/store unit, and comprises an address space classifier, a runtime information table, prefetching request generation units and the prefetching request queue.

Abstract: A determination is made that the performance of a user database query to a database does not meet a first performance threshold. In response to the user database query not meeting the first performance threshold, one or more test queries of the database are performed. A second determination is made whether a performance of the one or more test queries meets a second performance threshold. In response to the one or more test queries meeting the second performance threshold, an analysis is performed to determine whether to resize a database buffer cache of the database.

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

Abstract: A touch control human-machine interface for use in controlling operation of a machine, said interface including: an interface housing; a cover plate disposed on an outer-surface of the housing, said cover plate having a first electrically-conductive portion configured for touch interaction by a user's finger; a circuit assembly disposed within the housing, said circuit assembly including a circuit board having a second electrically-conductive portion and a light illumination module operably-connected thereto; a spacer element disposed between and separating the first conductive portion from the second conductive portion such that the first conductive portion, the second conductive portion and the spacer element are configured to form a capacitor device that is operably-connected with the circuit assembly; said first electrically-conductive portion being configured for deformation by the user's finger so as to cause a change in capacitance across the capacitor device, and whereby responsive to said change in c

Abstract: Disclosed by the present invention are a graphical user interface redrawing method, a terminal device and a computer readable storage medium. The method comprises: merging invalidate data of multiple Views under the same View Group in the same VSYNC drawing period in an Android system GUI and saving to a HashMap; sending to a user interface (UI) thread a message for delaying execution of an invalidate instruction; reading all invalidate data from the HashMap and emptying the HashMap after a delay time interval of the message is reached; and executing the invalidate instruction according to the read invalidate data.

Abstract: A receiving device receives from a base unit across a network an instruction stream that includes drawing commands for producing graphic frames of a user interface. The receiving device is connected to a display. The receiving device parses the instruction stream to determine the drawing commands and their arguments. The receiving device executes the drawing commands in a graphics engine of the receiving device to generate the graphic frames of the user interface. Executing includes performing rendering functions and interpolating coordinates for animation. The receiving device outputs the graphic frames of the user interface for display.

Abstract: Transformation of graphic objects is described. A graphic object modification system receives an indication of a transformation to be performed on one or more graphic objects. For merger transformations, a stroke and a fill are identified for each graphic object being merged. Fill values are written to a buffer in a first pass, and stroke values are written to the buffer in a second pass without overwriting fill values. The merged graphic object is then output by rendering values stored in the buffer. For other non-merger transformations, z-order information is identified for each displayed graphic object. Graphic objects selected for transformation are allocated into clusters based on their z-order information. Clusters are rendered in separate GPU textures and transformations are applied to the separate textures, enabling the graphic object modification system to output transformation results in real-time without re-rendering the actual graphic objects being transformed.

Abstract: A method for processing a print job file using a printing system includes receiving, by the printing system, the print job file, the print job file including at least one placeholder element designated in the document using a pattern, a spot color, or a set of color values; receiving, by the printing system, missing content for the print job file; replacing, by the printing system, the at least one placeholder element with the missing content; and printing, by the printing system, the print job file including the missing content.

Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

Abstract: A gaming key mode adjusting method and an electronic device are provided. The gaming key mode adjusting method includes: retrieving a display image; determining that the display image corresponds to a gaming scenario; obtain a key mode corresponding to the gaming scenario and process a keyboard input signal according to the key mode. In the key mode, key travels correspond to a plurality of key press values.

Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.

Abstract: A cache for use in a tile-based rendering graphics processing system for storing transformed primitive blocks, the graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated, the graphics processing system comprising rasterization logic that rasterizes primitives on a per tile basis in a plurality of stages, the cache comprising: memory configured to store a plurality of transformed primitive blocks in the cache, each transformed primitive block comprising transformed geometry data for one or more primitives; control logic configured to: maintain a counter for each of the plurality of transformed primitive blocks stored in the cache that indicates a number of tiles of the plurality of tiles that are currently being processed by the rasterization logic and require access to that transformed primitive block, the counter being updated when any stage of the rasterization logic indicates a tile no longer requires access to the transformed primiti

Abstract: A convolutional neural network (CNN) for an image processing system comprises an image cache responsive to a request to read a block of N×M pixels extending from a specified location within an input map to provide a block of N×M pixels at an output port. A convolution engine reads blocks of pixels from the output port, combines blocks of pixels with a corresponding set of weights to provide a product, and subjects the product to an activation function to provide an output pixel value. The image cache comprises a plurality of interleaved memories capable of simultaneously providing the N×M pixels at the output port in a single clock cycle. A controller provides a set of weights to the convolution engine before processing an input map, causes the convolution engine to scan across the input map by incrementing a specified location for successive blocks of pixels and generates an output map within the image cache by writing output pixel values to successive locations within the image cache.

Abstract: A system, method, and computer readable storage medium for inter-process rendering pipeline for shared process remote web content rendering. The method includes obtaining an image rendering request through an inter-process communication channel established by an application in which the image rendering request including a content area. The method further includes selecting a content rendering engine based on one or more image resources needed to generate web content as specified in the image rendering request, determining the one or more image resources corresponding to the image rendering request by using the content rendering engine, and generating the web content on the content area based at least in part on the one or more image resources.

Abstract: Disclosed are various embodiments for determining a wagering game to play on a client device. The client device can determine the orientation of a display using one or more sensors. The wagering game can be selected using the orientation. The selected wagering game can be rendered on the display. An outcome of the wagering game can be generated.

Abstract: According to one example embodiment of the present disclosure, there is provided a method for optimization in a distributed system, where the distributed system comprises a client and multiple hosts among which a host comprises a computing node. The method comprises: receiving a first command requesting to use the computing node from an application at the client; determining the type of the first command; and adjusting the first command on the basis of the type of the first command to optimize the execution of the first command in the distributed system, where the computing node is a graphics processing unit, and the first command is a remote procedure call of the graphics processing unit.

Abstract: Technology for selectively prefetching data, such that less data is prefetched when it is determined that the requested data is located in logical addresses allocated to a symbol table data structure. In some embodiments, data is still prefetched when the request is directed to the symbol table, but the amount of data prefetched (measured in memory lines, bytes or other unit) is decreased relative to what it otherwise would be in the context of a non-symbol-table request. In other embodiments, prefetching is simply not performed at all when the request is directed to the symbol table.

Abstract: A computer-implemented redundant-coverage discard method and apparatus for reducing pixel shader work in a tile-based graphics rendering pipeline is disclosed. A coverage block information (CBI) FIFO buffer is disposed within an early coverage discard (ECD) logic section. The FIFO buffer receives and buffers coverage blocks in FIFO order. At least one coverage block that matches the block position within the TCPM is updated. The TCPM stores per-pixel primitive coverage information. The FIFO buffer buffers a moving window of the coverage blocks. Incoming primitive information associated with the coverage blocks is compared with the per-pixel primitive coverage information stored in the tile coverage-primitive map (TCPM) table at the corresponding positions for the live coverages only. Any preceding overlapping coverage within the moving window of the coverage blocks is rejected. An alternate embodiment uses a doubly linked-list rather than a FIFO buffer.

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive one or more frames for a workload, determine one or more compute resource parameters for the workload, and store the one or more compute resource parameters for the workload in a memory in association with workload context data for the workload. Other embodiments are also disclosed and claimed.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: Implementations of the present application describe updating tile maps in virtual maps, including the following. A central area in which a virtual object is located is determined in a first area. The first area comprises an area of a map that includes tile maps loaded into a virtual map including the virtual object. A border of the central area is located in the first area. A distance parameter is determined after the virtual object moves out of the central area. The distance parameter indicates relative distances of a tile map containing the virtual object relative to the central area in x-axis and y-axis directions. A loading status of a tile map not shared by the first area and a second area is updated based on the distance parameter. The second area comprises a map area determined after moving the first area based on the distance parameter.

Abstract: A method comprising, in an image processing operation, identifying location data indicative of a read path for the image processing operation, the read path at least partly traversing a block of pixels of an image. Parameter data relating to a characteristic of the read path in the context of the block is generated from the location. Storage prioritization data is associated with the block at least partly on the basis of the parameter data. The storage prioritization data is for determining whether block data representative of the block is to be evicted from storage.

Abstract: One disclosed embodiment is directed to graphics processing method for displaying a user interface. The method includes executing a plurality of graphic processing operation in a single rendering pass. The rendering pass includes several render targets. At least one of the render targets is designated as a memory-less render target. The memory-less render target is used to store intermediate data. The intermediate data is combined with the outcome of at least one other graphics processing operation to generate a combined result. The combined result is stored in the frame buffer memory for display.

Abstract: A computer-based method for asynchronously requesting content items to a user computing device is described. The method is implemented using a user computing device in communication with a memory. The method includes receiving a content management response, generating a plurality of content request messages for requesting at least one content item from a plurality of content providers based on the plurality of links, asynchronously transmitting a first content request message to a first content provider and a second content request message to a second content provider where the first and second content request messages are transmitted based on the at least one transmission rule, receiving a content response message including a content item from at least one of the first and the second content provider, determining the content item to display on the user computing device, and displaying the determined online content item on the user computing device.

Abstract: Implementations of the present application describe updating tile maps in virtual maps, including the following. A central area in which a virtual object is located is determined in a first area. The first area comprises an area of a map that includes tile maps loaded into a virtual map including the virtual object. A border of the central area is located in the first area. A distance parameter is determined after the virtual object moves out of the central area. The distance parameter indicates relative distances of a tile map containing the virtual object relative to the central area in x-axis and y-axis directions. A loading status of a tile map not shared by the first area and a second area is updated based on the distance parameter. The second area comprises a map area determined after moving the first area based on the distance parameter.

Abstract: Systems and methods are provided for encoding a multi-pixel caching scheme for lossless encoders. The systems and methods can include obtaining a sequence of pixels, determining repeating sub-sequences of the sequence of pixels consisting of a single repeated pixel and non-repeating sub-sequences of the sequence of pixels, responsive to the determination, encoding the repeating sub-sequences using a run-length of the repeated pixel and encoding the non-repeating sub-sequences using a multi-pixel cache, wherein the encoding using a multi-pixel cache comprises, encoding non-repeating sub-sequences stored in the multi-pixel cache as the location of the non-repeating sub-sequences in the multi-pixel cache, and encoding non-repeating sub-sequences not stored in the multi-pixel cache using the value of the pixels in the non-repeating sub-sequences.

Abstract: A data processing method processes data using a processor including N (N is an integer equal to or more than 2) cores and a memory. The data processing method includes: searching a new character as a character whose raster data is not stored in the memory among a plurality of characters specified by character data included in print data to count a count of the searched new characters; generating M (M is an integer equal to or less than the N) threads, wherein the M is a count determined based on the count of the counted new characters among the N; dividing and allocating the plurality of characters to the M threads to generate raster data for the new characters using any one of the N cores for each of the M threads; and rendering the plurality of characters using raster data corresponding to the character data.

Abstract: One disclosed embodiment includes memory allocation methods for use by a graphics processing unit in rendering graphics data for display. The method includes receiving a buffer attachment associated with a first rendering pass. The hardware prerequisites for operation of the first rendering pass is determined. The method also includes receiving an indication to not allocate system memory for the received buffer attachment. Thereafter, it may be determined whether the received buffer attachment will be loaded from or stored to by the subsequent rendering passes. If it is determined that the buffer attachment will be accessed by the subsequent rendering passes, an error message may be generated indicating that system memory must be allocated. If it is determined that the buffer attachment will not be accessed by the subsequent rendering passes, the buffer attachment is rendered without allocating system memory.

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

Abstract: A storage device includes a memory unit, an access monitor, and a memory configurator. The memory unit includes a plurality of memory blocks. The access monitor is configured to monitor whether an access mode of the memory unit is a continuous-access mode or a random-access mode, to generate a monitor signal. The memory configurator configures, according to the monitor signal, any of the memory blocks to be either in a cache mode or a SRAM state to generate a configuration signal.

Abstract: Provided is a method and device for correction restoration and analysis alarming of a distorted image. The method includes that: an original distorted image acquired by a distortion lens is received, and original distorted coordinates of each coordinate point in the original distorted image are acquired; and pre-stored distortion parameters of the distortion lens are acquired, and restored coordinates of each coordinate point in the original distorted image are determined to obtain a restored image.

Abstract: This disclosure describes techniques for context switching. In one example, a graphics processing unit may be configured to generate one or more signatures for context information stored in on-chip memory of the graphics processing unit, determine whether the one or more signatures match any previously generated signatures for context information stored in one or more memories accessible by the graphics processing unit, store, to at least one of the one or more memories, any signature of the one or more signatures that is determined not to match any previously generated signature stored in at least one of the one or more memories, and store, to at least one of the one or more memories, the context information respectively corresponding to the one or more signatures determined not to match any previously generated signature stored in at least one of the one or more memories.

Abstract: Embodiments of the present invention are directed at providing a mirror snapping system for selecting candidate snap points as endpoints for path segments with symmetry in a created image. In one embodiment, generating candidate snap locations from a newly created path segment can be accomplished by automatically constructing an axis of symmetry for the newly created path segment and reflecting created path segment endpoints in the design across the axis of symmetry. In a further embodiment, upon selection of a candidate snap location as the anchored endpoint for an unanchored endpoint of a path segment, line parameters associated with the candidate snap location can be implemented in the path segment. Such parameters can include weight, color, and curvature of the path segment. Other embodiments may be described and/or claimed.

Abstract: A graphics processing core of a tile-based graphics processing system when processing a tile of a graphics output reads a primitive to be processed off a tile list for the tile being processed, along with an identifier for that primitive. The graphics processing core then checks whether or not the identifier matches the identifier stored for any entry stored in a primitive data cache. A match indicates that primitive-specific data (including line equations, depth equations and barycentric equations) for the primitive to be processed is stored in the cache. If a match is found then the stored primitive-specific data is retrieved and used to process (rasterise and render) the primitive. If no match is found, primitive-specific data is calculated from scratch, stored in the primitive data cache, and used to process the primitive.

Abstract: The present invention relates to a caching method of multi-core graphic processing unit (GPU) for improving image processing performance by efficiently storing video data into the cache memory out of the global memory. One aspect of the present invention is to provide a caching method of graphic processing unit (GPU) having multiple cores wherein at least a part of pixels out of A*B pixels of video data are cached into a cache memory in order to perform image processing on k pixels of N*N size (where, k, N, A and B are natural numbers; k=N*N; A>N; B>N), the method comprising: grouping the at least a part of pixels out of A*B pixels into k pixel groups; mapping the k pixel groups to k cores of the GPU one-to-one basis by utilizing index information of each of the k pixels; and storing video data of the k pixel groups in the cache memory with reference to the mapping result.

Abstract: Tile cache techniques are described. In at least some embodiments, a tile cache is maintained that stores tile content for a plurality of tiles. The tile content is ordered in the tile cache to match a visual order of tiles in a graphical user interface. When tiles are moved (e.g., panned and/or scrolled) in the graphical user interface, tile content can be retrieved from the tile cache and displayed.