Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: A method for using a state machine to control a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor, and tracking each of a plurality of cache lines stored within the cache using a least recently used variable. For each a cache line hit out of the plurality of cache lines and corresponding to one of the read requests, the least recently used variable is adjusted for a remainder of the plurality of cache lines. A replacement cache line is determined by examining the least recently used variables for each of the plurality of cache lines. For each cache line miss, a cache line slot corresponding to the replacement cache line is allocated to store a new cache line responsive to the cache line miss.

Abstract: A method and apparatus for processing vector data is provided. A processing core may have a data cache and a relatively smaller vector data cache. The vector data cache may be optimally sized to store vector data structures that are smaller than full data cache lines.

Abstract: Embodiments of the present invention provide a system for performing caching in an image-processing system. The system starts by receiving a filtering query for resources in a cache. The system then returning a subcache in response to the filtering query. Upon receiving a resource query for resources in the subcache, the system performs the filtering query on the cache, populates the subcache with addresses of resources returned by the filtering query until the resource query is satisfied, and returns available resources from the subcache in response to the resource query.

Abstract: A method for storing interpolation data is provided, which includes the following steps: dividing a buffer into a plurality of regions, and using the regions to store the interpolation data of a plurality of non-integer points. The decimal part of each logical coordinate for each of the non-integer points is identical to that of the corresponding logical coordinate for another of the non-integer points in the same region.

Abstract: A method is to implement a Scale Invariant Feature Transform algorithm in a shared memory multiprocessing system. The method comprises building differences of Gaussian (DoG) images for an input image, detecting keypoints in the DoG images; assigning orientations to the keypoints and computing keypoints descriptors and performing matrix operations. In the method, building differences of Gaussian (DoG) images for an input image and detecting keypoints in the DoG images are executed for all scales of the input image in parallel. And, orientation assignment and keypoints descriptions computation are executed for all octaves of the input image in parallel.

Abstract: When a user interface is scrolled, data requests are made. If the data is not found in cache, the data is retrieved from a remote server by asynchronously placing data requests to a server starting with the last added data request. Through a relaxed loader, the mobile device does not bombard the remote server with requests. By removing older data requests, the mobile application fetches data more in line with the current display. After receiving the data from the remote server, the data is decoded and compressed. The data is placed within cache. When multiple entries exist, the data within cache is associated and processed. Instead of the interface decoding data from the cache for each entry, the processed data is provided to the interface removing processing and required memory for each entry.

Abstract: Methods, apparatuses, and systems are presented for caching. A cache memory area may be used for storing data from memory locations in an original memory area. The cache memory area may be used in conjunction with a repeatedly updated record of storage associated with the cache memory area. The repeatedly updated record of storage can thus provide a history of data storage associated with the cache memory area. The cache memory area may be loaded with entries previously stored in the cache memory area, by utilizing the repeatedly updated record of storage. In this manner, the record may be used to “warm up” the cache memory area, loading it with data entries that were previously cached and may be likely to be accessed again if repetition of memory accesses exists in the span of history captured by the repeatedly updated record of storage.

Abstract: Methods, software, and apparatuses for graphics processing, including caching pixel data of one or more tiles of a graphics surface. Methods generally include setting a caching bit corresponding to the surface, setting tile pattern bits corresponding to tiles in the surface, and when the caching bit is active, storing one or more pixel values in a cache memory. When at least one tile contains pixels having the same value for at least one predetermined parameter, the caching bit and the corresponding tile pattern bits may be active. Apparatuses generally include a pixel memory, a cache memory, and a controller including logic configured to reserve the caching bit, tile pattern bits, and same pixel values in cache memory when the caching bit is active.

Abstract: An automated method of rendering image data using a multithread central processing unit (“CPU”) is described. The method retrieves a set of image processing instructions. The method determines an image section size to be processed by the CPU using the set of image processing instructions. The method iteratively: (i) retrieves a section of the image data that matches the image section size, and (ii) sends the section of the image data to a particular thread of the multithread CPU for processing using the processing instructions.

Abstract: The present invention is applied to a coding device and a decoding device for moving image data in compliance with, for example, an MPEG-4AVC/ITU-T H. 264 system, in which address data is issued to specify an area that is a plurality of read units in a horizontal direction and a vertical direction, respectively, and reference image data is stored in a cache memory.

Abstract: Tile cache techniques are described. In at least some embodiments, a tile cache is maintained that stores tile content for a plurality of tiles. The tile content is ordered in the tile cache to match a visual order of tiles in a graphical user interface. When tiles are moved (e.g., panned and/or scrolled) in the graphical user interface, tile content can be retrieved from the tile cache and displayed.

Abstract: A method for storing interpolation data is provided. The method uses a buffer in a cache memory and the concept of memory overlap record for storing previously calculated interpolation data, so as to avoid repeated interpolation, thereby decreasing the amount of system operation and the frequency of reading integer points for calculating interpolation from an external memory. Furthermore, a method of data storage for the buffer is provided. The storage method uses the concept of memory address rotation to store interpolation data beyond the boundary of the buffer. Moreover, another storage method is provided, which distributes interpolation data into a plurality of regions in the buffer according to different combinations of decimal coordinates of the interpolation points for economizing the use of memory space and simplifying the search of interpolation data in the buffer.

Abstract: An information processing apparatus for encoding image data, includes a filter unit for performing a filtering operation on the image data in a layer fashion to generate a plurality of subbands including coefficient data segmented on a per frequency band basis, an intermediate data storage unit for storing intermediate data generated in the middle of the filtering operation of the filter unit, a coefficient storage unit for storing the coefficient data generated in the filtering operation of the filter unit, and a coefficient rearranging unit for performing a rearranging operation to rearrange the coefficient data stored on the coefficient storage unit so that the coefficient data is output in a predetermined order. The intermediate data storage unit writes and reads data thereon at a speed higher than the coefficient storage unit and being smaller in storage capacity than the coefficient storage unit.

Abstract: Disclosed herein is a supplemental cache for use with a graphics processing unit. The supplemental cache can be used to supplement a vertex cache used with a graphics processing unit. The supplemental cache stores vertex values generated in assembling primitives from vertices provided to the graphics processing unit as part of an image geometry. Generated vertex values associated with a vertex determined to be shared by two or more primitives can be retrieved from the supplemental cache, so as to reduce the need to perform duplicative operations to generate vertex values for shared vertices.

Abstract: Presented are systems and methods that change the order in which triangles are rendered, to improve post-transform vertex cache efficiency and reduce view-independent overdraw. The resulting triangle orders are orders magnitude faster to compute compared to previous methods. The improvements in processing speed allow such methods to be performed on a model after it is loaded (i.e., when more information on the host hardware is available). Also, such methods can be executed interactively, allowing for re-optimization in case of changes to geometry or topology, which happen often in CAD/CAM applications.

Abstract: A three-dimensional computer graphics rendering system allows a tile-based rendering system to operate with a reduced amount of storage required for tiled screen space geometry by using an untransformed display list to represent the screen's geometry.

Abstract: A method includes determining a cache width of a cache of a processing device and determining a block size of image data processed by the processing device. The method further includes prefetching a data block of image data from a memory component to a plurality of cache lines of the cache based on the cache width and the block size. A processing system includes a memory component, a cache and an execution pipeline coupled to the memory component and the cache. The execution pipeline is to determine a cache width of the cache, determine a block size of image data stored at the memory component, and prefetch a data block of image data from a memory component to a plurality of cache lines of the cache based on the cache width and the block size.

Abstract: Apparatus, systems and methods are described including dividing cache lines into at least most significant portions and next most significant portions, storing cache line contents in a register array so that the most significant portion of each cache line is stored in a first row of the register array and the next most significant portion of each cache line is stored in a second row of the register array. Contents of a first register portion of the first row may be provided to a barrel shifter where the contents may be aligned and then stored in a buffer.

Abstract: A method with quick response time applied to the electronic apparatus is provided. The method includes: providing a storage configured for storing a plurality of images; providing a cache memory configured for temporarily storing decoded images; invoking the images that are previously to and next to the currently displayed image from the storage, decoding the invoked images, and storing the decoded images in the cache memory; receiving an instruction from user input; determining whether the instruction is for displaying a previous image or a next image; and invoking the decoded image of the image from the cache memory and displaying the selected image. A related electronic apparatus is also provided.

Abstract: The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: In some embodiments, a motion estimation search window cache is adaptively re-organized according to frame properties including a frame width and a number of reference frames corresponding to the current frame to be encoded/decoded. The cache reorganization may include an adaptive mapping of reference frame locations to search window cache allocation units (addresses). In some embodiments, a search window is shaped as a quasi-rectangle with truncated upper left and lower right corners, having a full-frame horizontal extent. A search range is defined in a central region of the search window, and is laterally bounded by the truncated corners.

Abstract: In a multiprocessor system level 2 caches are positioned on the memory side of a routing crossbar rather than on the processor side of the routing crossbar. This configuration permits the processors to store messages directly into each other's caches rather than into system memory or their own coherent caches. Therefore, inter-processor communication latency is reduced.

Abstract: The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a hybrid computing system. To this extent, a hybrid system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications on a hybrid image processing system referred to herein as an image co-processor that comprises (among other things) a plurality of special purpose engines (SPEs) that work to process multiple images in an accelerated fashion.

Abstract: A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.

Abstract: Embodiments of the present invention provide a system for performing image conversion operations. The system starts by receiving a request from a client for one or more pixel buffers containing a pixel-formatted, cropped, geometrically transformed, and/or color matched version of an image representation. The system then determines if a provider can provide the one or more pixel buffers. If so, the system calls the provider to generate the one or more pixel buffers containing the pixel-formatted, cropped, geometrically transformed, and/or color matched version of the image representation. Otherwise, the system calls the provider to generate one or more intermediate pixel buffers, generates a sequence of converters for converting the one or more intermediate pixel buffers, and calls the sequence of converters to generate the one or more pixel buffers containing the pixel-formatted, cropped, geometrically transformed, and/or color matched version of the image representation.

Abstract: A display device with embedded networking capability is described herein. The display device uses at least a portion of a memory of the display device, the memory of which is used for storing video/image data in the display, to store networking codes for establishing and maintaining the network connection.

Abstract: A video decoder cache used for motion compensation data may be dynamically reconfigured. In some embodiments, it may be reconfigured on picture or frame boundaries and in other embodiments it can be reconfigured on sequence boundaries. The cache may be flushed on each boundary to enable such reconfiguration.

Abstract: Embodiments of the present invention provide a system for performing caching in an image-processing system. The system starts by receiving a filtering query for resources in a cache. The system then returning a subcache in response to the filtering query. Upon receiving a resource query for resources in the subcache, the system performs the filtering query on the cache, populates the subcache with addresses of resources returned by the filtering query until the resource query is satisfied, and returns available resources from the subcache in response to the resource query.

Abstract: A method involving receiving an indication of a requirement to allocate at least one page for a process, where pages are associated with cache colors; generating a selection bitmap by performing a logical operation of a system available colors bitmap and a process bitmap, where the system available colors bitmap and the process bitmap each include one bit corresponding to each cache color, where each bit of the system available colors bitmap indicates whether a number of pages associated with a corresponding cache color that are available to be allocated is above a minimum threshold, and where each bit of the process bitmap indicates whether any pages associated with the corresponding cache color have been recently allocated for the process. The method also includes selecting, using the selection bitmap, a cache color; and allocating a page for the process, wherein the allocated page is associated with the selected cache color.

Abstract: When a user interface is scrolled, data requests are made. If the data is not found in cache, the data is retrieved from a remote server by asynchronously placing data requests to a server starting with the last added data request. Through a relaxed loader, the mobile device does not bombard the remote server with requests. By removing older data requests, the mobile application fetches data more in line with the current display. After receiving the data from the remote server, the data is decoded and compressed. The data is placed within cache. When multiple entries exist, the data within cache is associated and processed. Instead of the interface decoding data from the cache for each entry, the processed data is provided to the interface removing processing and required memory for each entry.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: Methods and computing devices enable optimized triangle strip generation using forward looking game tree evaluation methods with node evaluation of strip options based on desired performance criteria. The evaluation of possible triangle paths is performed using metrics which may be weighted for each desirable criteria at each move depth. A recursive algorithm may be used to recursively descend through alternative triangle paths and accumulates a score for the path. The final score for each evaluated triangle path at a dead end or maximum depth of evaluation provides a basis for selecting the best alternative path from the base or root triangle for graphic processing. This evaluation or alternative triangle paths may be repeated to select each subsequent triangle for processing or may be repeated after a number of triangles within the selected path have been processed.

Abstract: A vertex cache within a graphics processor is configured to operate as a conventional round-robin streaming cache when per-vertex state changes are not used and is configured to operate as a random access storage buffer when per-vertex state changes are used. Batches of vertices that define primitives and state changes are output to parallel processing units for processing according to vertex shader program. In addition to allowing per-vertex state changes, the vertex cache is configured to store vertices for primitive topologies that use anchor points, such as triangle strips, line loops, and polygons.

Abstract: A plurality of encoded video segments that are stored in a cache memory and associated with every nth video segment in a sequence of video segments of a video program is selected, where n is an integer. The selected encoded video segments are removed from the cache memory. Each video segment in the sequence may be associated with a respective plurality of encoded video segments encoded at different respective encoding rates.

Abstract: Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may be checked to see whether both a subspan request hits an unlit bit and a modify message was already sent. If so, the modification message may be filtered.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.

Abstract: Techniques for caching images are presented. A matrix of pixel values represents an image. A diagonal of the matrix is used as an array of numbers representing an index value. The index value is compared to existing index values housed in a cache. When no match is present, the index value is inserted into the cache and the corresponding image associated with the inserted index value acquired. When a match is present no action is taken on the index values of the cache.

Abstract: A graphics processing unit includes a first processing controller controlling a first set of multi-threaded processors. A second processing controller controls a second set of multi-threaded processors. A serial bus connects the first processing controller to the second processing controller. The first processing controller gathers first state information from the first set of multi-threaded processors in response to a context switch token and then passes the context switch token over the serial bus to the second processing controller. The second processing controller gathers second state information from the second set of multi-threaded processors in response to the context switch token.

Abstract: A caching apparatus for video motion estimation and compensation includes: an external memory including a plurality of banks and configured to allocate one pixel row to one bank to store the pixel row; a memory controller configured to cause successively-inputted read requests to access different banks of the external memory and transmit a read command for a next read request to the external memory while reference data corresponding to a first-coming read request is outputted; and a data processor configured to successively make read requests for the reference data to the memory controller when reference data read requests are successively inputted, store the reference data inputted from the memory controller, and output the stored reference data.

Abstract: A drawing apparatus which can create an exposure pattern rapidly. The drawing apparatus has a raster conversion processing module for converting vector images as wiring patterns into bitmap image data, an image cache module for temporarily storing a predetermined-size cached image supplied from the raster conversion processing module, a first compression module for compressing the cached image stored in the image cache module, a second compression module for compressing the cached image stored in the image cache module in a compression ratio differing from that of the first compression module, a comparison module for comparing data sizes of compressed data generated by the first and second compression modules and selecting one having a smaller data size, a memory access module for writing the compressed data selected by the comparison module, into a storage module, and a cache region control module for controlling a compression status of the cached image.

Abstract: Methods and apparatus for subdividing a shader program into regions or “phases” of instructions identifiable by phase identifiers (IDs) inserted into the shader program are provided. The phase IDs may be used to constrain execution of the shader program to prohibit texture fetches in later phases from being executed before a texture fetch in a current phase has completed. Other operations (e.g., math operations) within the current phase, however, may be allowed to execute while waiting for the current phase texture fetch to complete.

Abstract: A gaming machine that permits wagering on games includes an input/output module associated with a microprocessing unit and is adapted to download schedules from a server of gaming actions to be taken by the gaming machine. Memory in the gaming machine stores the schedules. The memory also stores a backup schedule of gaming actions to be taken. A microprocessing unit determines whether one of the schedules or the backup schedule will be implemented. The microprocessing unit controls the performance of the gaming actions defined by the schedule being implemented.

Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.

Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

Abstract: The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for generating tile sizes associated with an image presented by a web based image system. An optimal threshold memory size for tiles associated with the image is identified. The image is then divided into tiles of equal physical dimensions and placed into a set of subdivided tiles. The memory size of each tile within the set of subdivided tiles is compared to the threshold memory size. Tiles having a memory size less than or equal to the threshold memory size are deleted from the set of subdivided tiles and stored. Tiles having a memory size greater than the threshold memory size are subdivided into tiles of smaller physical dimensions. The smaller tiles are placed back in the set of subdivided tiles. The process repeats until no tiles exist within the set of subdivided tiles.

Abstract: The present invention provides an image processing apparatus including: a production section configured to determine polygon groups each composed of a predetermined number of polygons juxtaposed in a first direction successively as an object block, which is an object of a production process, in an order in which the polygon groups are juxtaposed in a second direction substantially perpendicular to the first direction and produce apex data of the polygons which compose the object block in a unit of a polygon; and a determination section configured to store image data corresponding to those polygons which are positioned in a boundary portion of an immediately preceding block, which is a preceding object block to the object block, with respect to the object block from among those polygons which compose the immediately preceding block into a storage section for storing the pixel data in a unit of a data block to determine the number of the polygons which compose the polygon groups and are juxtaposed in the first

Abstract: A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes. This data cache includes a plurality of input ports for receiving the LDPC codes from some of the processing units, and a plurality of output ports for sending the LDPC codes to others of the processing units. An off-chip, external memory stores the LDPC codes and transmits the LDPC codes to and receives the LDPC codes from at least some of the processing units. A sequence processor controls the transmission of the LDPC codes between the processor units and the on-chip data cache so that the LDPC codes are processed by the processing units according to a given sequence.

Abstract: A processing pipeline employs one or more bypass caches to allow a transaction that is dependent on the results of a prior transaction to be processed before the prior transaction has completed processing. Each bypass cache is coupled to the input and the output of one of the sections of the processing pipeline so that results of a transaction from that section can be written into or read from the bypass cache as soon as that transaction has been completely processed through that section. With such a configuration, more transactions can be processed by the processing pipeline in a shorter amount of time. This is especially true for very deep pipelines.