Abstract: A method for and apparatus for supporting a control plane (C-plane) and a user plane (U-plane) in a wireless communication system supporting multiple carriers is provided. A wireless device configures a cell for the U-plane to receive and transmit data, determines to enable a User Plane Reception Period (U-RP) corresponding to the cell for the U-plane, and determines to receive and transmit data with the cell for the U-plane during the enabled U-RP. The cell for the U-plane includes at least one or more serving cells, and the cell for the U-plane has a different frequency from a cell for the C-plane.

Abstract: One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released.

Abstract: The present invention relates to a look-up table comprising a plurality of register signals (r0-r3); a plurality of inputs signals (A, A?, B, B?); and at least one output signal (Y); and a plurality of pass gates, wherein at least a first pass gate of the plurality of pass gates is controlled by at least a first input signal of the plurality of input signals, and by at least a first register signal, of the plurality of register signals, such that the register signal has priority over the input signal on the operation of the first pass gate.

Abstract: A rendering apparatus acquires graphic information of a figure to be rendered in a rendering area; specifies for each division area of the rendering area, graphic information of a figure to be rendered in the division area; calculates based on data size of the specified graphic information and for each division area, total data size of graphic information of the figure to be rendered in the division area; selects a division area as a rendering destination, based on each calculated total data size and a data capacity of a memory area to which graphic information is to be stored that is among the acquired graphic information and for the figure to be rendered; writes to the memory area, the graphic information of the figure to be rendered in the selected division area; and generates based on the written graphic information, an image for the selected division area.

Abstract: A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.

Abstract: A system for performing finite input response filtering. The system includes an array of random access memories (RAMs) for storing at least one two-dimensional (2D) block of pixel data. The pixel data is stored such that one of each type of column or row from the 2D block of pixel data is stored per RAM. A control block provides address translation between the 2D block of pixel data and corresponding addresses in the array of RAMs. An input crossbar writes pixel data to the array of RAMs as directed by the control block. An output crossbar simultaneously reads pixel data from each of the array of RAMs and passes the data to an appropriate replicated data path, as directed by the control block. A single instruction multiple data path block includes a plurality of replicated data paths for simultaneously performing the FIR filtering, as directed by the control block.

Abstract: A system and method of capturing, storing, editing and outputting multi-track motion data in a continuous stream on a computer with deterministic timing, where the length of the motion dataset is not limited by computer Random Access Memory. A hard real time periodic motion task takes in data streams from sensors or other computers, stores it in a shared memory area, and streams out the data to other computers so as to actuate motion. A shared memory area stores buffers and flags which indicate what data should be swapped to and from persistent storage. A soft real time periodic task transfers data pages between RAM and persistent storage based on requests from the motion task. Three data pages surround the active point in the motion dataset, four pages are reserved for copying whole blocks of data, and three pages are reserved for data editing. These ten active memory pages define a fixed memory footprint which can handle a deterministic data stream of effectively infinite length.

Abstract: A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

Abstract: A facility for cross-application encoding of geographical location information is described. In various embodiments, the facility receives a first document containing information relating to a geographical area, displays an image representing the geographical area, receives input from a user identifying at least a geographical location that is located in the geographical area, encodes a portion of the input to create an encoded link to the geographical location, and causes the link to be added to a second document such that when the link is selected, the first application displays the geographical area and identifies the identified geographical location. In various embodiments, the facility includes a correlating server that correlates geographical locations identified in documents of a first document type with documents containing mapping information.

Abstract: A method involving receiving an indication of a requirement to allocate at least one page for a process, where pages are associated with cache colors; generating a selection bitmap by performing a logical operation of a system available colors bitmap and a process bitmap, where the system available colors bitmap and the process bitmap each include one bit corresponding to each cache color, where each bit of the system available colors bitmap indicates whether a number of pages associated with a corresponding cache color that are available to be allocated is above a minimum threshold, and where each bit of the process bitmap indicates whether any pages associated with the corresponding cache color have been recently allocated for the process. The method also includes selecting, using the selection bitmap, a cache color; and allocating a page for the process, wherein the allocated page is associated with the selected cache color.

Abstract: A memory address mapping method of controlling storage of images in a memory device is provided. The memory device includes banks each having a plurality of pages. The memory address mapping method includes: receiving a first image; and referring to an image partition setting to generate a first memory address setting for each horizontal line partition in the first image, wherein the image partition setting defines that one image is divided into horizontal line groups each having at least one horizontal line, and each of the horizontal line groups is divided into horizontal line partitions in a horizontal line direction. First memory address settings of the horizontal line partitions in each horizontal line group of the first image control that a corresponding horizontal line group having the horizontal line partitions included therein is not stored into a same bank of the memory device.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.

Abstract: In a memory control apparatus and a method for controlling memory access capable of selecting a desirable page mode, so as to reduce memory access time, a storage circuit receives threshold page hit ratios for each of a plurality of bus masters, and stores the threshold page hit ratios. A page hit ratio computing circuit receives the number of memory accesses by each of the bus masters and the number of page hits by each of the bus masters, computes page hit ratios by each of the bus masters, and outputs the page hit ratios. A comparing circuit compares the threshold page hit ratios with the computed page hit ratios obtained from the page hit ratio computing circuit, and outputs predetermined page mode control signals. The page mode control signals control the page modes of the memory by each of the bus masters in response to the comparison result.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.

Abstract: A buffer facilitates reordering of memory access commands in a memory access command stream so as to create column coherencies that may be exploited with burst-mode memory cycles. A multi-column data storage buffer is provided. Storage control circuitry stores data associated with a memory access command into the multi-column data storage buffer at a column that corresponds to at least one of the LSBs of the column address associated with the memory access command. Flush control circuitry flushes the data storage buffer, when required, in column order. Each entry in the data storage buffer is associated with a unique valid bit. At flush time, the flush control circuitry analyzes the valid bits to determine an appropriate burst type for executing the memory access commands represented by the flushed buffer contents. The flush control circuitry may indicate the determined burst type to memory controller hardware by means of a burst type flag. The data storage buffer may include multiple lines.

Abstract: A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as needed. When the buffer is flushed, groups of memory access commands are selected for flushing whose row/bank addresses are associated, thereby creating page coherency in the flushed memory access commands. Batches of commands may be flushed from the buffer according to a sequence designed to minimize same-bank page changes in frame buffer memory devices. Good candidate groups for flushing may be chosen according to criteria based on the binary bank address for the group, the size of the group, and the age of the group. Groups may be partially flushed. If so, a subsequent flush operation may resume flushing a partially-flushed group when to do so would be more beneficial than flushing a different group chosen solely based on its bank address.

Abstract: Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row address and a column address; a row decoder connected to the memory array for selecting a row address in the memory array; a column decoder connected to the memory array for selecting a column address in the memory array; and a multi-sequence address generator for generating addresses, where the multi-sequence address generator has a burst mode and in burst mode generates one of two or more burst sequences of addresses according to received burst parameters, and where each sequence has an index indicating the separation between two addresses in the sequence.

Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.

Abstract: A method and apparatus for dynamic issuing of memory access instructions. In particular, a specific data access request that is about to be sent to a memory, such as a frame buffer, is dynamically chosen based upon pending requests within a pipeline. It is possible to optimize video data requests by dynamically selecting a memory access request at the time the request is made to the memory. In particular, if it is recognized that the memory about to be accessed will no longer be needed by subsequent memory requests, the request can be changed from a normal access request to an access request with an auto-close option. By using an auto close option, the memory bank being accessed is closed after the access, without issuing a separate memory close instruction.

Abstract: Methods and apparatus for implementing a pixel page system providing pixel pages using combined addressing. In alternative implementations, the system stores and retrieves data other than pixel data.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.