Abstract: The present disclosure provides a picture processing method and device, including: an integrated circuit chip IC receiving a to-be-processed picture sent by a graphics processor GPU; the IC pre-processing the to-be-processed picture; the IC performing counter-distortion process on the pre-processed picture; and the IC outputting the picture which is subjected to the counter-distortion process for display.

Abstract: A clothes dryer having a control circuit including a speed sensor, wherein the control circuit can sense movement of a portion of a drum assembly. The control circuit uses sensed speed information to control the motor, the heater, or other portion of the clothes dryer. While conventional components can provide a simple speed-triggered on-off switch for the motor or the heater, the present speed sensor approach can provide additional functions by discriminating between varying speeds. The speed sensor can also provide improved accommodation of a broken or slipping drive belt or other drive system problems by sensing the speed of a portion of the drum assembly rather than the motor speed. The speed sensor can replace the functions of multiple conventional components, simplifying the construction and reducing cost. The speed sensor can incorporate a solid state component which has lower cost and improved reliability over standard approaches.

Abstract: A circuit for driving at least one light emitting diode (LED) of a display based on a greyscale vector. The circuit includes brightness scale detection circuitry to determine a brightness value based on the greyscale vector and refresh cycle selection circuitry to output an indication of a subset of refresh cycles, referred to as dithered refresh cycles. The circuit also includes pulse width determination circuitry to define a pulse width based on the greyscale vector. Pulse adjustment control circuitry, for each dithered refresh cycle, determines a dithered pulse width by adjusting the pulse width by a width adjustment amount, and outputs a dithered pulse width modulation signal including a series of pulses including a pulse having the pulse width determined by the pulse width determination circuitry non-dithered refresh cycles and a pulse having the dithered pulse width for the dithered refresh cycles.

Abstract: In order to realize efficient memory access, addresses in the same bank in a memory are consecutively accessed. A data processing apparatus performs mapping so as to store data, which are the same data, with use of the first arrangement and the second arrangement, respectively, in different memory areas constituting a memory. When reading a portion of the data, a selecting unit selects one of the arrangements that is more efficient in accessing the portion of the data based on an address range corresponding to the portion of the data according to each arrangement, and an access control unit accesses a memory area corresponding to the selected arrangement. The data is mapped to a position different from a position of the data in terms of relative positions with respect to boundary addresses of blocks each corresponding to the same row address in the same bank.

Abstract: A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.

Abstract: A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: One embodiment of the present invention sets forth a technique for reducing the amount of memory required to store vertex data processed within a processing pipeline that includes a plurality of shading engines. The method includes determining a first active shading engine and a second active shading engine included within the processing pipeline, wherein the second active shading engine receives vertex data output by the first active shading engine. An output map is received and indicates one or more attributes that are included in the vertex data and output by the first active shading engine. An input map is received and indicates one or more attributes that are included in the vertex data and received by the second active shading engine from the first active shading engine.

Abstract: A display device that comprises a flag memory containing state flags of pixel areas of the image is provided. The display device comprises a display screen and a graphical generation unit implementing at least three functions for displaying an image, i.e. a first data erasure function, a second function for generating an image comprised of pixels in a first memory, and a third function for displaying the image by reading the pixels in said memory and controlling the screen, in which an image is divided into a plurality of separate pixel areas and in that each area is addressed by a flag, wherein the display device further includes a memory that stores the flag states so that the graphical generation unit can execute the display function on the basis of the flag states. The generation of images having a predominantly uniform background can, in particular, be used for application in aeronautics.

Abstract: A bit-resolution-extension method is provided. The resolution extension method includes normalizing n-m upper bit values of adjacent pixels based on an upper n-m bit value of each pixel of a sample image, analyzing a statistical distribution of a lower m bit value of the reference pixel by patterns of a set consisting of the normalized adjacent pixels, generating a memory address from normalized adjacent pixel values of the sample image, saving a representative value of the lower m bits by patterns to the memory address as a result of the analysis, normalizing adjacent pixel values based on each pixel value of an input image, generating the memory address from the normalized adjacent pixel value of the input image, reading a representative value of the lower m bits saved in the memory address, and adding the read lower m bits to the input image pixel values as lower bits.

Abstract: A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data.

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract: A data access apparatus has a memory portion including plural memory banks. A data storage control portion stores the pixel data in the plural memory banks with the pixel data being divided into the plural memory banks based on information on an access pattern of plural pixels set on a predetermined screen. A data access control portion reads pixel data relative to the plural pixels specified by the access pattern at the same time from the plural memory banks at each set position in which the set position of the access pattern moves from the start position thereof toward a pixel row direction. A selector portion transmits pixel data corresponding to respective pixels constituting each of the groups of pixels based on correspondence information on input and output. Each group of pixels includes a center pixel and peripheral pixels positioned at a periphery of the center pixel.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.

Abstract: Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

Abstract: The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.

Abstract: A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the memory address, checks if the first memory stores data corresponding to the selected part of the memory address, and transfers the data, for which it is determined that the first memory does not store the data, and which corresponds to the part of the memory address, from a second memory to the first memory. The data processing apparatus determines to change a part to be selected of the memory address based on the checking result indicating that the first memory does not store the data corresponding to the selected part of the memory address, and changes the part of the memory address corresponding to the characteristics of the memory address.

Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to a group of contiguous physical memory locations in a memory system, determining a first physical memory address for a first transaction associated with the footprint, wherein the first physical memory address is within the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits associated with the second transaction, and combining a portion of the first physical memory address with the set of least significant bits associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

Abstract: In a method of programming for image enhancement, a content addressable memory is accessed. At least one template is transferred into the content addressable memory. A random access memory is accessed. Enhancement data is transferred into the random access memory. Video data input is inputted into the content addressable memory. Enhancement data is outputted from the random access memory based on the video data matching at least one template.

Abstract: The invention is directed, in one embodiment, to a method for generating memory addresses for accessing an image in which each pixel in a group of pixels has a luma component, but shares chroma components with other pixels of the group. A preferred method includes providing a memory, having a plurality of first portions and a plurality of second portions. First memory addresses may be generated, each of which corresponds to one of the first portions. Each first address defines a storage location for the luma components of one of the pixel groups. Second memory addresses may be generated, each of which corresponds to one of the second portions. Each second address defines a storage location for the chroma components of at least one of the pixel groups.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: The apparatus has an evaluated value calculating means 102 for calculating the complexity of the object shape and the complexity of the modeling structure of the object CAD data input by the CAD data inputting means 101; a searching means 104 for searching the reference CAD data in the reference CAD data base 103 in accordance with the condition of said complexity; an evaluated value calculating means 106 for calculating the complexity of the object shape and the complexity of the modeling structure based on the searched reference CAD data; and a displaying means 105 for evaluated values obtained by the means 102 and the means 106 on the graphic representation defining its horizontal axis for the complexity of the object shape and its vertical axis for the complexity of the modeling structure. It will be appreciated that the man-hour for evaluating large amount of various models can be reduced by means of not using a CAD system.

Abstract: A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address. The cache memory includes first and second memories coupled together by a plurality of activation lines. The first memory has a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address. The second memory includes a corresponding plurality of data storage locations. Each data storage location is coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.

Abstract: A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

Abstract: Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circuitry and cost. This allows more textures to be associated with each graphics primitive, thereby improving image realism.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.

Abstract: In systems and methods for graphic reproduction of an image including textural information, multiple rows or blocks of texture data can be retrieved from system memory in response to the single read command. In this manner, efficient use of system bus is achieved, and an increase in the texture cache hit ratio is realized, leading to more efficient system operation, and reduced system bus usage for texture data retrieval.

Abstract: An apparatus according to an example embodiment of the present invention, may process data of a present span. During processing, data corresponding to an address of the start data of the next span may be prefetched from the external memory device based on information related to the presently processed data. The prefetched data may store in the cache memory.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.

Abstract: An image transformation apparatus is provided, which includes a modeling unit 5 that calculates the coordinates of vertices of each polygon and calculates a pre-filter coefficient corresponding to a reduction ratio at the position of a vertex of each polygon, with respect to a model to which an image is attached to; a texture address unit 6 that converts the coordinates of vertices of each polygon calculated in the modeling unit 5 into the coordinates of each pixel and sets a read address for attaching an image to the model using the coordinates of each pixel; a filter coefficient unit 7 that converts a pre-filter coefficient calculated in the modeling unit 5 into a pre-filter coefficient at the position of each pixel; an H-direction pre-filter 9, an HV scan converter 10 and a V-direction pre-filter 11 that perform filtering on input image data with a pre-filter coefficient obtained through conversion in the filter coefficient unit 7; a texture memory 13 to which image data filtered in the H-direction pre-fil

Abstract: A display driver having Dynamic Random Access Memory (DRAM) cells and a method of controlling the timing of the display driver are disclosed. The display driver includes memory cells each of which is implemented using a DRAM cell having a single transistor and a single capacitor. The display driver includes a drive control unit generating a scan signal, a refresh signal and a write/read signal, a word line drive unit driving word lines of the memory cells, and a data input/output unit for controlling input/output of data to/from the memory cells. The display driver gives priority to a write/read operation over a refresh operation and a scan operation.

Abstract: A display driver for sending display data to a display panel includes a sampling circuit and a selector. The sampling circuit receives moving image data and a sampling signal generated by a write signal and an address designated with an address decoder and captures the moving image data on the basis of the sampling signal. The selector receives still image data, a selecting signal and the moving image data captured by the sampling circuit and selects one of the still image data and the moving image data on the basis of the selecting signal.

Abstract: Apparatus, systems and methods for reducing memory bandwidth to texture samplers via re-interpolation of texture coordinates includes at least one texture sampler coupled to at least one shader core where the texture sampler is at least capable of generating texture map addresses by re-interpolating pixel fragment block texture coordinates from starting data and attribute deltas associated with the block.

Abstract: Systems and methods are provided for optimizing a parametrization scheme in accordance with information about the surface signal. A surface parametrization is created to store a given surface signal into a texture image. The signal-specialized metric of the invention minimizes signal approximation error, i.e., the difference between the original surface signal and its reconstruction from the sampled texture. A signal-stretch parametrization metric is derived based on a Taylor expansion of signal error. For fast evaluation, the metric of the invention is pre-integrated over the surface as a metric tensor. The resulting parametrizations have increased texture resolution in surface regions with greater signal detail. Compared to traditional geometric parametrizations, the number of texture samples can often be reduced by a significant factor for a desired signal accuracy.

Abstract: There are provided a drawing device and an information processing apparatus which are capable of reading out texture data from a memory at a high speed. A storage circuit stores respective information items of each of texture pixels constituting the texture data and at least one texture pixel in a vicinity of the each of the texture pixels, in a continuously-accessible region thereof. An address calculation circuit calculates, based on texture coordinates corresponding to each pixel of the polygons, an address where a corresponding set of the information items are stored. A readout circuit reads out the corresponding set of the information items from the address calculated by the address calculation circuit. A synthesis circuit synthesizes the corresponding set of the information items read out by the readout circuit. A drawing circuit draws, based on texture pixel information synthesized by the synthesis circuit, a corresponding pixel of the polygons.

Abstract: An arrangement for displaying a sequence of digital images is described, including a chip with a first memory for storing an increment image which can be combined with a first digital image in such a way that a second digital image arises, an off-chip second memory for storing the first digital image, a combining device, which combines the first digital image and the increment image in such a way that the second digital image arises, and a display device which displays the first digital image and the second digital image.

Abstract: A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memory in accordance with a first memory address allocation format and the memory addresses are decoded to access the addressable memory locations of a second block of memory in accordance with a second memory address allocation method different from the first memory address allocation format.

Abstract: A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. Based on the orientation of a display device, an address translation system either passes the software address “as is” or translates the address to represent a portrait-oriented display address. A refresh address generator operates alternatively in column-forward and column-reverse modes, and additionally operates alternatively in row forward and row reverse modes to selectively rotate the image.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.