Abstract: A video test tool for diagnosing video processing for interlacing is disclosed along with a video test tool for quantifying “jaggies” in a video display.

Abstract: A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.

Abstract: Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to be displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed.

Abstract: A jitter correction method of a transmitting device, a jitter correction method of a receiving device, a transmitting device, and a receiving device are provided. The jitter correction method of the transmitting device includes: determining a time stamp of a video frame; determining a transfer time of an real-time transport protocol (RTP) packet that includes at least a part of the video frame as a payload; generating the RTP packet including the time stamp and the transfer time; and transmitting the RTP packet to a receiving device.

Abstract: In a method of managing color output by appearance intent a color display value is received. The color display value comprises at least one appearance intent tag and is associated with an item of graphic content. The color display value is converted into an intermediate color value such that an appearance intent specified by the appearance intent tag is preserved in the intermediate color value. The intermediate color value is converted into an output color display value recognizable by an output device, such that the appearance intent is preserved in the output color display value.

Abstract: An improved display screen flicker detection and correction system. The system includes a flicker detection component. A test pattern is placed on a display screen to be tested and corrected. The flicker detection component is placed on or near the display screen. The flicker detection component senses the change in light level that results from the flickering screen. The display system is then adjusted to minimize flicker.

Abstract: The invention relates to a method, device and computer-program product for suppression of undesired temporal variations, notably flicker, in a sequence of video frames. Histogram-based and similar approaches generally do not remove all flicker. Features that are resolved only in portions of the flicker cycle will manifest themselves as residual flicker. This effect is near-universal in bright regions of a scene. The inventive solution is a mapping that aims to resolve in the output only those features that are resolved in all frames of the flicker cycle. Use of time-maximal quantile values may preserve non-resolution of such image features that are unresolved due to intermittent bright saturation. Thus, in one embodiment, a reduction of resolution is attained by means of a pixel-value mapping based on selecting, over a time window, maximal and minimal quantile values, with maximal values being used for bright spatial regions and minimal values for dark spatial regions.

Abstract: Disclosed herein is a method and apparatus for preventing and eliminating undesirable effects in displayed video. The method may include receiving video information and decoding the video information. The method may also include processing the number of illuminable lines associated with a video frame and blanking a remainder of the illuminable lines. Blanking the remainder of the illuminable lines may prevent and eliminate undesirable effects in the displayed video. The illuminable lines may be processed, such that each field may comprise an even number of corresponding, illuminable lines 530. The fields, however, are not required to have the same number of lines. In an embodiment according to the present invention, no active lines in one field may be below a blanked line in a corresponding field.

Abstract: An image data processor for generating driving image data for operating an image display device, including: an image memory; a write-in control section for sequentially writing-in plural frame image data having a predetermined frame rate to the image memory; a read-out control section for reading-out the frame image data 1 times (1 is an integer of 2 or more) at a rate 1 times the frame rate with every frame image data written into the image memory; and a driving image data generating section for generating the driving image data corresponding to each read-out image data sequentially read out of the image memory.

Abstract: A video signal processing apparatus generates a plurality of subframes from each frame of an input video signal to generate an output video signal having a frame frequency higher than the frame frequency of the input video signal. The output video signal also has a smaller number of tones than the number of tones of the input video signal. The pixel values of pixels corresponding to the plurality of subframes are set in accordance with the input video signal to represent halftones that are difficult to display with the number of the tones of the output video signal. The pixel values of the pixels corresponding to the plurality of subframes are set to yield a maximum distribution of the pixel values in a time axis direction.

Abstract: An automatic gain control device in a digital broadcast receiver is provided. The device is constructed to include an AGC for receiving an input signal and a predetermined power reference value to thereby obtain a gain error value, determining one of a plurality of operational areas according to a received AGC step control signal, and generating an RF gain control signal and an IF gain control signal according to the gain error value; and a lock detector for receiving the gain error value and the predetermined power reference value and thereby generating the AGC step control signal and an AGC lock/unlock signal.

Abstract: A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set value for every reference clock, extracting data according to the cumulative value, converting the data into an analog signal, reducing quantization noise, and multiplying the analog signal, thereby to obtain a second clock; and a clock switch circuit for generating a sync signal that is switched to the second clock, by using a sync signal generated with the first clock; and video signal processing is carried out using the second clock that is generated according to the resolution of a pixel display.

Abstract: System and method for digitally correcting time base errors in video display systems. A preferred embodiment comprises 1) correcting time base errors in a first portion of a horizontal line of video information, wherein the first correcting makes use of an error estimate for the horizontal line of video information and a preceding horizontal line of video information, 2) correcting time base errors in a second portion of a horizontal line of video information, wherein the second correcting makes use of an error estimate for the horizontal line of video information, and 3) repeating the first correcting and the second correcting for remaining horizontal lines of video information in the digitized video signal.

Abstract: An improved display screen flicker detection and correction system. The system includes a flicker detection component. A test pattern is placed on a display screen to be tested and corrected. The flicker detection component is placed on or near the display screen. The flicker detection component senses the change in light level that results from the flickering screen. The display system is then adjusted to minimize flicker.

Abstract: The invention provides a digital image stabilization apparatus for compensating a jitter occurred in the ith frame among N frames of a video sequence, where each of the N frames includes a plurality of blocks, N is a natural number larger than or equal to 3 and i is an integer index ranging from 1 to N. The apparatus includes a determining module, a comparing module and an adjusting module. The determining module is to determine a block of background region BRi-1 in the (i?1)th frame. The comparing module, coupled to the determining module, is to compare the block of BRi-1 in the (i?1)th frame with the corresponding block in the ith frame so as to determine a jitter vector. The adjusting module, coupled to the comparing module, is to adjust the ith frame in accordance with the jitter vector to compensate for the jitter occurred in the ith frame.

Abstract: The present invention relates to an image processing apparatus and method, a recording medium, and a program that can very sharply display video images which are subjected to frame rate conversion by suppressing a decrease in the image quality (blurred images) caused by imaging blur. A high frame converter 11 performs high frame rate conversion on an input moving picture. An imaging blur suppression processor 13 corrects each pixel value forming a subject frame based on at least one value corresponding to the subject frame of the parameter values representing imaging blur detected by an imaging blur characteristic detector 12. Accordingly, a moving picture having a higher rate than that of the input moving picture and having each pixel value suitably corrected to suppress imaging blur is output. The present invention is applicable to a television system.

Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the number of encoded frames, Fpred, in the decoder buffer and transmit the value, Fpred, to the receiver with the audio data. If the transmitter determines that the decoder buffer level is becoming too high, the frames being generated by the encoder are too small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming too low, the frames being generated by the encoder are too big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. An audio encoder marks a frame as “dropped” whenever a buffer overflow might occur. Only a small number of bits are utilized to process a lost frame, thereby preventing the buffer from overflowing and allowing the encoder buffer-level to quickly recover from the potential overflow condition. The audio encoder optionally sets a flag that provides an indication to the receivers that a frame has been lost. If a “frame lost” condition is detected by a receiver, the receiver can optionally employ mitigation techniques to reduce the impact of the lost frame(s).

Abstract: In a method and system for 3D comb synchronization and alignment of standard and non-standard video signals, a coarse synchronization is performed on a bottom frame, a current frame, and a top frame based on a bottom frame field count. The current frame is assigned the frame transferred immediately prior to a bottom frame whereas the top frame is assigned the frame transferred two frames. A current frame window signal and a top frame window signal may be used to lock the current frame and the top frame to a bottom frame vertical sync signal. After coarse synchronization, the video frames are finely aligned by correlating a phase difference between the subcarrier signals in each frame and modifying the phase difference until the correlation results in a specified phase locked value range. This method and system may facilitate the handling of video stream switching and non-standard data streams.

Abstract: In a method for altering a video sequence, a first portion of the video sequence is digitally stabilized in accordance with an initial set of image stabilization parameters and displayed to a user. An input from the user is accepted during the displaying. The user input defines a revised set of image stabilization parameters. A second portion of the video sequence is then digitally stabilized in accordance with the revised set of image stabilization parameters and is displayed to the user. A predetermined video frame rate is maintained continuously during and between the displaying steps.

Abstract: When performing A/D conversion on image signals, when reducing noise that is caused by jitter by adjusting the phase of the sampling clocks, even if the input waveform has considerable waveform distortion such as a triangular wave, it is possible to reliably reduce this noise. Input analog image signals are converted into digital image data using sampling clocks from a PLL circuit by A/D conversion means. Next, image data that has delayed by a 1 clock delay circuit is subtracted from the digital data by a subtracter. The maximum value of one screen of the subtracted output is then determined, and 5 is subtracted therefrom to provide a threshold value. A comparator compares the subtracted output and the threshold value, and outputs a signal when the subtracted output is greater than the threshold value. A counter then supplies the count value of these signals to a CPU, and the CPU controls the phases of the sampling clocks using a switch.

Abstract: A jitter canceling apparatus is provided for canceling jitter in a video signal. For processing a video signal, using as a reference an internal synchronization signal and an external synchronization signal different from the internal synchronization signal in the jitter canceling apparatus, an external synchronization signal generator generates the external synchronization signal from an external reference signal. A jitter detector detects time difference jitter, which is jitter in a time difference between the internal and external synchronization signals. The external synchronization signal generator controls the external synchronization signal generating operation in response to the detected time difference jitter to reduce the time difference jitter.

Abstract: A jitter correcting apparatus and method for a video signal in a video signal reproduction system includes a digital video decoder for demodulating an externally-applied video signal and a phase-locked loop for generating a first clock signal synchronized with the video signal. The system includes an address generator, a comparator and a dual port memory device. The address generator generates a write address for writing the video signal in response to the first clock signal, generates a read address for reading the video signal in response to a second clock signal having a fixed frequency, and corrects the write and read addresses in response to a head switching signal and first and second comparison signals. The comparator compares the write address with the read address and generates the first comparison signal and the second comparison signal according to a result of the comparison.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.

Abstract: A scheme to reduce clock jitter is disclosed in applications where video content is transmitted through multiple stages, each having a switch allowing that stage's video stream to be selected. The video data is re-clocked using a new clock at each stage. Before re-clocked, the video data from the preceding stage is scaled into a constant resolution using a digital scaler. Since the downstream stages could re-clock the video as if it were sent at the same frequency, there is no need to anticipate the changeable video frequency and to create the necessary low-jitter clock in programmable logic.

Abstract: Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an associated index, which is stored, and stored indices are statistically processed to select a tap of another delay line.

Abstract: A DPRAM is placed in the RF path before the digital to analog converter, to provide dynamic path gain compensation to the digital signal prior to conversion to an analog signal. The DPRAM stores corrections to the signal to compensate for amplitude losses in the signal arising from heat and non-linearities. The DPRAM has two sets of identical addresses. A logic switch, alternately directs an input signal to one of the two sets of addresses. Pre-calculated signal values which compensate for path gain are stored in one of the two sets of addresses in the DPRAM. The signal input to the DPRAM is directed to the other block. The value of the signal input to the DPRAM will determine the address to which the new value can be found. It is this new value which is actually input to the DAC and from which an analog signal is created.

Abstract: A mask circuit masks a digital video signal so that a video signal of an analog video signal is not outputted for a predetermined period after the start of output of a horizontal synchronizing signal of the analog video signal. A period of masking the digital video signal by the mask circuit is set in a control register, and the control register transmits the masking period to the mask circuit. A digital video signal to analog video signal converting unit converts the digital video signal masked and outputted from the mask circuit into an analog video signal. Thus, by setting in the control register the period of masking the digital video signal until the video signal of the analog video signal is stabilized, a digital video encoder can output a stable video signal.

Abstract: Error correcting section holds PTS(n?1) and DTS(n?1) of the frame immediately preceding the current frame and the most recent CPTS as determined to be correct in the past. The time stamp of the current frame is determined to be incorrect if (1) CPTS>PTS(n) which is the current frame or (2) CPTS<PTS(n) and greater than the time interval of time information B_TS(n)?B_TS(n?1) plus a reference time (e.g., the multiple of the standard frame interval 33 msec of moving images using 30 frames per second). If the PTS(n) of the current frame is correct, it is used as reproduction timing and updates the CPTS, using the PTS(n). If, on the other hand, the PTS(n) of the current frame is incorrect, it is not used and the time obtained by adding the CPTS and B_TS(n)?B_TS(n?1) is used as corrected PTS(n).

Abstract: The delay circuit composed of plural flip-flops converts an input data into plural data 110-0˜110-n having delays of 1˜n clocks, which are inputted to the selector of the selector circuit. The counter counts the pixel number per one line of the input data, and supplies a discrete value signal indicating the counted pixel number to the judgment circuit of the selector. The judgment circuit calculates a difference between the standard pixel number and the pixel number that the discrete value signal indicates, and calculates a new delay to the delay circuit on the basis of this calculated difference. The selector outputs an output data based on the new delay calculated. With a simplified circuit configuration as above, the pixel number for each line will be regulated into the standard pixel number.

Abstract: A translator demodulates a received digital television signal so as to produce a digital data stream, a symbol clock, and a byte clock, wherein the symbol clock and the byte clock are corrupted by phase noise. The digital data stream is written into a buffer in response to the corrupted byte clock. The corrupted symbol clock is applied to a frequency/phase locked loop having a narrowband loop filter. The frequency/phase locked loop produces a regenerated symbol clock having substantially no phase noise. The digital data stream is read from the buffer in response to the regenerated symbol clock. The digital data stream read from the buffer and the regenerated symbol clock are applied to a modulator for re-broadcasting of the received digital television signal.

Abstract: A method and apparatus is directed to reducing jitter of the position of an On Screen Display (OSD) associated with a display device. Multiple horizontal signals are produced in response to a vertical flyback signal and a horizontal flyback signal for the display device. Each of the multiple horizontal signals has a different phase. One of the multiple horizontal signals is selected such that its rising edge of the selected horizontal signal occurs at a separate time when compared to the rising edge of the vertical flyback signal. By ensuring that the rising edge of the selected horizontal signal is not coincident with the vertical flyback signal, jitter is minimized in the position of the OSD.

Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: Providing picture transmission apparatus, a picture transmission method and a recording medium, and a picture transmission program that can transmit the latest picture data in real time depending on the situation of the network bandwidth.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A wander gamut display for perturbation analysis is created by determining from a periodic input data signal and a reference clock a frequency offset and frequency drift rate for the input signal. The frequency offset and frequency drift rate are input to respective orthogonal axes of a Cartesian display together with a wander limit bounding box that defines the wander gamut. Values that fall outside the bounding box on the display indicate wander that may result in data errors.

Abstract: For horizontal sync information HD suitable for use in image processing module, e.g., module for TBC features, image compression recording/playback features, and LCD displaying features, it would be desirable that the time base fluctuations of the video input signal is faithfully reflected and that an interpolated HD generating feature is provided. A module for generating pulses generates the trailing edges of Csync as the trailing edge HD, and switches to an interpolated HD when a dropped pulse is detected after a few microseconds delay in the leading edge relative to the standard pulse. Thus, the trailing edge HD is selected within a time base fluctuation on the order of a few microseconds and the time base fluctuation is faithfully reflected and interpolation features can also be provided.

Abstract: There is provided an image signal repeater apparatus with a simple construction, which can prevent the accumulation of jitter even if the image signal repeater apparatuses are connected in multiple stages, and which enables the reception of image signals of various frequencies.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A horizontal automatic frequency control (AFC) used in a display having a display device such as a cathode ray tube (CRT) is provided. The AFC circuit reduces a horizontal distortion and horizontal jitter on the CRT. The AFC circuit includes a video signal processor for demodulating and converting an input video signal into a desired signal such as a YUV signal or an RGB signal, a synchronous separator for separating a synchronizing signal from the video signal, a dual-port line memory, an Hout generator for generating a horizontal driving pulse which drives a horizontal deflection yoke, a read clock generator for generating a read clock (RCK) signal which is synchronized in phase with a flyback pulse, and a horizontal deflection driver for controlling horizontal deflection of the CRT and generating the flyback pulse. The line memory absorbs a horizontal position change of a displayed image caused by a temperature change or a load change in the horizontal deflection driver.

Abstract: A jitter detection device for detecting jitter of a video signal (Sv) measures a vertical period (Stf(v)) of one field (v) of the video signal (Sv) to determine, based on a vertical period signal (Stf(v)), whether the video signal (Sv) jitters or not. If the number of times (Cej) it is successively determined that the video signal (Sv) jitters is smaller than a first predetermined number of times (Tej), the video signal (Sv) is confirmed to be a jitter signal (Svj). If the number of times (Cnj) it is successively determined that the video signal (Sv) does not jitter is smaller than a second predetermined number of times (Cnj), the video signal (Sv) is confirmed to be a non-jitter signal (Svjn).

Abstract: A receiver is constructed so that it detects a short-break of a digital broadcasting wave by the absence of a synchronizing code or by a transmission control signal multiplexed with the broadcasting wave and, according to the short-break detection signal, holds data and state information (program arrangement, and reference time information) obtained by an antenna and converter (1), tuner and digital decoding portion (2), an error correction code decoding portion (3), a stream multiplexed signal separating portion (4), an audio/video decoding portion (5) and the other components and performs a process for optimally changing characteristics of closed loops for establishing synchronization.

Abstract: A method, computer readable medium, and system are provided for synchronizing a slave clock time with reference time signals received from a master clock. A first basis set of reference time signals received from a master clock is collected. A first comparison set of slave time signals from a slave clock is identified such that each of the slave time signals in the first comparison set correspond with receipt of each of reference time signals in the first basis set. A difference between each of the reference time signals in the first basis set and the slave time signals in the first comparison set is calculated. An average difference between each of the reference time signals in the first basis set and the slave time signals in the first comparison set is then calculated and a slave time kept by the slave clock is adjusted by the average difference.

Abstract: A method of measuring MPEG PCR jitter, frequency offset and drift rate uses a selectable, constant measurement bandwidth over non-uniform PCR arrival times and a variable PCR rate. The selectable, constant measurement bandwidth is fixed at a frequency that demarcates between jitter and wander. For each received PCR value a PCR interval is determined from the arrival time of the current PCR value and the arrival time of the preceding arrival time. The PCR values, intervals and the fixed bandwidth are input to a set of difference equations, derived either from a hybrid digital-analog PLL model where the frequency offset, drift rate and jitter are extracted from various points in the PLL feedback control system or from a linear filtering approximation to a least mean square (LMS) frequency offset and an LMS drift rate estimator of a simple second order time equation for the PCR values.

Abstract: An inventive method for preventing focus flutter display in a TV receiver or monitor includes the steps of amplifying a received signal for driving cathode elements of a cathode ray tube, and delaying initial full amplification of the signal during the amplifying step for a duration sufficient to prevent focus flutter display on the tube. A corresponding inventive kine driver circuit that prevents display of focus flutter includes an amplifier for amplifying and coupling received video signals to cathode elements of a picture tube, and a control circuit for delaying full amplification of the video signals to be fed to the cathode elements for a duration sufficient to prevent focus flutter display on the tube.

Abstract: A method and apparatus for compensating for time base or phase errors in video and audio signals that are separately stored or processed. A ring oscillator provides a plurality of clock signals, each having a same frequency and slightly different phase. Each of the clock signals is applied to a multiplexor for allowing an appropriate one of the clock signals to be selected. By selecting appropriate ones of the clock signals in a sequence, the frequency and phase of an output clock signal formed by the multiplexor can be continuously and precisely controlled. Sync pulses separated from a video signal having a varying time base are applied to a video timing generator circuit which generates a series of digital values representative of timing differences between an expected occurrence of a sync pulse and an actual occurrence of the sync pulse. A phase accumulator accumulates the digital values over time for generating appropriate addresses for the multiplexor.

Abstract: Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.