Abstract: A device for receiving, storing and displaying television images. The device comprises a buffer (2) for storing television images. Television images having a first frame frequency are received at an input (4). Television images having a second frame frequency are supplied at an output (6). The buffer is adapted to store and read television images. A number of X consecutive television images stored in the buffer lie between a television image read at a given instant from the buffer and a television image stored at substantially the same instant. In a first state, X increases with time. In a second state, X decreases with time. The device further comprises a control device (12) for generating a first control signal (14) for bringing the device from the first to the second state, and a second control signal (16) for bringing the device from the second to the first state.

Abstract: The delay circuit composed of plural flip-flops converts an input data into plural data 110-0˜110-n having delays of 1˜n clocks, which are inputted to the selector of the selector circuit. The counter counts the pixel number per one line of the input data, and supplies a discrete value signal indicating the counted pixel number to the judgment circuit of the selector. The judgment circuit calculates a difference between the standard pixel number and the pixel number that the discrete value signal indicates, and calculates a new delay to the delay circuit on the basis of this calculated difference. The selector outputs an output data based on the new delay calculated. With a simplified circuit configuration as above, the pixel number for each line will be regulated into the standard pixel number.

Abstract: An apparatus and method for correcting jitter components of a television system which can be generated by an asynchronous signal applied externally as well as a truncation error are described. In the apparatus for correcting jitter of a television system having a horizontal driving signal generator for generating a horizontal driving signal in response to a system clock signal and a first synchronous signal, a first phase difference detector detects a first phase difference between the system clock signal and a second synchronous signal, the second synchronous signal being input from the outside of the television system, asynchronous with the system clock signal, and able to be set as the first synchronous signal. A jitter corrector corrects a jitter component included in the horizontal driving signal in response to the first phase difference and outputting a horizontal driving signal the jitter component of which is corrected.

Abstract: An image processing apparatus and method which can reduce the size of circuits for &agr;-blending and dithering and realize high speed processing which perform in parallel processing for finding an amount of update of present image data to be drawn with respect to image data already stored in a display buffer by using a blending coefficient in a subtractor and a multiplier and processing for adding noise data to the image data already stored in the display buffer in a first adder and adding the data obtained by the two processing at a second adder so as to find data comprised of noise data added to data obtained by linear interpolation of two colors, then extracting color valid values at a clamp circuit, thinning out the extracted data in a rounding-off circuit, and writing it back to the display buffer.

Abstract: Methods and apparatus for encoding, decoding and displaying images in a manner that provides for relatively smooth motion are described. In accordance with the invention a multi-sync display device is used and the refresh rate of the display device is controlled to minimize or avoid judder. Control of the display device refresh rate is performed in various embodiments, as a function of frame display, frame coding, field coding and/or image capture rate information included in an encoded bitstream. Alternatively, the refresh rate of a display is controlled as a function of decoding rate information or other information available from a decoder. In one exemplary embodiment, frames are displayed and the refresh rate of a display device is controlled to be an integral multiple of the indicated frame display rate included in an encoded bitstream.

Abstract: A method of smoothly displaying field videos in an interlaced display according to the invention. In a currently-exiting interlaced display system, the sequence of a scan timing with a top scan timing, a bottom scan timing, a top scan timing, a bottom scan timing . . . , should be consistent to that of field number with a top field, a bottom field, a top field, a bottom field, . . . In the invention, a top or bottom field can be inserted/skipped right after any one field displayed. During inserting/skipping, a new top field which is created from the bottom field or a new bottom field which is created from the top field, is displayed at a corresponding scan timing, thereby efficiently preventing a TV screen from jitters, resulting in smooth display.

Abstract: A method and apparatus to improve the vertical alignment of images captured from video. The method shifts a current scanline by an alignment offset detected locally between either the two fields of the image or within a field of the image itself. This aligns the current scanline to more closely correspond with adjacent intra-field or inter-field scanlines, thereby reducing wiggles or jitters in the vertical lines of the image.

Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

Abstract: Jitter of a Program Clock Reference (PCR) in a transport stream of an Moving Picture Experts Group (MPEG) signal transmitted over Asynchronous Transfer Mode (ATM) system is reduced by correcting PCR to PCR−(T−&dgr;) if |PCR−STC|>T−&dgr;−&Dgr; is true and (PCR−STC)>0, correcting PCR to PCR+(T−&dgr;) if |PCR−STC|>T−&dgr;−&Dgr; is true and (PCR−STC)<0, and making no correction if −PCR−STC−>T−&dgr;−&Dgr; is false. The program clock reference received is represented by PCR, a system time clock at the time when the program clock reference is received is represented by STC, a period of a transport stream packet at an output terminal of an MPEG encoder is represented by T, a packet transmission time of the transport stream packet at an input terminal of the apparatus is represented by &dgr;, and a tolerable range is represented by &Dgr;.

Abstract: There is provided herein a system for reducing artifacts associated with multi-threaded video coding. The system generates a virtual thread from the multi-threaded data. The virtual thread combines the multi-thread data with estimates of virtual thread data in a manner that variably weights the combination according to motion information decoded from the multi-thread. A post-processing system is described that generates a single, virtual thread of video data, based upon image and motion data from a plurality of different threads in a multi-threaded video stream. The system estimates motion vectors for the virtual thread, generates frames of estimated video data, and applies the estimated frames to a filter. The filter generates an output that combines each new estimated frame with the current reference frame on a pixel-by-pixel basis.

Abstract: Television receivers are increasingly making use of digital signal processing. Present-day television receivers use a line-coupled clock system in this case, since this produces an orthogonal pixel array for signal processing on the picture screen. The disadvantage of such a clock grid resides in its problematical generation, in particular when video recorders are used as signal source. According to the invention, video signals are digitized and processed by means of a free-wheeling system clock made from a quartz oscillator. In order not to have to use large buffer memories, the vertical deflection is synchronized with the input signal, but the number of lines per field or frame is varied.

Abstract: A video signal mixing apparatus and a method thereof, which is capable of minimizing timing jitter caused when onsynchronized video signals are digitally mixed. A signal subtractor subtracts a second video signal synchronized with a clock signal from a first video signal which is not synchronized with the clock signal, and a weighted value extractor divides one period of the clock signal into N intervals, detects the interval where a digital selection signal is generated, among the N divided intervals, and outputs a predetermined value (where 0≦predetermined value≦1) allocated to the detected interval as a weighted value. A multiplier multiplies the weighted value with the output of the signal subtractor and outputs the multiplication result, and a signal mixer mixes the multiplication result with the second video signal and outputs the mixed result as a mixed video signal. Therefore, error causing timing jitter is reduced to 1/N, thereby minimizing dot crawling of the mixed image.

Abstract: A jitter detecting circuit firstly compares a target signal with a reference clock signal to see whether or not a phase difference takes place between the target signal and the reference clock signal, and, thereafter, the phase difference in each clock cycle is compared with the phase difference in the previous clock cycle for producing a detecting signal representative of cycle-to-cycle jitter when the phase difference is varied.

Abstract: A method and apparatus for reducing jitter and wander on the internetworking between ATM network and PDH network is disclosed.

Abstract: A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd0 is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd1 through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd1 through Ckdn. The output circuit outputs one of the correction subject signal Ckd0 and the delayed signals Ckd1 trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.

Abstract: A video signal processing apparatus comprising an oscillating unit for outputting a signal of a stable frequency, a counting unit for counting the period of a cycle of a signal supplied from the outside based on the signal output by the oscillating unit, a clock number calculating unit for calculating the number of clocks in a line based on a result of counting by the counting unit, a comparing unit for comparing the number of clocks calculated by the clock number calculating unit with a threshold to decide which is larger, a switching unit for deciding the number of clocks in the next operation by switching to the number of clocks calculated by the clock number calculating unit if the calculated number of clocks is larger than the threshold, or deciding the number of clocks in the next operation by holding the number of clocks in a line in the current operation as it is, and a synchronizing signal generating unit for, based on the number of clocks in operation decided by the switching unit and the signal out

Abstract: An apparatus having various on-screen display (OSD) functions and methods for each function are provided. The apparatus includes an on-screen display device for receiving serial data having a RAM write address, a ROM address, and the on-screen display functions. The apparatus synthesizes a character signal corresponding to serial data with a background color signal or an external composite video signal in response to an internal or external composite synchronous signal and provides the result to a monitor. The apparatus also includes a synchronous signal generating device for generating internal horizontal and vertical synchronous signals upon receiving a main clock signal, synthesizing means for synthesizing an internal equalization pulse with the internal horizontal and vertical synchronous signals, and means for determining the internal composite synchronous signal or the external composite synchronous signal extracted from the composite video signal. A control device is also part of the OSD apparatus.

Abstract: An apparatus for composing two screens in a television which is capable of solving the problems of a jitter and a screen being cut off at the top and bottom portions caused by a non reference signal in composing two screens, includes a line memory for storing in the unit of lines a video signal for a main screen converted into a digital signal, a frame memory for storing in the unit of frames a video signal for a sub-screen converted into a digital signal, a mixing unit for receiving and mixing the outputs from the line memory and the frame memory to compose two screens, a D/A converter for converting an output from the mixing unit into an analog signal, an encoder for encoding an output from the D/A converter and outputting a double screen signal, a clock signal generator for receiving the horizontal synchronous signals for a main screen and a sub-screen, generating a clock signal corresponding thereto, dividing a horizontal fly back signal in a predetermined number in accordance with a division control sign

Abstract: An image information processing apparatus is described that suppresses noise generated in digital signal processing while preventing the circuit scale from enlarging. The apparatus includes a separator, a first detector, a second detector, a phase-locked loop, an A/D converter, a phase difference detector, a chrominance data processor and a luminance data processor. The phase difference detector detects a phase difference between the reference clock signal and the scan sync signal. The luminance data processor combines the luminance data in Units of two pieces to produce compensated luminance data in accordance with the phase difference.

Abstract: The present invention relates in general to a digital-signal processing apparatus as well as a digital-signal processing method and, in particular, to a jitters removing apparatus as well as a jitters removing method. In the apparatus provided by the present invention, a TV signal received by a tuner or a video signal supplied by a VCR is fed to a moving-average correction circuit and a first FIFO circuit. In a correlation-value computing circuit, correlation between a carrier chrominance signal extracted by the moving-average correction and a carrier chrominance signal delayed by a second FIFO circuit by a predetermined time is found and a correlation value having a maximum absolute value is supplied to a quantization circuit. In the quanitization circuit, the quantization value is quantized to determine a class code. Then, coefficients for taps indicated by the class code are read out from a coefficient ROM unit and supplied to a linear first-order weighed-sum computing circuit.

Abstract: A sync signal correction circuit generates a corrected sync signal which is obtained by correcting a timing of a sync signal on the basis of a time axis variation component (jitter component) of the sync signal separated from a picture signal. The corrected sync signal is used as the sync signal to cause a variation of time axis error of the picture signal to follow a variation of time axis error of an output signal of an automatic frequency control (AFC) circuit which constitutes a monitor device for reproducing and displaying the picture signal, such that the variation of time axis error of the output signal of the AFC circuit and the variation of time axis error of the picture signal of the reproduced picture signal are cancelled each other to prevent jittere from appearing on a display screen.

Abstract: A video memory device is provided with a memory circuit, a write control circuit for controlling writing to the memory circuit by utilizing the horizontal synchronizing signal of a video signal input to the memory circuit, and a read control circuit for controlling reading from the memory circuit by utilizing the horizontal synchronizing of a video signal output from the memory circuit.

Abstract: A first information (I) is displayed on a display screen of a display device (5). A vertical and horizontal position of a field of the first information (I) on the display screen is determined by a vertical start pulse (V) and by horizontal start pulses (H), both corresponding to or being extracted from the first information (I). The vertical position of a second information (Oi) on the display screen is determined by counting a certain number of the horizontal start pulses (H). To eliminate any remaining jitter, a time difference (Td) is determined between the active edge of the vertical start pulse (V) and that horizontal start pulse (H) which is nearest to the active edge of the vertical start pulse (V). If this time difference (Td) is smaller than a certain safe margin (Ni), the nearest horizontal start pulse (H) is so close to the active edge of the vertical start pulse (V), that an occurrence of vertical jitter is becoming likely.

Abstract: A picture decoder which prevents picture jitter when operating in a fast play mode. The picture decoder has a picture jitter preventing apparatus, which includes a picture coding extension region detector for detecting a picture coding extension region from picture data coded according to the MPEG2 standard, information region detector for detecting a region having top.sub.-- field.sub.-- first and repeat.sub.-- first.sub.-- field information from the detected picture coding extension region signal, and an information converter for converting values of top.sub.-- field.sub.-- first and repeat.sub.-- first.sub.-- field into 1 and 0, respectively, when in the fast play mode, and outputting the picture data free of jitter.

Abstract: An arrangement (apparatus and method) for monitoring jitter caused during transport of digitally-coded information in a packet switched network, and for managing network operations in accordance with the detected jitter. The detected jitter is used to determine whether corrective action is necessary, such as rerouting network traffic, or performing network maintenance. The disclosed arrangement detects program clock reference (PCR) values from an MPEG-encoded transport stream, whereby each pair of PCR values represents an expected arrival time of a corresponding stream segment. An actual arrival time for the corresponding stream segment is determined in response to detection of the corresponding PCR values and an independent clock signal. The expected arrival time of the stream segment and the actual arrival time are correlated with an accumulation of expected and actual arrivaimes of previously-received data packet stream segments in order to determine the jitter in the digital data stream.

Abstract: A buffer occupancy control method is provided in order to properly control a buffer occupancy of a decoder. The intial time delay indicated in data received by the buffer is extended and the capacity of the buffer is expanded according to the additional amount of data inserted during the extended initial time delay, thereby preventing the buffer from overflowing and underflowing. In particular, when a bitstream encoded with a frame rate of 24 Hz is decoded according to a display field frequency of 60 Hz, excellent images can be regenerated without requiring additional components.

Abstract: A system and method for use in a video transmission network that regulates the timing of both the video signal and the audio signal regardless of the transport mechanism used to deliver the digitized audio and video signals from the source to a set top box, comprising replacing a program clock reference when it is present in ones of the audio and video transport packets with a new time derived from a high reliability source. A constant value is then derived from the new PCR value to be added to a program time stamp and a decode time stamp, if present, and the buffer size is increased merely by the amount of the constant times the bit rate of delivery of the packets.

Abstract: A color television signal, digitized by a sampling clock asynchronous with respect to the television signal's horizontal synchronizing pulses, is applied to a dynamically programmable digital filter which upsamples or downsamples the received digitized television signal over short time periods in response to time-base disturbances in the signal. The user may also select a higher or lower long-term clock frequency. Resampled digital samples are applied to a FIFO memory for readout at a clock rate which follows the time-averaged horizontal frequency of the received digitized television signal, or, alternatively, at a substantially fixed clock rate, asynchronous with respect to the horizontal line frequency of the received digitized color television signal.

Abstract: Encoder/decoder buffer overflow and underflow encountered when employing actually variable or effectively variable bit-rate channels for communicating encoded video images and corresponding audio signals are overcome by adjusting the parameters of a video encoder in response to a representation of cell delay variation, i.e., jitter, determined at a remote decoder.

Abstract: An ATM/MPEG system receives individual MPEG programs of different constant bit rates from a plurality of servers. The individual programs are converted into ATM cells which are transmitted along an ATM network at a constant bit rate. The ATM cells are received and arranged into queues of the individual programs. A microprocessor prioritizes the queues based upon the bit rates of the MPEG programs. The queues are multiplexed to 16 VSB modulators based upon their priority assignments with the highest priority queues being sent to the modulators in preference to lower priority queues.

Abstract: A digital time base corrector uses a memory with a reduced storage capacity, to reduce the cost. Absolute value data of an amplitude and polarity data of a burst signal in a color video signal are written into a memory every horizontal scan period. A signal in which a sync signal interval, a pedestal level interval, and a burst signal interval in the color video signal are eliminated is written as image data into the memory. The absolute value data, polarity data, and image data are read out from the memory. Burst signal data is reproduced on the basis of the absolute value data and polarity data. By inserting the burst signal data, sync signal data, and pedestal level data into the image data, a color video signal is reproduced.

Abstract: A video signal processing apparatus, video signal recording/reproduction apparatus, and method therefor, perform arithmetic operations upon an input video signal and the input signal delayed by a predetermined amount of time. A memory stores the input signal for the predetermined amount of time in order to produce the delayed input video signal. A controller controls the memory to store the input video signal for the predetermined amount of time based on a main synchronization signal. A first synchronization signal is produced by separating a synchronizing signal from the input video signal. A second synchronization signal is generated based on the first synchronization signal. During operation, a switching unit supplies the first synchronization signal to the controller as the main synchronization signal until the second synchronization signal becomes synchronized with the first synchronization signal.

Abstract: Encoder/decoder buffer overflow and underflow encountered when employing actually variable or effectively variable bit-rate channels for communicating encoded video images and corresponding audio signals are overcome by adjusting the parameters of a video encoder in response to a representation of cell delay variation, i.e., jitter, determined at a remote decoder.

Abstract: An apparatus for correcting a time base of a video signal generates a clock which is phase-synchronized with a sync. signal of the video signal and has the same frequency. In a special reproducing mode, the apparatus switches an output level of a phase comparator, which phase-compares the sync. signal and the clock to a predetermined level, which is applied to a controlled oscillator and resets a frequency divider which frequency-divides the output of the controlled oscillator, in accordance with the sync. signal to produce the video signal which can be visually recognized even in the special reproducing mode. The apparatus samples and holds the output level of the phase comparator when the video signal drops out and resets the frequency divider which produces the clock by frequency-dividing the output of the controlled oscillator, when the dropout is recovered so that a video signal of high quality is produced immediately after the recovery of the dropout of the video signal.

Abstract: Jitter of an overlay display with respect to the primary display of a television receiver is avoided by assuring that the vertical and horizontal blanking signal components are sufficiently time spaced by preventing the number of clock pulses occurring between the horizontal and vertical components of the blanking signal from going below a selected number. The number of clock pulses between the negative going transition of the vertical blanking signal and the positive going transition of the first horizontal blanking signal is tracked and when the number of pulses fails to exceed a reference value the number of pulses is changed to effectively shift the transitions with respect to one another.

Abstract: The invention relates to a video signal memory equipment comprising a FIFO memory for storing video data of video signals, and a control unit for controlling writing and reading in the FIFO memory, wherein the control unit receives a horizontal synchronizing signal of video signal in video data writing action, writes a specified number of video data from the beginning of video data of brightness signals of the horizontal scanning period sequentially into the FIFO memory, and reads out the specified number of video data upon every input of horizontal synchronizing signal, in video data reading action, in the written sequence as video data of that horizontal scanning period, thereby storing and producing the video data of video signals, whereby video data of each horizontal scanning period of video signals are continuously written into the FIFO memory by every specified number of pieces from the beginning, and are read out by every specified number of pieces upon every input of horizontal synchronizing signal,

Abstract: A digital time base corrector, when using a memory whose storage capacity is reduced to a value of about 1H of the video signal, can maintain an interleave relation between a luminance signal and a color signal of a video signal even when the writing operation into a memory is delayed by a jitter included in the demodulated video signal. When the read address is advanced from the write address in each of an image data memory and a subcarrier phase memory in one horizontal scan period, a discrepancy occurs between the polarity data read out from the subcarrier phase memory and the proper polarity data held in latch means. When such a discrepancy is detected, the color phase of the read-out image data is inverted. In starting the data reading operation for a new horizontal scan period, if it is detected that the operating mode has not shifted to the data writing operation for the new horizontal scan period, the color phase of the read-out image data is inverted for the new horizontal scan period.

Abstract: A digital time base corrector which can perfectly eliminate residual errors. A sync clock signal whose phase is synchronized with a time base fluctuation included in a reproduction video signal is formed in accordance with at least one of the horizontal sync signal and the color burst signal which are separated from a reproduction video signal. The sync clock signal is phase-modulated in accordance with a burst error signal indicative of the time base fluctuation of the color burst signal in a period of time other than the generating period of time of at least the color burst signal in the reproduction video signal, thereby obtaining a write clock signal of the image memory.

Abstract: A time base correcting apparatus for removing time base errors from video signals in a video tape playback device which is operable in either a first normal or high speed operation mode or a second still motion or slow speed operation mode. In the first operation mode, first and second fields are reproduced in succession from successive tracks and in the second operation mode, the same field is reproduced at least twice in succession from the same track. The video signals are received and stored in a memory. First and second synchronizing signals corresponding to the first and second fields are alternately generated and include equalizing, vertical and horizontal sync pulses. Corrected first and second synchronizing signals are selectively generated during the second operation mode as a function of whether the second field or the first field is reproduced twice in succession.

Abstract: An apparatus for correcting a time base error of a video signal. Signal portions of the video signal are sequentially written in memories with a write clock signal synchronizing with the video signal at specific write timings and sequentially read from the memories with a read clock signal of a constant frequency at specific read timings. At least one of the read timings are changed so that a correlation among the signal portions sequentially read from the memories remains unchanged when a difference between the write and read timings are smaller than a reference value.

Abstract: A system for synchronizing asynchronous video signals with a reference signal for input to a digital video processing system has a first-in, first-out (FIFO) buffer for each input signal that writes the digitized video signal into the FIFO under control of an input clock signal derived from the digitized video signal, and reads the digitized video signal from the FIFO under control of the reference signal. An input state machine monitors the digitized video signal at the input and the occupancy of the FIFO to provide a write enable signal to the FIFO so long as the FIFO is not in danger of overflowing. An output state machine monitors the digitized video signal at the output and the occupancy of the FIFO to provide a read enable signal to the FIFO so long as the FIFO is not in danger of underflowing.

Abstract: This specification concerns signal processing apparatus for processing line synchronization pulses in a line synchronization signal that define an analog video signal line period. The apparatus comprises a phase locked loop (40) for generating a clock signal of a frequency that is a multiple of the line synchronization signal frequency. The phase locked loop (40) comprises a counter (100) for dividing the clock signal by said multiple. The apparatus further comprises logic (110,50) for resetting the counter (100) upon detection of a spurious pulse introducing a time interval into the line synchronization signal of less than the line period of the video signal. The apparatus is particularly useful in image processing systems for digitizing analog video signals that have been replayed via a conventional, domestic video tape player, and therefore may comprise spurious line sync pulses introduced by playback head skip.

Abstract: A video signal processing device comprises: a unit for extracting a first color burst signal from a first video signal; a unit for generating a first subcarrier in synchronism with the first color burst signal extracted from the first video signal; a unit for extracting a second chrominance signal and a second color burst signal from a second video signal; a unit for demodulating the second chrominance signal and the second color burst signal on the basis of the first subcarrier to obtain a demodulated second color signal and a demodulated second color burst signal; and an operating unit for performing operation process of the demodulated second color signal on the basis of the demodulated second color burst signal in a manner such that the demodulated second color signal is converted into a corrected color signal which is substantially the same as an imaginal second color signal which is obtained on the assumption that the second chrominance signal is demodulated on the basis of a second subcarrier synchroni

Abstract: An image information transmission system of the kind receiving a transmitted analog image signal and forming digital image data by sampling the received analog image signal is arranged to control the timing of sampling according to the level of data of a specific part of the digital image data formed. The arrangement enables the system to accurately transmit the image information without being affected by time base variations caused by transmission.

Abstract: A circuit for detecting a jitter of an image signal reproduced from a recording media, comprises a variable oblique wave generating circuit for generating an oblique wave at timing according to the phase of the output pulse of a frequency dividing circuit wherein a tilt of the oblique wave is varied by an input control signal a sample-hold circuit for sampling and holding the tilt portion of the variable oblique wave in dependence upon reception of a horizontal synchronizing signal as a sample pulse.