Abstract: Time stamp replication within wireless networks is described. In an embodiment, a wireless station receives an input time stamp and uses this input time stamp to generate an output time stamp. The wireless station transmits the output time stamp to wireless stations in one of a number of groups which make up the wireless network. The output time stamp is generated to compensate for delays between receiving the input time stamp and transmitting the output time stamp such that output time stamp which is transmitted at a time T corresponds to the value that the input time stamp would have had if it had been received at time T (and not at a time earlier than T). This may, therefore, reduce or eliminate independent time stamp errors and jitter caused by multiple disparate systems and processes.

Abstract: A merchandising system that improves the merchandising of product by limiting the number and the frequency with which product can be removed from, for example, a merchandising shelf. The merchandising system may include a base configured to support product and a housing configured to engage the base. The housing may comprise a top wall, a first side wall, a second side wall, and a front retaining wall. The merchandise system may be configured to hold a number of products, such as cans (for example, baby formula cans) in the merchandise system that would be accessible to the customer one at a time out of the front of the merchandise system. The front of each merchandise system may include its own individual security window attached to the merchandise system that allows the customer to remove one can at a time.

Abstract: Systems and methods are operable to correct synchronization between a video stream and an audio stream presented to a user. An exemplary embodiment receives a synchronization correction instruction, wherein the synchronization correction is configured to be initiated by the user; and incrementally adjusts one of the video stream and the audio stream by a synchronization correction, wherein the synchronization correction advances or retards presentation of at least one of the video stream and the audio stream by a predefined duration.

Abstract: The time necessary for specifying an improper video signal is significantly reduced. An input signal determination circuit and a signal distribution circuit are included, the input signal determination circuit determining, for video signals to be input to a synchronization circuit, whether or not each of the video signals satisfies a display reference for performing video display in a division display area corresponding to the video signal, the signal distribution circuit distributing, for another proper video signal for a video signal determined by the input signal determination circuit to be a video signal that does not satisfy the display reference for performing video display.

Abstract: A display signal processing system, a circuit board, and a liquid crystal display are disclosed. The display signal processing system includes an image processing circuit and a V-by-One circuit capable of selecting a JEIDA mode and a VESA mode. A GPIO of the V-by-One circuit is for selectively inputting a first or a second selection signal such that the V-by-One circuit transforms the converted display signal to be a first LVDS signal under the JEIDA mode or a second LVDS under the VESA mode. The first LVDS or second LVDS signal is output by a signal output. The selection between the VESA mode and the JEIDA may be achieved by a simplified V-by-One circuit. In addition, the display signal processing system retains the advantage of lower cost and simple operations.

Abstract: Compatible video signal information having first information indicating a pixel number of a video signal displayable by a video display apparatus and second information that is setting information required in order for the video display apparatus to display a video signal having the pixel number is transmitted to a video output apparatus. In the case where a video signal received from the video output apparatus after the compatible video signal information is transmitted is a video signal having a pixel number displayable by the video display apparatus but not being displayable, the compatible video signal information is updated so that setting information for the pixel number of that video signal is included in the second information.

Abstract: According to one embodiment, an information processing apparatus includes a receiver configured to receive content, an acquiring unit configured to acquire a time required for reproducing the content, a counter configured to count a first time including at least the required time, and a display controller configured to display the content on the display unit and terminate display of a video on the display unit after expiration of the first time.

Abstract: A method for embedding an image in a video sequence for a mobile terminal. Preferably, the mobile terminal is a tablet or smartphone. The method comprises the steps of choosing an image to be embedded, reading the video sequence, displaying a frame, and determining the presence of an embedding zone in the frame. The embedding zone having been previously identified or deduced according to a predefined algorithm. The method further comprises the step of applying a deformation to the image to be embedded such that the image to be embedded coincides with the form of the embedding zone. The image combining the frame and the image to be embedded is displayed/disposed in place of the embedding zone.

Abstract: According to one embodiment, an electronic device includes a reproduction controller and a transmitter. The reproduction controller is configured to reproduce a first type of information of a first content. The first content includes a plurality of types of information. The transmitter is configured to transmit an instruction to reproduce a second type of information of the first content to other electronic device.

Abstract: A timing control apparatus includes: an extraction unit that outputs an input timing signal of an image signal; an input timing switch unit that selects whether to output the input timing signal output from the extraction unit or to input an external input timing signal; an input timing delay addition unit capable of adding delay information to the input timing signal output from the extraction unit; a reference timing generation unit that generates a reference timing signal from the input timing signal; a reference timing switch unit that selects whether to output the reference timing signal or to input an external reference timing signal; and an individual timing generation unit that generates, from the reference timing signal, a video processing timing signal and an output timing signal.

Abstract: Compatible video signal information having first information indicating a pixel number of a video signal displayable by a video display apparatus and second information that is setting information required in order for the video display apparatus to display a video signal having the pixel number is transmitted to a video output apparatus. In the case where a video signal received from the video output apparatus after the compatible video signal information is transmitted is a video signal having a pixel number displayable by the video display apparatus but not being displayable, the compatible video signal information is updated so that setting information for the pixel number of that video signal is included in the second information.

Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.

Abstract: An HDMI® source determines whether or not an HDMI® sink can receive a sub-signal based on VSDB of E-EDID. When the HDMI® sink can receive the sub-signal, the HDMI® source adds a sub-signal to pixel data of a main image composed of pixel data whose number of bits is smaller than that of transmission pixel data transmitted by a transmitter, thereby constructing transmission pixel data. This data is transmitted by the transmitter through TMDS channels #0 to #2. Furthermore, the HDMI® source transmits a general control packet containing sub-signal information indicating whether or not the sub-signal is contained in the transmission pixel data in the control period of a vertical blanking period. The present invention can be applied to, for example, HDMI®.

Abstract: High definition media content processing techniques are described in which enhanced media content rendering techniques may be performed to output high definition media content. In an implementation, luma keying may be provided to define clear pixels in a composite output using an optimum set of graphics processing instructions. In another implementation, techniques are described which may provide clear rectangles in a composite output of one or more video streams. Clear rectangles to appear in the composite output are configured by a media playback application. A texture is arrived at to represent a union of each of the clear rectangles and is applied to form the clear rectangles in the composite output. In another implementation, capture techniques are described in which an image to capture is resolved as strips to an intermediate texture and then from the texture to a capture buffer in system memory.

Abstract: An image signal processor and a method for processing an image signal thereof are disclosed. When the image signal processor executes an automatic chroma gain control (ACC), the image signal processor adjusts a variable rate of ACC gain according to a size of an input color signal to reduce a time for processing the ACC. Even if a difference between the size of the input color signal and the size of a reference color signal is large, the ACC is rapidly processed. As a result, transient phenomenon disappears from a screen.

Abstract: A timing control apparatus includes: an extraction unit that outputs an input timing signal of an image signal; an input timing switch unit that selects whether to output the input timing signal output from the extraction unit or to input an external input timing signal; an input timing delay addition unit capable of adding delay information to the input timing signal output from the extraction unit; a reference timing generation unit that generates a reference timing signal from the input timing signal; a reference timing switch unit that selects whether to output the reference timing signal or to input an external reference timing signal; and an individual timing generation unit that generates, from the reference timing signal, a video processing timing signal and an output timing signal.

Abstract: A synchronous signal conversion circuit converts a first synchronous signal, which is transmitted with a data signal, to a second synchronous signal conforming to a predetermined standard. In the synchronous signal conversion circuit, a transition detection circuit detects transition of the first synchronous signal. A synchronous signal generation circuit generates a second synchronous signal in response to a detection result by the transition detection circuit. An output timing control circuit delays the second synchronous signal generated by the synchronous signal generation circuit so that the second synchronous signal synchronizes with the data signal.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: An image distributing apparatus, a display apparatus, and an image distributing method thereof are provided. The image distributing apparatus includes: an image input unit which receives an input signal comprising an image signal and a first sync signal for synchronizing a display of the image signal; a sync signal regeneration unit which generates a second sync signal having a frequency that is different from a frequency of the first sync signal; and an image output unit comprising at least one output port to output the image signal and the second sync signal. Accordingly, a plurality of display apparatuses connected to the image distributing apparatus can synchronize a time with an image is displayed with each other.

Abstract: Text data is extracted from image data read by an image reader. Log data containing the extracted text data is generated. The generated log data is stored in a log management server.

Abstract: Disclosed herein is a transmitting device, including: a reproduction time information adding portion configured to add reproduction time information specifying timing of reproduction of data as an object of transmission to the data; a control time information adding portion configured to add control time information specifying control timing when circuit control is performed on a circuit, the data being to be transmitted through the circuit, to data transfer control information; and a transmitting portion configured to transmit data to which the reproduction time information and the control time information are added.

Abstract: A wired communication port comprising a transmitter operative to transmit, over a set of wires, a first transmission comprising a digital video clock multiplexed with a first direction of a bidirectional data channel. The transmitter is further operative to transmit video pixel data and video synchronization data over the same set of wires. And a receiver operative to receive a second transmission comprising a second direction of the bidirectional data channel, over at least a subset of the set of wires utilized for the first transmission.

Abstract: A multiplexed transport interface (MTSIF) may be utilized during communication between a demodulation module and a video processing system-on-chip (SoC). The MTSIF may enable concurrent demodulation of a plurality of input modulated video streams, via a plurality of demodulator chips within the demodulation module, by multiplexing data generated by the demodulator chips via the MTSIF during communication between the demodulator module and the video processing SoC. The MTSIF may also be utilized for communicating control signals, which may be used in controlling and/or managing operations of the demodulation module, the video processing SoC, and/or the MTSIF. Communication via the MTSIF may be synchronized. Packets communicated via the MTSIF may be timestamped. Timestamp counters may be used in the demodulation module and the video processing SoC to generate and/or track timestamps in communicated packets. The timestamp counter may be synchronized, using control signals communicated via the MTSIF.

Abstract: The invention concerns receive circuitry for extracting horizontal and vertical synchronization signals from a digital synchronization signal associated with a video signal, the digital synchronization signal having a plurality of pulses, the receive circuitry including detection circuitry arranged to determine a first value indicative of the time delay between a timing edge of a first pulse and a timing edge of a second pulse of the digital synchronization signal; and a synchronization extraction block arranged to determine that one of the plurality of pulses is a vertical synchronization pulse based on a comparison between the first value and a reference value.

Abstract: To improve accuracy of determining the average brightness level and maximum and minimum levels of the brightness signals for the entire screen. There are included a differential operation circuit that detects and differentiates rise or breaking edges in horizontal and vertical synchronous signals of an input image signal, thereby outputting horizontal and vertical differential signals synchronized with the horizontal and vertical synchronous signals, respectively; a sample window circuit that detects the beginning and ending positions of horizontal and vertical intervals to produce sample window signals established in any desired vertical and horizontal positions on the screen in accordance with the horizontal and vertical differential signals; and a brightness signal output circuit that outputs sampled brightness signals when the sample window circuit is operative.

Abstract: A moving image separating apparatus is disclosed. The apparatus is provided with a privacy image region detection unit and a moving image separating unit. The privacy image region detection unit detects privacy image region data indicating a position and a range of a privacy image region from the original moving image data. The moving image separating unit receives the original moving image data and the privacy image region data from the privacy image region detection unit. The moving image separating unit separates the original moving image data to private moving image data composed of image data corresponding to the privacy image region and to public moving image data composed of image data of a region excluding the privacy image region, on the basis of the privacy image region data.

Abstract: The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path.

Abstract: Movies are produced in 24 Hz frame frequency and progressive scanning format (denoted 24p) for projection in film theatres, adhering to a worldwide standard for 35 mm film. However, the major TV systems in the world use interlaced scanning and either 50 Hz field frequency (denoted 50i) or 60 Hz field frequency (denoted 60i). Content providers would prefer providing single-picture-frequency single-audio-speed AV discs that can be replayed in most parts of the world. According to the invention, For a 50 HZ output mode, in the media player either audio signal frames are dropped adaptively or video fields or frames are repeated adaptively, depending on the current video and audio content. Thereby the less perceptible stream controls the synchronisation.

Abstract: Program clock references in first and second MPEG data streams are re-stamped in accordance with delays introduced into the first and second MPEG data streams. Accordingly, the program clock references in the first MPEG data stream are re-stamped according to a variable delay in the first MPEG data stream, and the program clock references in the second MPEG data stream are re-stamped according to a variable delay in the second MPEG data stream. The re-stamped program clock references in the second MPEG data stream are corrected according to a fixed delay in the second MPEG data stream. The first and second MPEG data streams are multiplexed, and the multiplexed first and second MPEG data streams are transmitted and received.

Abstract: A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) may be received from a pre-stage video processing circuit (13). The first timing signal (S1) may be synchronous with a pre-stage system clock (C1) and may be set to the vicinity of a center of a screen by a video signal. A second timing signal (S2) may be generated on the basis of first timing signal (S1) and transferred to a post-stage video signal processing circuit (14). Second timing signal (S2) may be synchronous with a post-stage system clock (C2). In this way, a disturbance or distortion of a video on a screen due to a difference in system clock frequency affecting a video signal in the post-stage circuit may be reduced or eliminated.

Abstract: Disclosed is a video signal processing apparatus comprising a plurality of line memories to which in sequence input video signal data is written on a line-by-line basis; a timing controller for controlling a timing to write video signal data to the plurality of line memories and a timing to read video signal data from the plurality of line memories; a computation output portion for computing video signal data read from the plurality of line memories and outputting video signal data differing in resolution which is determined by a pixel count in the horizontal direction and a line count in the vertical direction; and a line controller which vary the pixel count in specified lines of video signal data obtained from the computation output portion, depending on a conversion rate of the video signal data resolution.

Abstract: A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCK—1 and CLOCK—2, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit (7) by an interface circuit (10). The progressive scan signal is clocked into a first register (20) on the second clock signal CLOCK—2, and is clocked to a second register (21) by the first clock signal CLOCK—1 and in turn to a third register (22) by the first clock signal CLOCK—1. The edge of the first clock signal CLOCK—1 on which the progressive scan signal is clocked into the second register (21) is chosen to allow sufficient time to clock the signal.

Abstract: A method and apparatus for retiming video. Vertical synchronization information (VSI) is detected in an incoming video stream. A VSI is also detected in both as output video stream and a reference video stream. Based on the difference between the VSI of the reference and output video stream reads or writes to a FIFO are suppressed until the VSI's are coincident.

Abstract: The present invention provides a device for signal transfer, which outputs a treatment signal relating to a vertical-horizontal composite sync signal of a monitor and an integrated signal of the vertical-horizontal composite sync signal. There is a plurality of logic circuits in the device of the present invention. The first logic circuit is provided for receiving the vertical-horizontal composite sync signal and the integrated signal, and outputs a high level signal when the voltage level of the vertical-horizontal composite sync signal transforms from the high level to the low level while the voltage level of the integrated signal is in the low level. The second logic circuit is connected to the first logic circuit and receives the vertical-horizontal composite sync signal and the signal outputted from the first logic circuit.

Abstract: A fly-back pulse width adjustment circuit and a method for adjusting the width of a fly-back pulse which are applied to a video signal processing unit realized as one chip are provided. The fly-back pulse width adjustment circuit is built into a video signal processing unit including a video amplifier, an on screen display unit, and a horizontal/vertical synchronous signal processing unit within the video signal processing unit realized as one chip.

Abstract: A color encoder is incorporated in an apparatus for reproducing a signal recorded on a disk for a video-CD, CD-G, or similar system. The color encoder serves as an interface between such an apparatus and a television receiver. The color encoder has a color-difference signal forming circuit for forming a color-difference signal from R, G, and B signals reproduced from a disk, a modulation circuit for modulating a chrominance subcarrier with the color-difference signal, and chrominance subcarrier generating device for generating the chrominance subcarrier. Moreover, to generate a chrominance signal having the same frequency for any of a plurality of clocks having different predetermined frequencies, the chrominance subcarrier generating device has a plurality of ROMs, each containing in its data area a data table corresponding to a different frequency, and a ROM switching circuit for selecting a ROM to be accessed from among the plurality of ROMs in accordance with a switching signal.

Abstract: Improved circuitry for adjusting the video gain, black level, chroma gain and burst phase of a video signal includes composite to Y/C splitter, luminance processing section, sync separator and chroma processor. Unity and split mode selection is provided. A meter circuit provides display of black and white levels as well as clip indication.

Abstract: A method of clock recovery from a fast packet switched asynchronous network wherein a time stamp is transmitted over a network that has variable delay, involves maintaining an input counter at a sending device. The counter has a value dependent on an input clock. The value of the input counter is periodically transmitted over the network to a receiving device. A local counter at a receiving device has a value dependent on a local clock. The received value sample x.sub.i is compared with the local sample y.sub.i to derive the difference e.sub.i. The local clock frequency f.sub.j is adjusted such that the average of Emin.sub.j, where Emin.sub.j is the minimum of a block of error samples e.sub.i, remains close to a predetermined value, preferably zero. The clock recovery method is particularly suitable for MPEG2 video transmitted over ATM.

Abstract: A receiver for receiving a cable and terrestrial digital signals of differing VSB modes where the data levels of the various signals have a desired relationship that enables simple data level slicing and error determination. Some of the signals have sync levels that do not conform to the desired relationship and the receiver includes a comb filter for reducing interference when receiving an 8VSB terrestrial signal. The mode of the received signal is determined and a correction factor is applied to the syncs of the signals as needed to reestablish the desired relationship. Operation of the comb filter results in additional levels and a disruption of the desired relationship. For such cases, the comb filtered data levels are modified to make them a subset of the VSB 16 data levels. The modifications are accomplished in feedback paths of the phase tracker after the circuit equalizer and do not affect the data levels passed to the next stage.

Abstract: A method and apparatus in a computer system for decoding and displaying video frames. An estimated number of intraframes which can be decoded in a current interframe run is determined. Based upon the estimated number of intraframes, determining an adjusted time interval in which to display each intraframe in the current interframe run. The intraframes are then displayed at the adjusted time interval in the current interframe run. The adjusted time interval may include equal time periods for displaying the estimated number of intraframes within the current interframe run. Discontinuities in display of moving video sequences can be avoided.

Abstract: A sync signal correction circuit generates a corrected sync signal which is obtained by correcting a timing of a sync signal on the basis of a time axis variation component (jitter component) of the sync signal separated from a picture signal. The corrected sync signal is used as the sync signal to cause a variation of time axis error of the picture signal to follow a variation of time axis error of an output signal of an automatic frequency control (AFC) circuit which constitutes a monitor device for reproducing and displaying the picture signal, such that the variation of time axis error of the output signal of the AFC circuit and the variation of time axis error of the picture signal of the reproduced picture signal are cancelled each other to prevent jittere from appearing on a display screen.

Abstract: A video/graphics overlay circuit receives an analog input composite video signal and a digital input composite video signal and combines them into a linear combination output composite video signal depending on the state of one or more mixer control signals. The two composite video input signals are each capacitively coupled to buffer and clamp circuits through which the blank or DC level of each signal is clamped to two volts. The outputs of the buffer and clamp circuits are then fed to a mixer circuit and burst separator circuits. The mixer circuit generates the output composite video signal which is a linear combination of the input composite video signals as controlled by the one or more mixer control signals. The burst separator circuits separate the burst signal from the input composite video signals. The extracted burst signals are then provided to a burst signal phase-locked loop for locking the burst signals of the input composite video signals in phase.

Abstract: A video/graphics overlay circuit receives an analog input composite video signal and a digital input composite video signal and combines them into a linear combination output composite video signal depending on the state of one or more mixer control signals. The two composite video input signals are each capacitively coupled to buffer and clamp circuits through which the blank or DC level of each signal is clamped to two volts. The outputs of the buffer and clamp circuits are then fed to a mixer circuit and burst separator circuits. The mixer circuit generates the output composite video signal which is a linear combination of the input composite video signals as controlled by the one or more mixer control signals. The burst separator circuits separate the burst signal from the input composite video signals. The extracted burst signals are then provided to a burst signal phase-locked loop for locking the burst signals of the input composite video signals in phase.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronisation signal component, the synchronisation signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: A digital recording/reproducing apparatus having an external input digital interface is disclosed. A changeover switch is controlled by a changeover control circuit for selecting horizontal synchronizing signals generated by horizontal synchronizing generator for an external input mode and for selecting horizontal synchronizing signals derived from reproduced video signals reproduced from a recording medium for a playback mode. Standard color sub-carrier signals may be generated by a color sub-carrier signal generator based on the horizontal synchronizing signals as selected by the changeover switch. Even when the digital video signals supplied from outside for the external mode include non-standard horizontal synchronizing signals, standard composite video signals may be generated by an encoder by employing the color sub-carrier signals from the color sub-carrier signal generator.

Abstract: The present invention relates to a method of aligning and blending input digital samples, comprised of delaying the input samples by a clock pulse, to provide delayed data samples, subtracting a smaller fractional part from a larger fractional part of either an input sample number and a requested sample number to provide a sample difference number first factor, subtracting the sample difference number from 1 to provide a second factor, multiplying either of the input samples or the delayed samples by the first factor to provide a first result, multiplying the other of the input samples or the delayed samples by the second factor to provide a second result, and adding the results to provide output samples.