Abstract: The disclosure discloses methods and devices for transmitting and rendering a 3D scene.

Abstract: A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

Abstract: An embodiment of the present invention is an imaging system in which a camera unit and a control unit are connected by a video signal transmission line and a clock line, and the camera unit and the control unit operate in synchronization with each other by a horizontal synchronization signal and a vertical synchronization signal indicating reading timing of the video signal. The camera unit includes a signal analysis circuit configured to encode information superimposed on a master clock, and encode a register control signal superimposed on the master clock using a camera clock based on timing of the horizontal synchronization signal or the vertical synchronization signal, and write an imaging condition indicated by the register control signal to a register.

Abstract: A method includes: obtaining a first frame synchronization signal, period between a trailing edge of a first pulse and a leading edge of a next first pulse being first time period corresponding to a first integer number of pulses of a first pixel clock signal; generating a synchronization calibration signal, a triggering edge of the second pulse being delayed compared to a trailing edge of a first pulse; generating a second frame synchronization signal, period between a triggering edge of the second pulse and a leading edge of a third pulse being second time period. When ratio of frequency of the second pixel clock signal to frequency of the first pixel clock signal is within threshold range, the second time period corresponds to a second integer number of pulses of the second pixel clock signal. The second integer is integer value of product of the first integer and ratio.

Abstract: A video timing conversion method and a video timing conversion device, and a non-transitory computer-readable storage medium are provided. The video timing conversion method includes: analyzing an original timing signal in a form of a differential signal of an original video, to obtain original timing parameters; determining target timing parameters and a target clock signal parameter according to a format of a target video and the original timing parameters; wherein the target timing parameters include a data enabling period number, a field sync data valid row number and a refreshing frequency, which are the same as the data enabling period number, the field sync data valid row number and the refreshing frequency of the original timing parameters, respectively; generating a target timing signal in the form of the differential signal of the target video according to the target timing parameters and the target clock signal parameter.

Abstract: A signal processing method includes: obtaining a first frame synchronization signal including a plurality of first pulses, a period between a trailing edge of a first pulse and a leading edge of a next first pulse being a first time period, which corresponding to a first integer number of pulses of a first pixel clock signal; generating a synchronization calibration signal including a plurality of second pulses, a trigger edge of each second pulse being at a same time as the trailing edge of the first pulse; and generating a second frame synchronization signal including a plurality of third pulses, a period between the trigger edge of each second pulse and a leading edge of a third pulse closest to the second pulse after the second pulse being a second time period, which corresponding to a first integer number of pulses of the second pixel clock signal.

Abstract: According to an aspect of the disclosure, an information processing apparatus comprising a communication circuit and a control circuit is provided. The control circuit transmits reduced image data of captured image data, to a first external apparatus through the communication circuit; receives, from the first external apparatus, a result of evaluation processing applied to the reduced image data; on the basis of the result of the evaluation processing, determines whether to apply image processing to the captured image data corresponding to the reduced image data, by a second external apparatus; transmits the captured image data that is determined to be applied the image processing, to the second external apparatus through the communication circuit; and receives, from the second external apparatus, a result of the image processing applied to the captured image data.

Abstract: The present disclosure relates to a content distribution system and a content distribution method capable of improving a user experience of a user who views content. A distribution server distributes content in which a plurality of high-definition partial images and a low-resolution entire image including those partial images as regions are hierarchically configured. Then, a mobile display device displays the entire image and displays the partial image in a selectable manner on the entire image, and operation of selecting a predetermined partial image is performed. On the other hand, a large screen display device displays the partial images distributed from the distribution server in high definition according to operation on the mobile display device.

Abstract: A method and a device are used to generate a control command. A resolution base value and a resolution-tick corresponding function are created. A first operation frequency value, a minimal tick value and a resolution value are received to calculate a resolution ratio and a second operation frequency. A conversional tick value is calculated. If or not the conversional tick value is greater than or equal to the minimal tick value is determined. If the conversion tick value is smaller than the minimal tick value, the minimal tick value, the conversional tick value and the second operation frequency are used to calculate a conversional operation frequency. A conversional resolution ratio is calculated according to the first operation frequency and the conversional operation frequency, and also a modified tick value is calculated. The control command is output according to the modified tick value, the first operation frequency and the conversion operation frequency.

Abstract: A timing controller may reduce power consumption and/or reduce influence on wireless communication. A line memory is capable of retaining at least pixel data of one line. An input interface circuit is used for receiving pixel data and storing the pixel data in the line memory. A frequency synthesizer is used for receiving the external pixel clock CKP received by the input interface circuit and generating an internal pixel clock CKINT having frequency being a coefficient K multiplied by frequency of the external pixel clock CKP. An image processing circuit is used for processing the pixel data stored in the line memory synchronously with the internal pixel clock CKINT.

Abstract: The present technology relates to a reception apparatus and a data processing method that permit efficient processing of time information. The reception apparatus receives a digital broadcasting signal based on an IP transport scheme, acquires time information from a physical layer frame transported in a physical layer of a protocol stack for the IP transport scheme, converts the acquired time information into the same data format as data provided in a payload of the physical layer frame, and outputs the converted time information to a processing section that performs a given process relating to an upper layer that is a layer higher than the physical layer. The present technology is applicable, for example, to a television receiver that supports an IP transport scheme.

Abstract: Techniques pertaining to thermal management for smooth variation in display frame rate are described. A method may involve performing either or both of: (1) determining whether a temperature of at least one portion of an electronic apparatus exceeds a temperature threshold; and (2) determining whether a variation in a frame rate of images displayed on a display device associated with the electronic apparatus exceeds a variation threshold. The method may also involve controlling the frame rate in response to either or both of a first determination that the monitored temperature exceeds the temperature threshold and a second determination that the variation in the frame rate exceeds the variation threshold.

Abstract: An imaging device includes: first and second image sensors; a first communication controller configured to be connected to the first image sensor; a first clock generator that generates a first clock signal that is a reference for operation of the first communication controller; a second communication controller configured to be connected to the second image sensor; a second clock generator that generates a second clock signal that is a reference for operation of the second communication controller; a reference synchronization signal generator that generates a reference synchronization signal; and an imaging synchronization signal generator that generates an imaging synchronization signal which is a trigger for determining timings of imaging by the first and second image sensors, and outputs the imaging synchronization signal to the first and second communication controllers at a timing when a predetermined period of time has elapsed from a reference timing based on the reference synchronization signal.

Abstract: A system and process is provided in which original video or dialog content is securely received from the content owner. Subtitle language data is derived, translated, stored and served on a separate database for synchronous playback with the content in video streaming, downloading or online TV following the activation of an option by the end user through a media player.

Abstract: Methods and apparatus for processing and displaying caption information associated with a video program are provided. The caption information is extracted from a video signal and different captions are rendered in sequence for different segments of the video program. A plurality of the different captions is blended in a form for simultaneous display superimposed on video images during one of the different segments of the video program. The different captions may be the latest caption corresponding to the current segment of video and a previous caption corresponding to a previous video segment. These different captions can be displayed such that they overlie each other and such that their opacity is different. In this manner, a viewer is able to have a prolonged period of time to read captions and can readily distinguish the current caption from the previous caption.

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: Provided are a method of receiving an enhanced service and a video display device thereof. The method includes: receiving an audio-visual (AV) content; extracting first feature information from the received AV content; receiving a database including at least one of content information, enhanced service information, and an enhanced service, which correspond to the first feature information, from a first server by transmitting the extracted first feature information to the first server; storing the database received from the first server in a memory; extracting second feature information from the received AV content; and searching and obtaining one of content information, enhanced service information, and an enhanced service, which correspond to the extracted feature information, from the database.

Abstract: [Problem] In order to eliminate timing offset between reproduction devices when a content transmitted from a distribution device is received and reproduced by a plurality of reproduction devices, data (SCR) indicating the elapsed time from the start of the content, generated by counting clock pulses, and data (FCR) indicating a frame number generated by counting the number of frames reproduced by a decoder (54) are transmitted by the distribution device, and a clock generation unit (103) in each reproduction device is controlled so that data (STC) indicating the elapsed time and data (FTC) indicating the frame number, which are generated in the same manner by each reproduction device, match the transmitted data (SCR, FCR). Synchronization between reproduction devices can thereby be established even when, in a state in which a content is being reproduced by one reproduction device, another reproduction device subsequently connects to the distribution device.

Abstract: There is provided a driving apparatus which includes an acquisition section which acquires a parameter for driving an imaging element, which receives an optical image from a subject and outputs an imaging image as an electric signal, in an action mode which is desired by a user; a timing generation section which generates respective timings of the starting of each of a plurality of horizontal synchronization periods, where horizontal synchronization periods which are only different in terms of the number of clocks determined in advance are acquired in a mixed state, based on the parameter; and a driving control section which receives the optical image from the subject for each line which configures the imaging element by synchronizing the respective timings which are generated using the timing generation section.

Abstract: According to one embodiment of the present invention, a timing controller for a display, includes a first unit, a second unit and a third unit. The first unit is configured to generate an image signal from a first input signal. The second unit is configured to generate a multitude of timing signals and a control signal from a multitude of second input signals, the control signal being generated after the multitude of timing signals are generated. The third unit is configured to generate a multitude of first signals from the multitude of timing signals after receipt of the control signal from the second unit. The image signal and the multitude of first signals are configured to drive the display when the timing controller is connected to the display.

Abstract: Adapter (3, 5) for processing electrical signals in an installation comprising a video camera equipment (1) and a remote equipment (7). A first aim of the present invention is to provide an adapter system which allows automatically providing an output video signal that is co-timed to the master timing reference of the remote equipment. A second aim of the invention is to provide an adapter system which improves the security of the installation when power for the camera is transmitted by the remote equipment.

Abstract: A voltage level control circuit controls a target slicing voltage level to slice a video signal by a target circuit. The voltage level control circuit includes a slicing circuit for sequentially slicing the video signal by a plurality of slicing voltage levels to correspondingly generate a plurality of first clock signals; a detection circuit for respectively detecting a plurality of phase differences between the first clock signals and a plurality of corresponding second clock signals to generate a plurality of detection signals; an oscillating circuit for generating the second clock signals according to the detection signals, respectively; and an adjusting circuit for determining whether to adjust the target slicing voltage level according to the detection signals corresponding to the slicing voltage levels.

Abstract: Audio data and video data are processed to determine one or more audible events and visual events, respectively. Contemporaneous presentation of the video data with audio data may be synchronized based at least in part on the audible events and the visual events. Audio processing functions, such as filtering, may be initiated for audio data based at least in part on the visual events.

Abstract: A measuring device for measuring a response speed of a display panel is provided. The measuring device includes a microcontroller and at least one photo sensor. The microcontroller provides a control command, according to which a display controller of the display panel provides test pattern to the display panel. The photo sensor senses a test frame displayed corresponding to the test pattern by the display panel, and provides a corresponding sensing signal associated with brightness and a response signal. According to the response signal, the response speed of the display panel is calculated.

Abstract: To provide a time synchronization information computation device capable of synchronizing the times of a plurality of cameras without the need of a special device, a time synchronization information computation method and a time synchronization information computation program. There are provided a plurality of video acquisition means 100-1 to 100-N for acquiring videos, a plurality of visual event detection means 101-1 to 101-N provided corresponding to the plurality of video acquisition means for analyzing the videos acquired by the plurality of video acquisition means 100-1 to 100-N to detect visual events, and generating visual event detection information including time information on when the visual events occur, and visual event integration means 102 for integrating the visual event detection information generated by the plurality of visual event detection means 101-1 to 101-N and synchronizing the times of the videos acquired by the plurality of video acquisition means 100-1 to 100-N.

Abstract: Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.

Abstract: A signal transmission apparatus includes: a vertical rectangular region sampling-out control section that obtains vertical rectangular regions, repeatedly performs a process where pixel samples read out from each line of class images are mapped to each line of video data regions of sub-images, maps pixel samples to each line of the video data regions, and repeatedly maps pixel samples to the next line; a line sampling-out control section that samples out the pixel samples every other line from each line of the sub-images to which the pixel samples have been mapped, so as to generate an interlace signal; a word sampling-out control section that samples out for each word the pixel samples which have been sampled out for each line so as to be mapped to video data regions of an HD-SDI prescribed by the SMPTE 435-2; and a readout control section that outputs the HD-SDI.

Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.

Abstract: According to one embodiment, an electronic device includes a reproduction controller and a transmitter. The reproduction controller is configured to reproduce a first type of information of a first content. The first content includes a plurality of types of information. The transmitter is configured to transmit an instruction to reproduce a second type of information of the first content to other electronic device.

Abstract: A method for transmitting service data of a handset TV is disclosed in the present invention, wherein, an audio part and a video part of a handset TV program are split into an audio sub-service and a video sub-service respectively, and when transmitting the service data of the handset TV program, a transmitting terminal splits the service data into audio sub-service data and video sub-service data; the transmitting terminal respectively transmits the audio sub-service data and the video sub-service data on different transmission resources, and transmits association relationship information of the audio sub-service and the video sub-service to a terminal.

Abstract: A mechanism for facilitating dynamic timestamp-less clock generation for transmitting media streams over shared channels is described. In one embodiment, a method includes periodically counting and producing, at a first media device, a number of audio/video (“A/V”) samples, generating a pace clock based on the number of A/V samples, generating a target clock based on the pace clock, and transmitting an A/V media stream based on a frequency difference between a pace frequency relating to the pace clock and a target frequency relating to the target clock.

Abstract: A method for de-interlacing interlaced video includes receiving a first video field and a second video field of an interlaced video frame, generating a first video frame from the first video field and a first synthesized video field, where video data of the first synthesized video field is based exclusively on video data of the first and second video fields, generating a second video frame from the second video field and a second synthesized video field, where video data of the second synthesized video field is based exclusively on the video data of the first and second video fields, and outputting two de-interlaced video frames for every received interlaced video frame. The first (second) synthesized video field is generated by combining image data from the second (first) video field with image data from corresponding lines of an up-scaled first (second) field generated by a scaler.

Abstract: The invention concerns a device for transmitting packets in a packet communication network comprising at least two stations, characterized in that it includes means for: extract image cues from a synchronizing signal, initializing a first counter based on said image cues, initializing a second counter every “m” zero crossing of the first counter, sampling the second counter at all the Tech periods, where Tech is derived from a time base synchronized on all the network stations, and transmitting packets containing the samples in the network. The invention also concerns a device for receiving packets in a packet communication network comprising at least two stations.

Abstract: Disclosed herein is a camera system including, a camera apparatus having, an image sensor, a correction section, a first transmission processing section, and a synchronization processing section, and a video processing apparatus having a second transmission processing section and a conversion section, wherein the video processing apparatus outputs the video data obtained by the conversion by the conversion section.

Abstract: There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.

Abstract: Stereographic glasses includes reception-stop timing control means that is so arranged as to: (i) cause a wireless-signal receiving section to stop receiving signals, after a cycle detection section detects a cycle of synchronous signals and a liquid crystal shutter control data memory section stores liquid crystal shutter control data therein signals; (ii) cause a liquid crystal shutter control signal timing generation section to generate timings for controlling opening and closing of liquid crystal shutters, based on cycle signals generated by a cycle signal generation section and the liquid crystal shutter control data stored in the liquid crystal shutter control data memory section; and (iii) cause a liquid crystal shutter control section to open and close the liquid crystal shutters, at the timings thus generated.

Abstract: A method for de-interlacing interlaced video includes receiving a first video field and a second video field, generating a first video frame by inserting the first video field in the first video frame on every second line of the first video frame, and by inserting a first synthesized video field on the lines of the first video frame not populated by the first video field. The video data of the first synthesized video field is based on video data of the first and second video fields. A second video frame is generated by inserting the second video field in the first video frame on every second line of the second video frame and by inserting a second synthesized video field on the lines of the second video frame not populated by the second video field. Two de-interlaced video frames are output for every received interlaced video frame.

Abstract: In one embodiment, an interface may include various mechanisms to handle incoming clock and data signals. More specifically, the interface includes a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin and a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin. In addition, the interface may include a decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin.

Abstract: Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.

Abstract: An image display device including a receiving section acquiring a synchronizing signal superimposed on a digital signal, an image generating section outputting image data based on a digital signal, a control section controlling the image generating section, an adjusting section making an adjustment to the digital signal based on setting information, and an information inputting section to which a display instruction to display a setting image for assisting the change of the setting information is input, wherein the image generating section generates a second synchronizing signal different from the first synchronizing signal, and the control section controls the image generating section.

Abstract: A method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period in the television signal between two successive video display fields; generating a synchronization signal indicative of the detected inactive video period; and in response to the synchronization signal, performing measurement and adjustment operations on analog circuitry of the television receiver. In another embodiment, a method in a television receiver receiving interlaced analog modulated television signals includes: detecting an inactive video period between two successive video display fields using a not-fully-demodulated intermediate frequency (IF) signal; and generating a synchronization signal indicative of the detected inactive video period.

Abstract: A method and system for boosting a clock frequency for a processor in a mobile device based on user interface (UI) demand are described. In response to a user interaction through a UI in the mobile device, a vertical synchronization pulse request is made by an application and an indication of such request can be provided to a governor. The governor can adjust a clock frequency of a processor in the mobile device based on the generated indication. The processor can be a central processing unit or a graphics processing unit. The clock frequency can be boosted to a higher frequency to increase the processing capabilities of the mobile device to handle the computational requirements of the user interaction. Some time after boosting the clock frequency of the processor, the governor can return to normal operations in which the clock frequency scaling is typically based on a measured system load.

Abstract: A method and apparatus for improving a channel change response time are disclosed. A meta channel associated with an original and auxiliary media streams is generated. The information conveyed by the meta channel is propagated toward at least one user device. The user device may receive the meta channel information and select one of the media streams using the meta channel information in response to a channel change request from a user terminal, or a network device may select one of the media streams for a user terminal in response to a channel change request from the user terminal.

Abstract: A display device is provided, which includes a first communication interface which receives a partial amount of contents of a plurality of contents which partial amount of contents have been synchronized with each other from a content receiving device, a second communication interface which receives a remaining amount of contents of the plurality of contents from a first communication network that is different from a second communication network from which the content receiving device receives the partial amount of contents, a signal processor which performs signal processing such that the partial amount of contents received via the first communication interface and the remaining amount of contents received via the second communication interface are displayable in synchronization with each other, and an output device which displays the plurality of signal-processed content.

Abstract: A method for converting a sink device and an apparatus for providing a content using the same are provided. The method for converting the sink device includes receiving a sink device conversion command from a first sink device, transmitting the content to a second sink device if a conversion approval of the sink device is received from the second sink device, and transmitting a control authority related to a content provision from the first sink device to the second sink device.

Abstract: The present invention provides a system and method for automatically controlling the phase of the clock signal for sampling an HDTV signal, which implements a new and improved method for phase detection. The system and method utilize the standard format of an HDTV signal to consistently ensure accurate phase detection. Particularly, the system and method detect the target phase for the sampling clock using a tri-level sync pattern that exists at the beginning of each display line. This tri-level sync pattern or “sync pulse” is well suited for phase detection since it includes several static areas separated by substantial transitions. Furthermore, by using the sync pulse of the HDTV signal, the system and method provide consistent and accurate results, since the sync pulse will not change regardless of the whether the video data is static or in motion.

Abstract: Provided is an OFDM receiver which extracts a time sync signal from a prefix having a symmetric structure. The OFDM receiver, according to exemplary embodiments of the present invention, generates the sync signal (e.g., start point) of a symbol by using only the MSB (e.g., sign bit) of the cyclic prefix of an OFDM symbol, reducing the overhead of a logic circuit for generating the sync signal of the symbol.

Abstract: An embodiment of the present invention discloses a method for quickly responding to a signal, where the method includes: generating a frame synchronization signal; pre-reading image data, and saving the image data after processing the image data; and receiving a TE signal, and outputting the processed image data according to the TE signal. An embodiment of the present invention further discloses an apparatus for quickly responding to a signal. Using the present invention may improve a rate for responding to a signal and reduce an instantaneous bandwidth pressure on a transmission line.

Abstract: A horizontal synchronization signal detection system includes a coarse period estimator and a fine period time estimator. The coarse period estimator estimates a minimum value and corresponding position of each period of a CVBS signal to calculate a coarse period of a horizontal synchronization signal. The fine period time estimator divides the horizontal synchronization signal into a first part and a second part so as to generate a first sum and a second sum by adding signals of the first part and the second part, and detects a middle point of the horizontal synchronization signal when the first sum equals the second sum. The steps of fine-tuning the coarse period to generate a fine-tuned coarse period, extracting the horizontal synchronization signal according to the fine-tuned coarse period, and determining whether the first sum is equal to the second sum are repeatedly executed until the first sum equals the second sum.