Abstract: A clamp pulse generating circuit comprising a synchronizing decision circuit for deciding whether an external synchronizing pulse is being input or not; an exclusive-OR circuit, a change-over switch and a pulse width detecting circuit for deciding whether a video signal containing a synchronizing pulse is being input or not; and a pulse generating circuit for generating a clamp pulse at the front or rear edge of the external synchronizing pulse output from a synchronizing separator circuit, and outputting the clamp pulse at the front edge selected by a selection switch when the external synchronizing pulse is being input and forcing to select and output the clamp pulse at the rear edge of the synchronizing pulse irrespective of the presence of the external synchronizing pulse when the video signal containing the synchronizing pulse is being input.

Abstract: An analog to digital converter circuit having sync control is constructed to monitor the sync condition of the digital output. When sync is lost, for example due to a low input signal level or due to an out of phase situation, the gain of the output increased to relatively high level so as to enhance the possibility of detecting the sync condition. As soon as sync is reestablished the gain is immediately turned down to a level lower than the blanking level and then gradually increased to the blanking level. The gain levels at startup and during the sync reestablishment intervals are fixed but under selective control.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronization signal component, the synchronization signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: A controller for synchronising video signals for displaying on TV screen.

Abstract: A synchronization detection circuit quickly detects resynchronization to a new input signal quickly when the input signal changes, etc. A frame synchronization detection circuit 3 synchronizes the frame pattern contained in, for example, the MUSE signal, etc., and a frame synchronizing signal (signal (IFP1)) formed in the MUSE decoder, pattern detection circuits 30, an integrating circuit 32, and a slicing circuit 36 function in concert to detect and output the frame pattern to a phase comparator 36 as a signal (SS).

Abstract: A system for generating a video control signal to process a video signal associated with a video composite signal. The video composite signal has horizontal and vertical driving signal, each having one or more pulses. The system comprises a counter for counting the number of the pulses of respective one or more of the horizontal and vertical driving signals, and a flip-flop, which is coupled to the counter, for generating a blanking signal based on the result of the counting.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronization signal component, the synchronization signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: The present invention relates to a device which generates a vertical synchronizing signal of video signals according to digital methods.

Abstract: A television receiver providing a stable image whether or not a composite color signal is present, in which a transmitter-recognition processes the television synchronization signals of the composite color signal. A character generator displays alphanumeric as well as graphic characters. The deflection generators and the character generator are operative with TV signals as well as characters that are alphanumeric as well as graphic. The deflection generators and the character generator are driven by control signals. An oscillator controls the deflection generators, and a phase comparator operates in the presence of synchronization signals to synchronize the oscillator. The phase comparator receives no signals from the input terminal when no synchronization signals are present, so that the oscillator oscillates at a fixed preadjustable frequency to provide a stable image.

Abstract: An electronic stereoscope displays field-sequential stereoscopic images on a display screen at a predetermined field rate. The images are viewed through left and right electro-optical shutters driven out of phase with each other and synchronously with the field rate. Left and right lenses are also provided in correspondence with the left and right shutters to accommodate and converge the user's eyes on the display screen.

Abstract: This invention is a method and apparatus for identifying and separating the synchronizing signal component of video like signals by identifying or detecting the arrangement or sequence of the known occurances of events or patterns of the sync. The invention also provides for establishing data slicing references in response to the levels of known portions of the sync component.

Abstract: A method for the conversion of conventional interlaced video display synchronization signals to those required for a field sequential color display interlaced video synchronization signals comprises the steps of receiving the conventional horizontal and vertical synchronization signals; multiplying the repetition rates of these signals by a factor that is number of component colors that comprise the colors of the video display; selecting time segments of the multiplied horizontal synchronization signals; phase shifting these selected time segments to align with the multiplied vertical synchronization signal; merging the phase shifted and the non-phase shifted time segments of the multiplied horizontal synchronization signal to form the field sequential color display horizontal synchronization signal; and amplifying and buffering the multiplied vertical synchronization signal and the field sequential color display horizontal synchronization signal to act as input to the deflection circuitry of a field is seque

Abstract: The present invention relates to a synchronizing signal generation circuit equipped with a PLL circuit. A pulse signal having a time constant that is broader than the clock width of a horizontal synchronizing signal included within synchronizing signals and that moreover contains steady-state phase error of the PLL circuit is generated and inputted to a phase comparison inhibiting circuit by way of a signal conversion circuit. The logic level of the pulse signal is then varied for the active interval and the inactive interval of the vertical synchronizing signal, phase comparison of the horizontal synchronizing signal and the reproduced horizontal synchronizing signal being inhibited during the active interval. The reproduced horizontal synchronizing signal is generated based on the output of two frequency dividers.

Abstract: To interface a video/graphic controller, which produces conventional, ana video output signals, suitable mostly for CRT type displays, to a matrix display, one of the video output signals, for example the horizontal sync signal, is encoded with the clock frequency and phase information used in generating the original video output signals. The encoded information is decoded at the display end, by extracting from it the clock information and synthesizing a clock signal which has the identical frequency and phase as the original clock used at the video/graphic controller. The replicated clock signal is used as a clock input to the matrix display, to assure that the video output signals are displayed at the correct pixel locations of the matrix display, preventing picture jitter and/or loss of video/graphics data.

Abstract: A monolithically integratable display apparatus for receiving a picture signal having frames of video information and horizontal and vertical synchronizing components includes a matrix of display cells arranged in an array of M rows by N columns. Display cells in the matrix are individually addressable by row and column signals so as to receive the video information in the picture signal in response thereto. A first shift circuit coupled to the matrix provides the row signals in response to a first clocking signal and a data signal. A second shift circuit coupled to the matrix provides the column signals in response to a second clocking signal. A first clock circuit, such as a phase locked loop, receives the horizontal synchronizing component of the picture signal and produces the second clocking signal in response thereto. A synchronizing detector circuit receives the vertical synchronizing component of the picture signal and produces the data signal in response thereto.

Abstract: A video system pulse generating circuit has the frequency of the video system pulse being an integral multiple of a video synchronizing signal, and being synchronized with video synchronizing signal. The video system pulse generating circuit includes a phase locked loop circuit, a dividing circuit, and a synchronizing range determining circuit, wherein an asynchronous oscillator such as a quartz oscillator is not required.

Abstract: A programmable CPU running at a video display rate, or a sub-multiple thereof, is used to generate the timings by loading control registers on the fly. In a preferred embodiment, a very reduced instruction set is used to generate VSYNC, HSYNC, and CSYNC signals. The CPU executes instructions out of an Instruction SRAM. The CPU's main goal is to load a pair of backing registers before a down counter reaches the value of zero.

Abstract: A deflection waveform correction signal generator comprises a multiplying circuit for generating a pincushion correction signal. A horizontal frequency ramp is generated by a clipped retrace pulse. The ramp generator has an output coupled to an integrating circuit for generating a parabolic shaped signal. The ramp generator and ramp integrator are reset at a horizontal rate by reset pulses of differing duration. The different duration of reset pulses results in the parabolic signal having regions of non-parabolic shape. The parabolic shaped signal is coupled to an input of the multiplying circuit. A control circuit is coupled to the parabolic shaped signal for maintaining a peak amplitude thereof by controllable coupling to the ramp generator. A control loop is coupled to the integrator for controlling an integrator input bias current to generate the parabolic shaped signal at a predetermined time interval.

Abstract: An integrated circuit device for processing an image signal has an inexpensive structure and an excellent signal processing characteristic. The integrated circuit device (3) formed on one integrated circuit substrate comprises a switch circuit (4), a separator circuit (8) and preamp circuits (5) to (7). The separator circuit (8) has an input terminal which has an input impedance which is sufficiently higher than an output impedance of the switch circuit (4). Receiving an output of the switch circuit (4) at such an input terminal, the separator circuit (8) filters off high-frequency components including the maximum frequency of the image signal and outputs signal components which belong to a frequency band which is related to a synchronization signal. The preamp circuits (5) to (7) amplify and output image signals which are outputted by the switch circuit (4).

Abstract: A first clamp circuit clamps a tip of a synchronization signal of input video signal in accordance with a synchronization signal generated from a synchronization signal generator and outputs a clamped video signal. A level detector detects a level of a tip of a synchronization signal of the clamped video signal. A converter converts the detected level to a reference level signal so that the greater the detected level becomes, the smaller the reference level signal becomes. A second clamp circuit clamps the tip of the synchronization signal of the clamped video signal to the reference level signal and outputs an output video signal. Thus, the second clamp circuit compensates a remaining sag component included in the input video signal accurately.

Abstract: A multiplex frame format for transmitting digital data in a data transmission system comprises a PACKETS portion comprising a highly error-protected region and a region having only Reed Solomon encoding as an error protection measure, the PACKETS portion including low speed data. The frame format also comprises portions for transmitting medium (AUDIO) and high speed (VIDEO) data streams following the PACKETS portion. Prior to transmission, the composed frame comprising the PACKETS, AUDIO and VIDEO portions is interleaved and the BLOCK SYNC and FRAME SYNC are added. A multiplex structure control packet word of the PACKETS portion immediately follows FRAME SYNC. Thus, the FRAME SYNC word defines where interleaving begins. A demultiplexer in concert with a microcontroller of a decoder decodes the multiplex structure control word and related PACKETS and outputs digital data streams to related output peripheral processors.

Abstract: A timing logic system which includes a generic television-standard timing generator selectably provides precisely timed horizontal and vertical control signals for controlling the operation of a high resolution charge coupled device (CCD) image sensor of the type having two line pixel registers in a high resolution mode of picture imaging. Alternatively, the timing logic system selectably provides precisely timed horizontal and vertical control signals, and a precisely timed display field control signal applied to a switch mechanism, for controlling the operation of the high resolution CCD image sensor in a television resolution mode of picture imaging in accordance with a television standard, for example, the NTSC standard. The timing logic system also provides sync and control signals to a television-standard display in the television mode of operation.

Abstract: A free running frequency alignment method in a video display having a sync generator comprising a first oscillator having a first frequency and a second oscillator having a second frequency. The first oscillator is phase modulated by the second oscillator which has a free running frequency different from a standard frequency. The free running frequency of the first oscillator is to be controllably aligned to the standard frequency by a method comprising the steps of applying a frequency determining initial control value to the first oscillator and measuring an average free running frequency responsive to the initial control value. An absolute difference frequency is calculated between the average frequency and the standard frequency. The absolute difference frequency is tested for a frequency value less than a predetermined value which signifies an aligned condition. If the difference frequency is less than the predetermined value the alignment is complete.

Abstract: The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.

Abstract: The invention inputs a single timing clock. Through procedure of mode setting, the invention generates the required timings corresponding to the display mode selected. In the invention, a programmable mode register, a mode decoder, a pixel timing generator, a horizontal timing generator, a vertical timing generator, a composite timing generator, AND gate, EXCLUSIVE NOR gate, and a selector are provided. The invention may generate the required timings for NTSC interlace mode, NTSC non-interlace mode, PAL interlace mode, PAL non-interlace mode, VGA 60 Hz progressive mode and VGA 50 Hz progressive mode.

Abstract: A video display has microcomputer control via a data bus and comprises a first sync generator coupled to the data bus for control by data thereon. A second sync generator is without controllable coupling to the data bus. A deflection amplifier is coupled to a deflection coil for generating a deflection current therein. A circuit for controlling the second sync generator is coupled to the first sync generator and is responsive to a digitally controlled signal therefrom. The second generator output signal is coupled to the deflection amplifier for deflection generation responsive to the digitally controlled signal.

Abstract: A horizontal line counter (110,115,120) provides a signal (LINE #21) identifying the beginning of video data in a particular horizontal video line. The counter is clocked by multiple clock signals. A first clock signal (HOR PLS) clocks the counter until the line count value equals a known value that is less than the line number of the horizontal line that is to be identified. When the count value equals the known value, clocking by a second clock signal (COMP SYNC) is enabled. Although, the first clock source provides a regular pulse waveform suitable for clocking the counter reliably, transitions on the first clock signal may not accurately indicate the beginning of information within a horizontal line interval. Transitions on the second clock signal accurately indicate the beginning of the desired information.

Abstract: A synchronizing signal regenerating circuit for standard video signals in a digital video signal processing system includes a circuit for regenerating stable horizontal synchronizing signals, a circuit for generating double horizontal synchronizing signals, a circuit for generating horizontal synchronizing signals, a circuit for generating vertical synchronizing signals and an output circuit. The circuit for regenerating stable horizontal synchronizing signals regenerates the horizontal synchronizing signals in response to quadruple burst signals, and the circuit for generating double horizontal synchronizing signals is connected to the output terminal of the circuit for regenerating stable horizontal synchronizing signals. The circuit for generating horizontal synchronizing signals is connected to an output terminal of the circuit for regenerating stable horizontal synchronizing signals.

Abstract: A digital multivalue synchronizing signal generating circuit generates three-value synchronizing signals for one frame using an address counter operating by a clock frequency which is more than 50 times the horizontal frequency and a ROM, and the three-value synchronizing signals are limited in band by a digital filter operating by the sampling clock of the digital video signal, and a digital multivalue synchronizing signal is generated. The video signal processing apparatus possessing a digital multivalue synchronizing signal generating circuit combines the digital video signal and digital multivalue synchronizing signal digitally, and produces a video signal having a digital synchronizing signal, and by D/A conversion thereof, a video signal having a analog synchronizing signal without waveform deterioration in the synchronizing signal portion is obtained.

Abstract: Apparatus and method are provided which receive and sample an incoming video image signal asynchronously, and then processes the signal to recover the video image, including video format, for conversion into a preselected video format. The apparatus and methods first sample the video signal using a stable (crystal oscillator) time base clock to reconstruct the frequency of the video signal, i.e., to recover the video format and then using a contrast optimization process to determine the video signal pixel clock rate.

Abstract: Apparatus and method for controlling a charge coupled device (CCD) image sensor provides, in accordance with a television standard, horizontal and vertical CCD control signals to obtain a purely sequential mode of operation on the one hand, and alternatively a modified mode of operation to permit image signals to be viewed directly on a standard viewfinder display. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to selectably generate the vertical and horizontal CCD control signals for the alternate modes of operation. The method includes generating a plurality of precisely timed pulses referenced to television standard synchronizing and control signals, and logically combining these pulses and standard signals to generate the vertical and horizontal CCD control signals.

Abstract: When a specific signal (such as copy guard signal) is added between horizontal synchronizing signals in a composite synchronizing signal, and the addition period of the specific signal is defined in a specific period on the basis of the vertical synchronizing signal, the composite synchronizing signal is masked to remove the specific signal, thereby obtaining a masked composite synchronizing signal. Afterwards, from the masked composite synchronizing signal, the horizontal synchronizing signal and vertical synchronizing signal are obtained. In the case of composite synchronizing signal containing noise, without masking, the horizontal synchronizing signal and vertical synchronizing signal are directly obtained from the composite synchronizing signal. Therefore, when noise is not present, the horizontal synchronizing signal and vertical synchronizing signal may be obtained without disturbing the video image.

Abstract: A horizontal synchronization circuit uses a standard decoder to generate a stable first signal locked in frequency and phase to horizontal synchronizing pulses in a composite video signal. A waveshaping circuit reshapes the first signal to generate a second signal for input to a synchronizing circuit. The synchronizing circuit generates a higher-frequency third signal. A timing generator divides the frequency of the third signal to generate a fourth signal having the same frequency as the first and second signals, and a fifth signal having a higher frequency. The fourth signal is fed back to the synchronizing circuit, and can also be used for synchronization of video signal processing. The fifth signal can be used for horizontal scanning at a rate higher than the standard horizontal frequency.

Abstract: An image signal reproducing apparatus includes a synchronizing signal generator which is configured so as to count the number of clocks of a generated clock signal, generate various kinds of timing signals in accordance with the result of count, compare the phase of the generated timing signal with the phase of an input synchronizing signal, and control a period to count the number of clocks of the clock signal in accordance with the result of comparison. It becomes thereby possible to form various kinds of correct timing signals even if the input synchronizing signal reproduced from a recording medium is deteriorated.

Abstract: In a video signal processing apparatus for correcting time axis errors using a memory, with replacement of a horizontal sync signal in a video signal read out from the memory by a reference horizontal sync signal, data appearing in a vertical flyback period is not lost. A vertical flyback period detecting circuit functioning as an inhibiting means detects the vertical flyback period and produces a detection signal. An AND gate gates the detection signal and a reference horizontal sync signal generated from a sync signal generating circuit, so that a replacement of the horizontal sync signal is inhibited during the vertical flyback period, and an address, a time code and an ID code which have been inserted during the vertical flyback period are not lost.

Abstract: A circuit for preventing the false detection of vertical sync pulses included in a video signal which also includes copy guard signals inserted in predetermined intervals thereof, including signal generating circuitry which is responsive to vertical sync pulses separated from the video signal for generating a corrected vertical sync signal, and inhibit circuitry for rendering the signal generating circuitry non-responsive to the separated vertical sync pulses during the predetermined intervals of the video signal, thereby preventing any falsely detected vertical sync pulses due to misinterpretation of the copy guard signals from being included in the corrected vertical sync signal. The inhibit circuitry preferably functions to count a predetermined number of horizontal sync pulses also included in the video signal before allowing any change in the output of the signal generating circuitry.

Abstract: A field synchronization system for asynchronous video signals, comprises a video display synchronized with a first video signal having a first line rate component and a first field rate component. A second video signal having a second line rate component is first stored in a field memory, having synchronous write and read ports. The second video signal is thereafter speeded up in a multiple line memory having asynchronous write and read ports and independently resettable write and read pointers. The second video signal may be subsampled, written and read into and out of the field memory respectively and written into the multiple line memory, all synchronously with the second line rate component. The second video signal is read out of the multiple line memory synchronously with the first line rate component. The write pointer is reset by a circuit which samples the first field rate component with the second line rate component.

Abstract: An apparatus for synchronizing a terminal equipment such as a TV camera includes an external synchronizing signal generator which includes a switching circuit which generates two frequency signals and alternately transmits these signals to the terminal equipment which is provided with a decoder circuit decoding an alternating rate of the two signals outputted from the synchronizing signal generator, and an internal synchronizing signal generating circuit receiving a decoder circuit and generating a new synchronizing signal on the basis of the decoded signal.

Abstract: A system for recording one or more individual fields or frames of a color, high definition video signal. In a preferred embodiment, the system is capable of digitally recording as many as 32 frames of a color, high definition video signal per memory board, and as many as four memory boards may be installed in the system. The invention is capable of performing partial or full frame (or field) transfers at any selected rate less than or equal to the standard video rate. In a preferred embodiment, the system of the invention accepts HDTV signals in either digital or analog format, includes a post processing unit for simultaneously reconstructing stored HDTV signals in both digital and analog format, and a control unit which emulates a conventional video tape recorder (in the sense that it responds to conventional video tape recorder control signals) for controlling the system's frame memory.

Abstract: In a method and apparatus for converting a synchronizing signal received from a controller for controlling a TV camera into a new synchronizing signal, a single frame synchronizing pulse for every two field pulses is generated on the basis of at least a vertical drive signal of the synchronizing signal received from the controller. The new synchronizing pulse which has a level higher than the white level and lower than the black level of a composite video signal generated by the TV camera is injected into a video transmission line connected to the TV camera for synchronizing the latter on the basis of the injected synchronizing pulse.