Abstract: The invention provides a clock frequency generator for the use of converting the format of the video signal, which generates a clock of an unified frequency, in order to obtain the horizontal and the vertical synchronizing signals for the video signal after the format conversion without changing the field frequency and the scanning lines of the standard video signal. By using the clock generated by multiplying by a factor of 4740 the horizontal synchronizing signal for the SD format interlace scanning signal in the first multiplier (0009) and the second multiplier (0003), the horizontal synchronizing signal for the HD format interlace scanning signal is generated from the output terminal (0007) and the vertical synchronizing signal for the HD format interlace scanning signal is generated from the output terminal (0008) without changing the standard number of the scanning lines and the field frequency.

Abstract: A clock generator is provided which comprises a reference signal generator; a voltage controller/generator to generate a dot clock signal; a frequency divider to divide the frequency of the dot clock signal supplied from the voltage controller/generator; a phase comparator to detect a phase difference between the reference signal supplied from the reference signal generator and a signal supplied from the frequency divider; a frequency division ratio setter to set the frequency division ratio in the frequency divider to less than a quotient resulted from division of a total number of horizontal pixels in each of the video signals by a greatest common divisor of the total of horizontal pixels in the video signal having one format and total number of horizontal pixels in the video signal having the other format; and a frequency division ratio selector to select a frequency division ratio set by the frequency division ratio setter correspondingly to a format of a video signal.

Abstract: In a video signal capturing apparatus with a simple construction capable of distinguishing fields in units of a color field, a separation circuit separates from input video signals, vertical synchronizing signals that lead fields in a one-to-one relationship. A field counter formed by, for example, a scale-of-four counter, counts the number of vertical synchronizing signals. Based on the count value of the field counter and values set in a register, a timing generating circuit performs data capture in such a manner that color fields are distinguished from each other. If color field 3 is to be captured, a value “3” is set the register. The timing generation circuit compares a count value from the field counter with the set value “13”. When the count value equals 3, the timing generation circuit starts capture of digital video data in the determined field. An even-odd number determining circuit may be provided for distinguishing (i.e.

Abstract: The signal processing apparatus for setting a vertical blanking signal of the television set that allows to set the beginning position and end position of a horizontal blanking signal irrespective of the numbers of lines in the vertical synchronous signal interval, comprising: an up counter for counting the vertical synchronous signal interval, synchronizing with the horizontal synchronous signal to lock forcedly the interlace signal to become a non-interlace signal; and a down counter for loading and down counting the count value of the up counter, wherein the down counter loads the data of the up counter immediately before the up counter is reset at a timing of the vertical synchronous signal and down counts the data which is loaded in the down counter as the initial value.

Abstract: A sync signal generator circuit comprises a first counter which is reset each time it detects a reference edge of the input sync signal, a first register for holding a first value immediately before the first counter is reset, a reset signal generator for generating reset pulses, a second counter which is reset each time it receives a reset pulse, a second register for holding a second value immediately before the second counter is reset, and a sync pulse generator for generating an output sync signal on the basis of the reset pulses. The reset pulse is generated each time the counted value of the second counter matches a predetermined value or each time the first counter detects the reference edge while an absolute value of a difference between the counted value of the second counter and the second value held in the second register is not greater than a permissible value of period fluctuations.

Abstract: A first counter counts a first clock signal repeatedly in accordance with an external synchronous signal. A second counter counts a second clock signal repeatedly in every predetermined cycle, and generates an internal synchronous signal having the predetermined cycle. A controller adjusts the cycle of counting performed by the second counter by controlling the second counter. By doing so, the controller controls the internal synchronous signal to synchronize with the external synchronous signal in each horizontal period.

Abstract: A programmable synchronizing system for selectively providing synchronizing signals at different rates, such as for incorporation in a video signal decompression system, includes an oscillator and a programmable counter. The programmable counter is conditioned to count pulses from the oscillator by alternate moduli in predetermined sequences to generate the synchronizing signals. The desired synchronization rate is effectively the average of the counter output resulting from counting by the alternate moduli.

Abstract: A reference signal having either twice or four times the frequency of a color burst signal (2fsc or 4fsc) is divided into a plurality of divided signals, each having the same frequency as that of the color burst signal, or an fsc frequency. In addition, a reference signal is delayed by a predetermined amount to thereby generate a delay signal. One of the divided signals is output in synchronism with this delay signal as a first divided signal having a predetermined delay. When this first divided signal is used as a color burst signal, the remaining divided signals resultantly all have phases shifted by a predetermined amount with respect to the color burst signal. With this arrangement, some of the divided signals can be used intact as a color signal, while the others may also be used after being delayed by a predetermined amount.

Abstract: A video signal processing apparatus comprising an oscillating unit for outputting a signal of a stable frequency, a counting unit for counting the period of a cycle of a signal supplied from the outside based on the signal output by the oscillating unit, a clock number calculating unit for calculating the number of clocks in a line based on a result of counting by the counting unit, a comparing unit for comparing the number of clocks calculated by the clock number calculating unit with a threshold to decide which is larger, a switching unit for deciding the number of clocks in the next operation by switching to the number of clocks calculated by the clock number calculating unit if the calculated number of clocks is larger than the threshold, or deciding the number of clocks in the next operation by holding the number of clocks in a line in the current operation as it is, and a synchronizing signal generating unit for, based on the number of clocks in operation decided by the switching unit and the signal out

Abstract: A synchronize processing circuit offers a stable supply of synchronizing signal to control circuits in display devices.

Abstract: A signal production circuit for producing a control signal used in a driving and controlling circuit of a display device externally input to the driving and controlling circuit, using an external interface signal. There is a vertical synchronization signal having a predetermined frequency and a reference clock signal in synchronization with the vertical synchronization signal. The signal production circuit includes: a first counter circuit for counting a number of reference clock signal pulses up to a value of a parameter which is preset based on a time interval of one cycle of the vertical synchronization signal and a predetermined target period.

Abstract: The present invention relates to processing of a video signal in a computer display and the like, and aims at providing a synchronizing signal generator which can obtain a vertical synchronizing pulse whose phase is stable with respect to the horizontal synchronizing signal and in which a counter for counting a clock synchronized with the horizontal synchronizing signal has a small counted value. It comprises a counter (8R) for detecting the vertical synchronization period (N) on the basis of the horizontal synchronizing signal (Hsync) and an output switching unit (14) which outputs a vertical synchronizing pulse (Vd) synchronized with the vertical synchronizing signal (Vsync) when the input vertical synchronizing signal (Vsync) has a vertical synchronization period of a given range, and which selects and outputs a pulse (Sq) having a given vertical synchronization period when the input vertical synchronizing signal does not have a vertical synchronization period of the given range.

Abstract: A video format mode detector for detecting the format mode of a video signal transmitted from a video data output device such as personal computer, which includes a counter for counting a horizontal synchronous signal input during one cycle of a vertical synchronous signal separated from the video signal, generating positive counting data and negative counting data, a data holder for holding the output from the counter whenever the horizontal synchronous signal separated from the video signal is applied thereto, a data adder for adding up positive holding data and negative holding data sent from the data holder whenever the horizontal synchronous signal is applied thereto, generating data which indicates the number of horizontal lines corresponding to one cycle of the vertical synchronous signal, a data comparator for comparing the positive holding data and negative holding data with each other, outputting data having the smaller value, and a mode discrimination part for searching an ROM included therein, gen

Abstract: In a display monitor, a horizontal synchronization signal having a horizontal scanning frequency is received by a first circuit. A vertical synchronization signal having a vertical scanning frequency is received by a second circuit. A moire correction signal that is proportional to a horizontal resolution of the displayed image is generated by dividing the horizontal scanning frequency by the vertical scanning frequency.

Abstract: A method and an apparatus for control a timing in a flat panel display system are disclosed. In an alternating current plasma display system for respectively driving a plurality of subfields at every field in three steps such as a) entering and for eliminating a whole pixel for a first predetermined time, b) entering data for a second predetermined time and c) maintaining a discharge at every subfield for times which are different from one another, a first clock generator generates a first clock signal having a high frequency. A second clock generator generates a second clock signal having a low frequency. A first counter counts the second clock signal in response to a vertical synchronizing signal, and generates both a first pulse signal which sets the first and second predetermined times respectively in steps a) and b) in the respective subfield sections and a second pulse signal which sets times in step c) in the respective subfield sections which are different from one another.

Abstract: The period of an input signal is subdivided into N parts by carrying out a count, during this period, of the pulses delivered by a clock. This number is divided by N and then the remainder of this division is distributed among all the N parts of the period of the input signal. This technique may be applied to the generation of scanning signals in television.

Abstract: A sync signal generator with a signal discriminator comprising an input terminal supplied with a fist signal or a second signal of a higher frequency; a clock signal generating circuit; a first counter reset by the first or second signal received from an input terminal, and caused to halt counting the clock signal when the count thereof has reached a predetermined value MC4; a first detector for outputting a detection signal relative to the first or second signal during the counting action of the first counter; a second counter reset when the count of the first counter has reached a predetermined value MC1, and caused to halt counting the clock signal when the count of the first counter has reached a predetermined value MC2 (MC2<MC4), and to output a detection signal (SMAX) when the count thereof has reached another predetermined value SC1 (SC1<MC2); a second detector for outputting a detection signal relative to the second signal in response to the detection signal (SMAX) from the second counter; and a

Abstract: A system and method for obtaining and maintaining synchronization to a digital signal containing framing. The method searches for a synchronizing pattern and maintains a confidence counter indicative of the success in finding the synchronization pattern where expected. The confidence counter can be used to indicate when the system is locked to the framing of the digital signal and when resynchronization needs to occur.

Abstract: A synchronizing signal generator produces a PAL standard horizontal synchronizing signal using a PAL standard subcarrier signal as a timing reference. The synchronizing signal period is not an even multiple of the subcarrier signal period. To produce the synchronizing (sync) signal, the generator first frequency multiplies and divides the input signal to produce a reference signal having a period that is a rational multiple of the subcarrier signal period but smaller than the desired sync signal period. The generator then delays each successive pulse of the reference signal by increasingly longer delay times to produce the sync signal.

Abstract: A scan converter receives VGA or SVGA graphics data and outputs NTSC or PAL TV data. The scan converter is integrated inside a personal computer's graphics controller, allowing the digital-to-analog converter (DAC) to be used for either CRT-pixel conversion or TV encoding. The VGA timing is altered to better match with TV scan-conversion. The horizontal rate is not constant but can be increased or decreased during the vertical blanking period. A second register is provided for the total number of pixels in a line during vertical blanking, while a first register contains the total number of pixels in a displayable line not during the vertical blanking period. Since lines with fewer pixels require less time to display, the period of time or rate for blanked lines is changed. An extra horizontal line is added during vertical blanking for every second frame for SVGA conversion to better match the asymmetry of TV standards.

Abstract: A horizontal synchronization signal generating circuit self-generates a horizontal synchronization signal if an actual horizontal synchronization signal fails to be detected in a composite video signal. Each time an edge-detection circuit detects an actual horizontal synchronization pulse, a counter and decoder are reset. An actual horizontal synchronization signal has a period of 63.5 .mu.s. If the edge detection circuit fails to detect the actual horizontal synchronization signal, then the decoder outputs a self-generated horizontal synchronization signal at 64 .mu.s and a selector circuit disables the edge detection circuit for approximately 35 .mu.s. In contrast, if the edge-detection circuit detects an actual horizontal synchronization signal, the decoder is reset before it can output the self-generated signal and the selector disables the edge detection circuit for approximately 60 .mu.s. Accordingly, a period of 35 .mu.

Abstract: The invention provides a horizontal synchronizing signal frequency measuring instrument which can measure a horizontal synchronizing signal frequency with a higher degree of accuracy. The horizontal synchronizing signal frequency measuring instrument includes a first counter for counting a reference clock signal, a second counter of the preset type for counting a horizontal synchronizing signal, and a control section operable to detect an edge of the vertical synchronizing signal, set a first preset value to the second counter, detect that a count value of pulses by the second counter reaches a first preset value, renders a count control signal active, reset and start the first and second counters, detect that the count value by the second counter reaches the second preset value, render the count control signal inactive and calculate a frequency of the horizontal synchronizing signal from the count value of the first counter, the second preset value and a frequency of the reference clock signal.

Abstract: A synchronizing signal creating circuit which can feed stable synchronizing signals even after input signals stop. it is constituted of gate circuit 804 makes signal (G) into logic level 1 and outputs to switching circuit 818 when the still picture creating apparatus which executes processing with the synchronizing signals created by synchronizing signal creating circuit 80 executes creation or output of still pictures, and when frame synchronizing signal (IFP) and the frame pulse do not synchronize. Switching circuit 818 selects contact point b and outputs numerical value (V.sub.DC) to digital/analog converting circuit 816 so the operation of PLL loop stops. Consequently, in this case, voltage control oscillating circuit 820 creates signals (HCK) with a frequency corresponding to numerical value (V.sub.DC) and in other cases, creates signals (HCK) with a frequency determined by the operation of the PLL loop.

Abstract: A system for generating a video control signal to process a video signal associated with a video composite signal. The video composite signal has horizontal and vertical driving signal, each having one or more pulses. The system comprises a counter for counting the number of the pulses of respective one or more of the horizontal and vertical driving signals, and a flip-flop, which is coupled to the counter, for generating a blanking signal based on the result of the counting.

Abstract: The present invention relates to a device which generates a vertical synchronizing signal of video signals according to digital methods.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronisation signal component, the synchronisation signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: A data collision avoidance circuit is utilized in a memory write control circuit of an image signal processing apparatus for preventing the write and read clocks of a FIFO memory from colliding. The circuit contains a write enable signal generating unit, a window pulse section set up unit, and a write enable signal control unit. The write enable signal generating unit generates a write enable signal in response to the write control odd/even field signal to write the data into the FIFO memory. The window pulse section set up unit generates a window pulse signal having a predetermined pulse width. The time interval of the predetermined pulse width is designed to be greater than a time interval during which write and read clocks of the FIFO memory can potentially collide, and the window pulse signal is generated in response to a read control odd/even field signal.

Abstract: A motor control unit (15c) for synchronizing a color wheel (15) to an incoming video signal and for re-synchronizing the color wheel after a channel change. The motor control unit (15c) has an error control unit (31), which detects an out-of-phase condition, and derives a color wheel sync signal from the pixel sample clock adjusted by any phase error. A drive unit (33) phase locks this sync signal to an index signal provided by the color wheel. The result is a tightly controlled re-synchronization that minimizes perceived effects.

Abstract: The present invention relates to a synchronizing signal generation circuit equipped with a PLL circuit. A pulse signal having a time constant that is broader than the clock width of a horizontal synchronizing signal included within synchronizing signals and that moreover contains steady-state phase error of the PLL circuit is generated and inputted to a phase comparison inhibiting circuit by way of a signal conversion circuit. The logic level of the pulse signal is then varied for the active interval and the inactive interval of the vertical synchronizing signal, phase comparison of the horizontal synchronizing signal and the reproduced horizontal synchronizing signal being inhibited during the active interval. The reproduced horizontal synchronizing signal is generated based on the output of two frequency dividers.

Abstract: An external sync image superimposing apparatus synchronizing an analog video signal with digital image data is provided by an apparatus which includes a sync separator for separating an external composite sync signal from an external composite image signal, a clock signal generator for synchronizing the frequency of the clock signal with an external sync signal according to a phase difference between the horizontal sync signal of the separated external composite sync signal and the internal horizontal sync signal and generating the adjusted clock signal, a sync signal generator receiving the adjusted clock signal for generating an internal composite sync signal and a reproduction address signal, a video memory for reading stored digital video information according to the reproduction address signal and a superimposing circuit for converting the digital video information from the video memory into an RGB signal, encoding the internal composite sync signal and the RGB signal as a color television signal, and su

Abstract: A camera apparatus in which a video camera and a photographic camera are integrally combined or which has a self-timer function, and an aspect conversion circuit for converting the orientation of an image are provided. A normal mode and a self-timer mode are provided, and in either mode, a shutter pulse synchronized with a vertical synchronizing signal is obtained from an output signal of a frequency divider, while in the self-timer mode, a timer is driven by the output signal of the frequency divider, whereby the frequency divider is used in both modes. Alternatively, a still mode and a video mode is provided, and in the still mode, a shutter pulse and a record pulse are output in response to an operation of a shutter switch, while in the video mode, the record pulse is output in response to an operation of a record switch and the shutter pulse is output in response to an operation of the shutter switch.

Abstract: A programmable CPU running at a video display rate, or a sub-multiple thereof, is used to generate the timings by loading control registers on the fly. In a preferred embodiment, a very reduced instruction set is used to generate VSYNC, HSYNC, and CSYNC signals. The CPU executes instructions out of an Instruction SRAM. The CPU's main goal is to load a pair of backing registers before a down counter reaches the value of zero.

Abstract: Before transmission of moving image data, the period of a frame of the moving image data is counted using a clock signal used for the transmission to produce a frame count. The moving image data is then transmitted along with the frame count so that it can correctly be timed in frames at receiver.

Abstract: There is disclosed a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal which has no frequency variations and which is in phase with an entered composite synchronizing signal if the entered composite synchronizing signal is a nonstandard signal having a varying horizontal frequency. A horizontal counter circuit (5) counts a reference clock (V.sub.CL), and a window pulse generating circuit (4) outputs a window pulse signal (V.sub.W) which is low for a fixed time period when a counter output (V.sub.CT) equals a counter value (878) indicative of a standard output timing. A horizontal synchronizing signal separating circuit (1) outputs a horizontal synchronizing signal (V.sub.2) only when the composite synchronizing signal (V.sub.1) falls within the fixed time period. Then a horizontal phase judging circuit (2) outputs a standard signal flag (V.sub.3) and a synchronizing signal generating circuit (3) outputs the horizontal synchronizing signal (V.sub.

Abstract: A synchronization (sync) separation system and method quickly and accurately generate a sync signal from an analog video signal by using feedback control. The system comprises a voltage generator for generating first and second reference voltages V.sub.REF1, V.sub.REF2. A first comparator compares the analog video signal to the first reference voltage V.sub.REF1 and generates a shift control signal, A voltage shift mechanism receives the shift control signal and adjusts the analog video signal so that the sync level of the analog video signal converges toward the first reference voltage V.sub.REF1. A second comparator compares the analog video signal with the second reference voltage V.sub.REF2 and generates the sync signal indicative of when the analog video signal exhibits the sync level. Preferably, the voltage shift mechanism introduces a continuous current i.sub.c into the analog video signal.

Abstract: The invention inputs a single timing clock. Through procedure of mode setting, the invention generates the required timings corresponding to the display mode selected. In the invention, a programmable mode register, a mode decoder, a pixel timing generator, a horizontal timing generator, a vertical timing generator, a composite timing generator, AND gate, EXCLUSIVE NOR gate, and a selector are provided. The invention may generate the required timings for NTSC interlace mode, NTSC non-interlace mode, PAL interlace mode, PAL non-interlace mode, VGA 60 Hz progressive mode and VGA 50 Hz progressive mode.

Abstract: A video camera in which an output signal from a solid-state image sensor is converted into the corresponding digital signal at the horizontal reading cycle of the output signal, and the digital signal is digital-processed with a first predetermined clock (fs) synchronous with the reading cycle to provide a luminance signal and a color difference signal.

Abstract: This specification concerns signal processing apparatus for processing line synchronization pulses in a line synchronization signal that define an analog video signal line period. The apparatus comprises a phase locked loop (40) for generating a clock signal of a frequency that is a multiple of the line synchronization signal frequency. The phase locked loop (40) comprises a counter (100) for dividing the clock signal by said multiple. The apparatus further comprises logic (110,50) for resetting the counter (100) upon detection of a spurious pulse introducing a time interval into the line synchronization signal of less than the line period of the video signal. The apparatus is particularly useful in image processing systems for digitizing analog video signals that have been replayed via a conventional, domestic video tape player, and therefore may comprise spurious line sync pulses introduced by playback head skip.

Abstract: In a vertical deflection circuit of a display monitor including a vertical deflection coil 41 and a sigmoid correction capacitor 42 connected to the vertical deflection coil 41, a series connection circuit consisting of a resistor 21 and a switch 22 connected in series with each other is connected in parallel with the sigmoid correction capacitor 42. By turning the switch 22 on and off in response to a control signal having a period twice as long as a period of the vertical synchronizing signal, a current flowing through the resistor 21 and the switch 22 is periodically added to a vertical deflection current, thereby causing shift of displaying points on a screen to make the moire phenomenon unnoticeable.

Abstract: A digital multivalue synchronizing signal generating circuit generates three-value synchronizing signals for one frame using an address counter operating by a clock frequency which is more than 50 times the horizontal frequency and a ROM, and the three-value synchronizing signals are limited in band by a digital filter operating by the sampling clock of the digital video signal, and a digital multivalue synchronizing signal is generated. The video signal processing apparatus possessing a digital multivalue synchronizing signal generating circuit combines the digital video signal and digital multivalue synchronizing signal digitally, and produces a video signal having a digital synchronizing signal, and by D/A conversion thereof, a video signal having a analog synchronizing signal without waveform deterioration in the synchronizing signal portion is obtained.

Abstract: Signal processing apparatus comprises a chrominance subsampler (10) for sampling the U and V components of a PAL video signal in response to an enable signal. A counter (30) responsive to the horizontal synchronization component of the PAL video signal generates the enable signal upon detection of a predetermined number of horizontal synchronization pulses. Logic (60,70,80) responsive to the vertical synchronization component of the PAL video signal resets and disables the counter (30) upon detection of a vertical synchronization pulse. Logic (50,60,70,80) restarts the counter (30) from a reset state upon detection of a predetermined polarity in the V component of the PAL video signal.

Abstract: A sync signal generating apparatus for use in a converter for converting a broadcast signal between different broadcast systems so as to generate a sync signal adapted for the converted broadcast system.