Abstract: A synchronous signal separation circuit 2 for separating horizontal synchronous signal HSn is connected to a horizontal synchronous signal detection circuit 3, which includes a switch 4, an oscillator 5 and a window signal generator 6 for generating a window signal WP. The switch 4 passes the separated horizontal synchronous signal HSn during an open-period of the window signal WP and intercepts the separated horizontal synchronous signal HSn during a close-period of the window signal. The oscillator 5 generates a rate signal having a period equal to a horizontal scan period synchronously with a change in an output signal HS from the switch circuit, and adjusts a time duration of the open period of the window signal so as to make a timing of a change in the output signal HS coincide with a generation timing of the rate signal while the open-period of the window signal is synchronized with the generation timing of the rate signal.

Abstract: A wireless receiving device of the present invention is so arranged that (i) a high-frequency circuit section is provided on a front surface of a printed board and (ii) a digital video signal processing section and a wireless LAN digital signal processing section are provided on a back surface of the printed board. Further, an earth pattern is provided in a middle position between the front and back surfaces of the printed board, so that (i) the high-frequency circuit section and (ii) the digital video signal processing section and the wireless LAN digital signal processing section are shielded from one another using electromagnetic shielding by the earth pattern. Thus, when members that are commonly used for the wireless LAN and for wireless video reception are formed on a single printed board in order to reduce the size of the printed board, it is possible to effectively reduce the lowering of signal quality caused by the noise.

Abstract: A display device that is capable of displaying either one of a video signal whose aspect ratio coincides with that of a display screen and a video signal whose aspect ratio differs includes a boundary-position detector 5 for detecting a boundary position between a signal of a picture portion of the video signal whose aspect ratio differs and a signal of a non-picture portion on the basis of the video signal and a synchronizing signal which are inputted to the boundary-position detector 5, a masking-control-signal generator 15 for generating a masking control signal for masking the non-picture portion and an end portion of the picture, and a masking section 6 for replacing the signals of the non-picture portion and the end of the picture portion with a predetermined substitute video.

Abstract: A method and apparatus for compensating for time base or phase errors in video and audio signals that are separately stored or processed. A ring oscillator provides a plurality of clock signals, each having a same frequency and slightly different phase. Each of the clock signals is applied to a multiplexor for allowing an appropriate one of the clock signals to be selected. By selecting appropriate ones of the clock signals in a sequence, the frequency and phase of an output clock signal formed by the multiplexor can be continuously and precisely controlled. Sync pulses separated from a video signal having a varying time base are applied to a video timing generator circuit which generates a series of digital values representative of timing differences between an expected occurrence of a sync pulse and an actual occurrence of the sync pulse. A phase accumulator accumulates the digital values over time for generating appropriate addresses for the multiplexor.

Abstract: A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch (34) to clamp the DC level therein for a given pixel. A switch (38) then samples the reset level onto a sampling capacitor (46), and a switch (42) thereafter samples the video signal onto one plate of a capacitor (50). The lower plates of the capacitors (46) and (50) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier (68). An offset is provided by a programmable DAC (26) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors (46) and (50) can be varied to vary the gain of the amplifier.

Abstract: An apparatus and method for extracting vertical (V-SYNC) and horizontal (H-Blank) sync signals from a digital composite sync signal (C-SYNC) of a master video source for use in controlling a second video source, which allows for an adjustable delay relationship between the C-SYNC from the master source and the generated H-Blank. The present invention also provides a system and method for varying the responsiveness or gain of the genlocking circuit used to synchronize the system pixel clock frequency of the second video source to that of the master video signal.

Abstract: In a device for reducing noise in image signals, the image signals passing through a temporal recursive filter whose feedback factor is a function of movement in the images represented by the image signals, in order to form the feedback factor for the respective current image, a first and a second factor are combined in such a way that the smaller one of the factors substantially determines the feedback factor. The first factor is formed from the feedback factor of the preceding image, and the second factor is calculated from the difference between the preceding image and the current image.

Abstract: In a photosensitive device wherein voltages are read sequentially from a dark, or dummy, photosensor and a plurality of active photosensors with each of a series of scans, a circuit downstream of the photosensors resets the offset value of the voltage signals, based on successive voltage readings from the dark photosensor. An RC averaging circuit maintains a running average of readings from the dark photosensor over a large number of scans. Signals from the dark photosensors are read a first time into the averaging circuit, and then signals from the dark photosensors are read directly to downstream video circuitry. This double readout of dark-photosensor signals enables precise calibration of both on-chip circuitry and downstream video circuitry.

Abstract: The invention concerns a method for determining the quality of a video and/or television image signal. In diversity reception installations comprising several receivers, it is necessary to establish a criterion for assessing the reception signals, so as to select the receiver with the best reception. In order to determine the quality of a television image, the interfering impulses appearing in a line after a horizontal synchronization impulse are detected then their parameters are evaluated. The invention is applicable to television receivers, video recorders, diversity reception installations, in particular for mobile installations.

Abstract: A method for obtaining line synchronization information items from a video signal is proposed. To that end, the following improvement measures are proposed: a) an accurate determination of the position of a line synchronization pulse is effected by carrying out a convolution operation between the video signal for the video line and a pattern function. The exact position is then established by analysis of the result function (&phgr;sv(k)) of the convolution operation. B) time-domain filtering of the established positions of the line synchronization pulses is carried out, in which a linear or non-linear estimation for the purpose of determining the corrected positions of the line synchronization pulses is carried out in each case. The invention also relates to an apparatus for carrying out the method.

Abstract: A signal treatment circuit treats an input signal containing line sync pulses used for displaying data on a screen. The circuit contains a phase locked loop to control horizontal sweeping according to active edges of line sync pulses, and a filter circuit that filters equalizing signals from the input signals and provides a filtered input signal to the phase locked loop.

Abstract: A symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output. If the clamped video level drops suddenly, a delayed version of the fixed composite sync output clocks a flip flop, creating a fault signal which discharges a memory capacitor over a time period.

Abstract: Video compressed by (macro)block level motion compensation has bitstream with the motion vectors aggregated and separated form the corresponding texture data by a resynchronization word, and a method of generating resynchronization words from variable length code tables which encode the motion vectors or the texture data adjacent to a resynchronization word.

Abstract: In a Sync signal detection circuit for detecting a Sync signal included in a television signal transmitted in a digital mode, pattern check means 2 checks a pattern of a Sync signal which is super imposed on a series of input data with a reference pattern. Based on a check result, Sync detection determination means 5 outputs a Sync detected signal or a Sync non-detected signal. Sync detection initialization means is further provided to this detection circuit for outputting forcibly a Sync non-detected signal when a signal of a series of input data is switched over. As a result, a Sync signal can be detected within a shorter period than the conventional circuit structure.

Abstract: A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both sample and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus.

Abstract: A video signal level detector is configured to avoid the erroneous recognition of channels adjacent to normal channels as those which are to be stored during performance of an automatic channel detection and storage function. The video signal level detector separates at least two target signals whose levels are to be detected from an input composite video signal; detects signal levels of the target signals; compares each of the detected levels with a reference voltage level; and logic-operates the result to obtain a final detection so that a storage possibility of automatically detected channels is determined.

Abstract: Sync separator and video detector circuits, including a sync tip clamp having symmetrical and non-symmetrical clamps. The symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output.

Abstract: A technique for delivering analog video over fiber-to-the-home (FTTH) networks addresses a fundamental problem of the standard signal format, i.e., power budget constraint, by increasing the usable optical signal efficiency. In particular, a technique is provided for transmitting an efficient modified analog video which is compatible with existing receivers. More specifically, the synchronization portion of a standard NTSC video signal is reduced in amplitude during transmission, producing an appreciable increase in the allowable optical modulation index (OMI).

Abstract: An apparatus and method for generating a clock signal phase-locked to a horizontal synchronization signal of a digital video signal in which noise superposed on the horizontal synchronization signal is eliminated or reduced. To eliminate or reduce such noise, a noise suppressing device located prior to a phase comparator may be utilized. Such noise suppressing block may include a slice circuit and/or a spike removing circuit.

Abstract: A device for extracting synchronization from a video signal. The device includes a dual-threshold synchronization pulse detection circuit, a first threshold device for detecting the leading edge of a pulse, and a second threshold device for detecting the trailing edge of the same pulse. The thresholds of the devices are defined by a synchronization pulse amplitude detector. The device includes sample-and-hold circuitry for bringing back the voltage stored by the amplitude detector in a storage capacitor to the voltage corresponding to the synchronization pulse, when a synchronization pulse is detected.

Abstract: An arrangement for stabilizing a horizontal synchronization signal, serving as an input signal for a phase-locked loop (PLL) for generating a clock signal, by separating the horizontal synchronization signal from a composite synchronization signal including both horizontal and vertical synchronization signals. A horizontal synchronization gate signal is generated for outputting a pulse signal approximately in phase with the horizontal synchronization signal and having at least the pulse width of the horizontal synchronization signal in accordance with the composite synchronization signal and a clock pulse signal having a predetermined frequency. The horizontal synchronization signal is retrieved from the composite synchronization signal in accordance with a logical product when matching the polarity of the horizontal synchronization gate signal with the polarity of the composite synchronization signal.

Abstract: An apparatus and method for suppressing noise and an input image having a plurality of pixels, each of the pixels in the plurality of pixels having a range of possible values between at least two extremities. A first group of pixels is determined, each pixel of the first group having a value that is less than a predetermined amount from the value of at least one of the extremities. The values of pixels adjacent to each pixel in the first group are examined to determine if the adjacent pixels are also members of the first group and, when a predetermined number of the pixels adjacent to a pixel in the first group are also members of the first group, reassigning the pixel value of that pixel in the first group and each of its adjacent pixels to have the value of at least one of the extremities.

Abstract: A noise reduction circuit for use with video signals or image producing signals in which trailing and other image degrading phenomena are prevented by not using the noise reduction circuit for the edge of the motion picture portion on the image. The noise reduction circuit includes a subtractor 14 which outputs a difference signal E between input video signal VSi and delayed video signal VSd. ROM 18, a look-up table that forms the coefficient multiplier, outputs a corrected difference signal KE corresponding to the difference signal E from subtractor 14. At adder 12, corrected difference signal KE from ROM 18 is added to input video signal VSi, forming output video signal VSo processed by the noise reduction processing. However, when "H" level expansion video signal MEH,Y is output from vertical expansion circuit 42, the outputs of AND gates 24, 26 become null, and the output signal of ROM 18 becomes null.

Abstract: The present invention provides a more reliable circuit for judging the existence of television image signals. A circuit for judging the existence of television image signals by counting the number of edges of the synchronous signals of a composite synchronous signals for a certain period, and judging the existence of TV image signals, wherein a mask timer circuit which masks signals generated following the synchronous signals for a certain period after the composite synchronous signal is detected, is installed before a synchronous counter.

Abstract: An auxiliary video information decoder for decoding information such as closed caption data in a video signal identifies a desired horizontal line of video in a video signal. A reference pulse in a synchronizing signal is detected followed by the generation of first and second window pulse signals occurring at predetermined delays after detection of the reference pulse. A pulse occurring in the synchronizing signal during the window pulses indicates the start of the desired horizontal line interval. A field identification signal may also be generated. Features for improving noise and phase error immunity when identifying a video line are provided.

Abstract: A synchronizing signal separating circuit for a television receiver, comprising: a source of a video signal having a line synchronizing signal component; a line synchronizing signal component separator having an amplitude selective stage and having a flywheel stage imparting a response time constant to the separator which enhances noise immunity; a delay circuit for the video signal, for example a multiple line delay, coupled ,between the video signal source and the separator; a control circuit coupled to the video signal source and evaluating the time positions of line synchronizing pulses of a plurality of successive lines to identify a kind of line phase disturbance in which the line phase of an entire raster is displaced, the control circuit supplying a control signal to the separator indicative of the kind of phase disturbance; and, the flywheel stage being temporarily rendered inoperative responsive to the control signal, for example by temporarily decreasing the response time of the separator, upon ide

Abstract: A clamping circuit for applying clamping to a signal having a plurality of components includes a frequency divider which frequency-divides a main clock signal of the clamping circuit by an even number when the plurality of components of the signal are odd in number and another frequency divider which frequency-divides the main clock signal of the clamping circuit by an odd number when the plurality of components of the signal are even in number. Manual adjustment of an optical black correction is provided which permits verification of an accurate optical black correction by monitoring color difference vectors on a vector scope.

Abstract: In monitor circuitry, a simple circuit separates out the horizontal synchronization pulses from the composite synchronization signal and removes undesired horizontal synchronization pulses during the vertical blanking period. By using a pulse-width modulated signal having the same frequency as the horizontal rate but not necessarily with the same phase, and having at least a 50% duty cycle, the undesired pulses are gated out before being coupled to the horizontal synchronization circuit of the monitor, thus, the monitor system will not attempt to lock at a double frequency, nor cause visible distortion of the raster. The effect of the pulse width modulated signal is inhibited when a user changes the horizontal synchronization frequency and until the monitor achieves lock on the new frequency.

Abstract: A self-adjusting window circuit suitable for fabrication as a monolithic integrated circuit. The self-adjusting window circuit comprises an input port, a positive edge detector coupled to the input port, a latch coupled to the output of the edge detector and a charging stage coupled to the latch. The input signal comprises a signal having a sequence of pulses appearing at a predetermined scan rate, for example, a composite video signal. The input port feeds the input signal to the edge detector which produces a pulse output signal in response to detecting a pulse in the input signal. The pulse output from the edge detector is latched and used to generate a charging control signal which controls the charging stage. In response to the charging control signal, the charging stage produces a window control signal for a predetermined period.

Abstract: An apparatus for separating vertical synchronizing signal components from image signals in a VCR of a double rotation head helical scanning system. The apparatus comprises a level detecting unit for detecting the level of an output signal from an amplifying unit, a comparing unit for comparing the output signal from the level detecting unit with a reference voltage (V.sub.1), a switching unit operable according to the output signal from the comparing unit, and a limiting unit for limiting an output signal from a demodulating unit to a predetermined limit voltage (V.sub.2) via the switching unit upon the operation of the switching unit. The apparatus achieves an accurate separation of vertical synchronizing signal components in all cases of using a combined head for a SP/LP mode and using a single head for a SP mode or a LP mode.

Abstract: A copy guard processing detecting apparatus which can correctly judge whether or not a copy guard is applied to an input video signal and prevents copy guard processing from being applied to a video signal to which a copy guard is not applied. The copy guard processing detecting apparatus comprises a first circuit for receiving an input video signal which includes a plurality of false synchronizing signals for prevention of duplication inserted in a vertical blanking interval thereof and for counting the number of the false synchronizing signals, a second circuit for counting the number of synchronizing signals in an image interval of the input video signal except the vertical blanking interval, and a discriminator for discriminating whether or not copy guard processing is applied to the input video signal from the count values of the first and second circuits.

Abstract: When a specific signal (such as copy guard signal) is added between horizontal synchronizing signals in a composite synchronizing signal, and the addition period of the specific signal is defined in a specific period on the basis of the vertical synchronizing signal, the composite synchronizing signal is masked to remove the specific signal, thereby obtaining a masked composite synchronizing signal. Afterwards, from the masked composite synchronizing signal, the horizontal synchronizing signal and vertical synchronizing signal are obtained. In the case of composite synchronizing signal containing noise, without masking, the horizontal synchronizing signal and vertical synchronizing signal are directly obtained from the composite synchronizing signal. Therefore, when noise is not present, the horizontal synchronizing signal and vertical synchronizing signal may be obtained without disturbing the video image.

Abstract: Noise estimation circuitry for estimating the noise in a small number of horizontal scanning lines of a video signal includes a lowpass line comb filter responding to said video signal, but not to chrominance-descriptive components thereof. The video signal free from chrominance-descriptive components is repeatedly sampled during the backporch interval of each horizontal scanning line, and the samples are accumulated to generate a revised noise estimate each successive horizontal scanning line.

Abstract: A vertical synchronization processing circuit includes a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A circuit for discriminating an existence of a vertical synchronization interval can also be provided along with a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case there is not a vertical synchronization pulse within the predetermined limit.