Abstract: In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

Abstract: The present disclosure relates to management of presentation content including technical instances where presentation content interacts with live feeds. The scope of the present disclosure covers technical examples that pertain to creation/design of presentation content as well technical examples where presentation content is presented in real-time (or near real-time). Design solutions are provided enabling users to easily interject a representation of a live camera feed into presentation content. For example, an editable GUI object is presented enabling users to incorporate a representation of a live camera feed into slide-based presentation content. The present disclosure further provides processing that fosters dynamic management of presentation content including interactions with live camera feeds during a presentation. Furthermore, an improved GUI presents GUI elements and notifications to aid management of representations of live camera feeds relative to presentation content.

Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.

Abstract: A computer-implemented method according to one embodiment includes obtaining, by a first LPAR, first device information about devices that a first LPAR is physically connected to. The first device information is sent by the first LPAR to a storage device for storage therein. Second device information stored on the storage device by a second LPAR is accessed by the first LPAR. The second device information includes information about devices that the second LPAR is physically connected to. The method further includes performing, by the first LPAR, a function using the second device information. A computer program product for device information sharing between a plurality of LPARs according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. The program are instructions readable and/or executable by a first LPAR to cause the first LPAR to perform the foregoing method.

Abstract: A communication device according to an embodiment includes: a processor configured to execute a media clock for generating a frame synchronization signal having a frequency which is m times a sampling frequency; a first interface configured to output 2m-channel audio data to a DAC or receive an input of the 2m-channel audio data from an ADC, in synchronization with the frame synchronization signal; and an external counter configured to generate a frequency-divided frame synchronization signal obtained by 1/m-frequency division of the frame synchronization signal and output the frequency-divided frame synchronization signal to the DAC and the ADC.

Abstract: A bus system having a plurality of bus components connected in a bus for the transmission of process data by all bus components, with a master as one of the bus components, with at least one slave as one of the bus components. The master has a master system clock for a master system time. The slave has a slave system clock for a slave system time to be synchronized with the master system time. The master is set up to send a synchronization command at a synchronization time via the bus for the parallel reception by the bus components embodied as slaves. The slave system clock of the slave is set up to calculate and output the slave system time based on the synchronization time received by the data transmission and the synchronization signal time and the current time value of the monotone clock.

Abstract: In a display controller for generating a video sync signal using an external clock, he display controller includes an initializer configured to initialize an internal parameter in response to a frame start signal. A sync signal generation circuit is configured to count the external clock, increase the internal parameter, and generate the video sync signal according to a result of comparing the internal parameter that has been increased with a setting value. An original use of the external clock may not be generating the video sync signal.

Abstract: There is provided a system including a non-transitory memory storing an executable code, and a hardware processor configured to execute the executable code to receive first and second Internet protocol (IP) video packets including respective first and second video content, and to identify a common reference time for the first and second IP video packets. The hardware processor also determines a first buffering interval for synchronizing the first and second IP video packets based on a first frame number, a first line number, and a first pixel number of the first video content, and the common reference time. In addition, the hardware processor holds the first IP video packet during the first buffering interval, and releases the first IP video packet when the first buffering interval elapses so as to align the first video content with the second video content at the common reference time.

Abstract: A method for reducing electromagnetic interference (EMI) in a system that periodically operates with a fixed sampling frequency includes reading a digital signal to which an analog signal received from a sensor is converted, generating a time delay that is modulated each cycle of the fixed sampling frequency with software, starting to execute a digital signal processing algorithm by applying the time delay that is modulated, and transmitting to another device through write of the digital signal. Accordingly, the EMI spectrum is spread through the time delay that is modulated with software, resulting in reduced EMI level.

Abstract: There is provided a display device including a display panel, a plurality of data drivers configured to apply a data voltage to the display panel and to output a feedback signal indicating a driving status, a shared back channel configured to receive the feedback signal from the plurality of data drivers, a virtual feedback signal circuit configured to output a virtual feedback signal indicating a normal driving state of the plurality of data drivers, a timing controller configured to apply a data signal to the plurality of data drivers, and a switch connected to the timing controller, and configured to selectively connect the shared back channel or the virtual feedback signal circuit to the timing controller.

Abstract: Provided is a method for sending an in-band positioning signal and in-band positioning system in a communication network. The system includes: a Position Management Station (PMS), arranged to manage one or more Position Service Stations (PSSs) and provide a synchronization reference clock for the one or more PSSs; a positioning center network element, arranged to provide position estimation information for a terminal based on position information of the one or more PSSs and send the position estimation information to the terminal; and the one or more PSSs, of which each PSS uses a same frequency band used by the communication network and is arranged to generate an in-band positioning signal for measuring a distance, regulate a sending clock of the in-band positioning signal according to a difference value between a local sending clock and the synchronization reference clock and send the in-band positioning signal to the terminal.

Abstract: A LCD device includes pixels formed of column data lines and row scanning lines. The pixel includes a display element; a first switching unit that performs sampling on each frame data of an input video signal; a first holding unit that configures an SRAM, and holds sub frame data; a second switching unit that causes the sub frame data held in the first holding unit; and a second holding unit that configures a DRAM, and applies output data to the pixel electrode, a pixel control unit that performs an operation of repeating writing the sub frame data in the first holding unit, turning on the second switching units, and rewriting memory content of the second holding units; and a timing control unit. A delay of a certain period of time is sequentially given to a timing at which the pixel control unit turns on the second switching unit.

Abstract: The invention relates to transmission and reception of clock synchronization data in a wireless communication system. According to the invention a device for transmitting clock synchronization data obtains at least one time reference of a wireless communication system clock, controls transmission of a frequency reference of the wireless communication system clock via an air interface of the wireless communication system, and provides transmission of the time reference via a transport network associated with the wireless communication system, while the base station receives the frequency reference, locks an own oscillator to the frequency of the frequency reference, receives the time reference from the transport network and adjusts timing that is controlled by the oscillator based on the time reference.

Abstract: A multimedia system includes a data source for providing a multimedia data; a wireless transmitting module, coupled to the data source, comprising a wireless transmitter for transmitting the multimedia data; a wireless receiving module comprising a wireless receiver for receiving the multimedia data from the wireless transmitter; and a reproducing device, coupled to the wireless receiving module, for reproducing the multimedia data received by the wireless receiver.

Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

Abstract: A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock.

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: A method and device regenerating a pixel clock signal, the method comprising, and the device being configured for: determining a first drift value D1 representative of a first time difference between a reference clock signal RC and a local clock signal LC based on a local pixel clock signal LPC; adjusting the local pixel clock signal LPC according to an adjustment command to provide a regenerated pixel clock signal RPC; determining a second drift value D2 representative of a second time difference between the reference clock signal RC and a regenerated clock signal based on the regenerated pixel clock signal RPC; and providing the adjustment command to the adjustable clock generator 32; 132; 316 for adjusting the local pixel clock signal LPC, wherein the adjustment command is based on the difference between the determined first and second drift values.

Abstract: Various embodiments are described herein for a universal television receiver that is capable of processing television channel signals broadcast according to a variety of analog and digital broadcast standards. In particular, various embodiments are provided for avoiding interferers in a desired television channel signal and these embodiments generally include changing sampling rate, shifting certain oscillation frequencies or changing sampling rate and shifting certain oscillation frequencies.

Abstract: An image data processing apparatus of the present invention includes: a base clock output circuit for outputting a base clock; a plurality of image processors; and a plurality of external PLL circuits provided for each one of the plurality of image processors. The plurality of external PLL circuits each synchronize an output clock given from a corresponding one of the plurality of image processors with the base clock.

Abstract: A method for transmitting spectrum information is provided. The method includes: sampling a first video of a scene by a first sampling device and sampling a spectrum video of a sampling point in the scene by a second sampling device, and processing the spectrum video to obtain a spectrum information of the sampling point; calculating estimated transmission ratio coefficients of the spectrum video according to color integral curves of the first sampling device; estimating a location of the sampling point in each frame of the first video; and transmitting the spectrum information of the sampling point to a plurality of scene points in the first video according to the estimated transmission ratio coefficients and the location of the sampling point in each frame of the spectrum video through a trilateral filtering algorithm.

Abstract: Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value.

Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Abstract: A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.

Abstract: A clock data recovery circuit has: a receiver circuit configured to receive a serial data including a predetermined pattern and to sample the serial data in synchronization with a clock signal to generate a sampled data; a PLL circuit configured to perform clock data recovery based on the sampled data to generate the clock signal; and a false lock detection circuit configured to detect false lock of the PLL circuit by detecting a false lock pattern included in the sampled data. The false lock pattern is a pattern obtained by the receiver circuit sampling the predetermined pattern when the false lock of the PLL circuit occurs.

Abstract: A method for digitizing an analog signal through a pipelined analog-to-digital converter (ADC) may include pipelining a sample sub-stage, a quantization sub-stage and an amplification sub-stage to an ADC lane. Within a first of multiple pipelined stages, clock phases may be assigned to the ADC lane, including a sample clock phase, a quantization clock phase, and an amplification clock phase such that the quantization clock phase is non-overlapping with the sample clock phase and the amplification clock phase. The non-overlapping feature may be facilitated by generating multiple reference clock phases for the sub-stages of multiple ADC lanes, and interleaving assignment of the sample clock phase, the quantization clock phase, and the amplification clock phase to the reference clock phases among the multiple lanes.

Abstract: A video signal output device and method are capable of easily displaying moving images while synchronizing transmission-side data and reception-side data even if video data is asynchronously transferred to the reception side from the transmission side. A video signal output device for receiving video data transmitted from a transmitter in sync with a first clock through a communication unit, storing the video data in a storage unit, reading the video data from the storage unit in sync with a second clock, and displaying moving images on a display unit, includes a synchronization adjustment unit for detecting a video data correction amount in accordance with a reference video data amount in one vertical synchronous period and a video data amount of the second clock in one vertical synchronous period to adjust a predetermined horizontal scanning period in accordance with the video data correction amount.

Abstract: Embodiments of the invention are generally directed to video frame synchronization. An embodiment of a method includes receiving a first video data stream from a first source at a first port of a multi-port device, a first video frame of the first video data stream arriving at the first port at a first arrival time, and receiving a second video data stream from a second source at a second port of the multi-port device, a second video frame of the second video data stream arriving at the second port at a second arrival time. The method further includes determining an offset between the first arrival time and the second arrival time, determining one or more correction factors based at least in part on the offset, the one or more correction factors including a first correction factor for the first source, and sending a first command to the first source to modify a time of transmission by the first source of a third video frame following the first frame using the correction factor.

Abstract: A video signal processing apparatus may include a first analog-to-digital converter (ADC) configured to convert an analog video signal into a first digital video signal according to a first clock; and/or a second ADC configured to convert the analog video signal into a second digital video signal according to a second clock that is different from the first clock. The first and second clocks may have a first phase difference in a first section of the analog video signal, such that the first and second ADCs operate alternately, first ADC then second ADC, and the first and second clocks may be generated to have a second phase difference, that is different from the first phase difference, in a second section of the analog video signal that is different from the first section, such that the first and second ADCs operate alternately, second ADC then first ADC.

Abstract: Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference are transmitted to a wireless clock receiver which also receives the same reference clock frames. Source clock frames are re-constructed using the reference clock frames, clock difference information and the receiver's local clock system.

Abstract: A method for removing color noise on a slowly varying component contained in color difference component image data of image data which is imported from an image sensor and converted to brightness and the color difference component image data, includes the steps of: sampling pixels of said color difference component image data by thinning out according to a first defined sampling format when not performing a color noise removal process on the slowly varying component; determining if the color noise removal process is necessary to be performed or not; producing the color difference component image data, corresponding to a compressed image data size smaller than an image data size without said color noise removal process, by thinning out according to a second defined sampling format when performing said color noise removal process; and recording the color difference and brightness component image data.

Abstract: A signal transmission system includes a first clock signal generator and a second clock signal generator. The first clock signal generator is configured for generating a first clock signal according to clock information derived from a transmitted signal, wherein the transmitted signal is changed in response to a frequency change of a second clock signal, and the first clock signal generator enters a frequency-unlocked state if the second clock signal has a frequency transition from a first frequency to a second frequency during a first time period. The second clock signal generator is configured for generating the second clock signal having the frequency transition from the first frequency to the second frequency during a second time period longer than the first time period such that the first clock signal generator stays in a frequency-locked state during the second time period.

Abstract: The display apparatus includes an image display element being driven based on a digital video signal, a quantizing part converting an input analog image signal into the digital video signal based on a quantization phase and a quantization frequency, and a converting part converting an input value into an output value, the input value being a difference value of signal values of pixels adjacent to each other in the digital video signal. The apparatus includes an accumulating part accumulating the output values from the converting part that converts the difference values obtained over entire pixels in one frame of the digital video signal to produce an accumulation evaluation value, and a controller adjusting the quantization phase in the quantizing part such that the accumulation evaluation value becomes maximum. The output values a(m) for the input values k1, k2 and k3 satisfy conditions of a(k1+1)?a(k1)<a(k2+1)?a(k2), a(k2+1)?a(k2)=a(k3+1)?a(k3) and k1<mi-1?k2<k3<mi.

Abstract: The present invention provides a system and method for automatically controlling the phase of the clock signal for sampling an HDTV signal, which implements a new and improved method for phase detection. The system and method utilize the standard format of an HDTV signal to consistently ensure accurate phase detection. Particularly, the system and method detect the target phase for the sampling clock using a tri-level sync pattern that exists at the beginning of each display line. This tri-level sync pattern or “sync pulse” is well suited for phase detection since it includes several static areas separated by substantial transitions. Furthermore, by using the sync pulse of the HDTV signal, the system and method provide consistent and accurate results, since the sync pulse will not change regardless of the whether the video data is static or in motion.

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: A display device includes a display panel, a control circuit and a random number generating circuit. The random number generating circuit includes a plurality of shift registers, an output circuit, and registers which holds initial values. By providing a plurality of initial values, the randomness of random numbers can be enhanced. Further, the random numbers different from each other can be outputted from the plurality of shift registers and hence, it is possible to increase the frequency and to output the increased frequency by an output circuit. Further, by adding a noise control signal which suppresses the number of inversion of a digital signal, electromagnetic wave noises generated from a liquid crystal display device can be reduced. Further, by adopting an intermittent drive clock which intermittently repeats stopping thereof as a basic clock of the plurality of shift registers, electromagnetic wave noises generated from the display device can be reduced.

Abstract: Disclosed herein is a signal transmission system including: a first signal processing section configured to perform signal processing on a basis of a reference signal; a high-frequency reference signal generating section configured to generate and transmit a high-frequency reference signal having a higher frequency than the reference signal such that the high-frequency reference signal is synchronized with the reference signal; a low-frequency reference signal generating section configured to receive the high-frequency reference signal from the high-frequency reference signal generating section, and generate a low-frequency reference signal having a lower frequency than the high-frequency reference signal such that the low-frequency reference signal is synchronized with the received high-frequency reference signal; and a second signal processing section configured to perform signal processing on a basis of the low-frequency reference signal generated by the low-frequency reference signal generating section.

Abstract: There is provided a method of measuring delay variation between first and second elementary streams in a digital audiovisual data stream, comprising detecting and storing digital audiovisual data stream timestamp values, detecting and storing elementary stream timestamp values for the first and second elementary streams, interpolating the digital audiovisual data stream timestamp values and elementary stream timestamp values to form data sets having mutual sampling points, and subtracting the interpolated data set for the first elementary data stream from the interpolated data set for the second elementary data stream to form elementary stream difference values indicative of changes in delay over time between first and second elementary streams.

Abstract: Provided is a video display device that quickly determines, when a video signal of unknown resolution is input from the outside, the resolution of the video signal to correctly display a video.

Abstract: To realize a random number generating circuit that is optimum for a liquid crystal display device that is used in a terminal device that includes a display/input component. A liquid crystal display device includes a liquid crystal display panel, a control circuit and a random number generating circuit, the random number generating circuit comprises plural shift registers, an output circuit and a register that stores an initial value, and the random number generating circuit is equipped with plural initial values, whereby the randomness of the random numbers is improved. Further, it becomes possible to increase and output frequencies by the output circuit because it is possible to output respectively different random numbers from the plural shift registers.

Abstract: When an image signal suitable for performing automatic adjustment of an effective image area and a dot clock is not output, the adjustment may be unsuccessfully performed. An effective image area detector detects an effective image area and determines whether an image in the effective image area is a blank image. If a synchronization signal detector determines that there exists a synchronization signal and if the effective image area detector determines that the image is not a blank image, a controller adjusts an area captured as image data by an input signal processor.

Abstract: When transmitting a digital video signal having, as a variant clock signal, a clock signal of a frequency which does not fall within a predetermined frequency range, a frequency multiplier 21 carries out a frequency conversion of the frequency of the variant clock signal so as to generate a transmit side clock signal which falls within the predetermined frequency range, and a transmitting unit transmits, as a transmission digital video signal, the digital image data and control signal, as well as the transmit side clock signal, according to this transmit side clock signal. A receive side divides the frequency of the transmit side clock signal using a frequency divider 22 to obtain the variant clock signal after acquiring the digital image data and control signal from the transmit side digital video signal according to the transmit side clock signal.

Abstract: A system and method for detecting a sampling clock offset of an analog-to-digital converter used to digitize an analog image signal. A method comprises buffering samples of an analog image signal, computing a value of an autocorrelation function using the buffered samples and a delayed version of the buffered samples, and repeating the computing a value for delays in a range of delays. The method also comprises computing a sampling frequency offset from the values of the autocorrelation function and changing a sampling frequency using the sampling frequency offset.

Abstract: A circuit and a method for using the circuit to provide synchronization between a first video signal and a second video signal are provided, comprising a circuit to capture a first video signal, a circuit to measure the timing format of the first video signal including an input clock and count input Vsync pulses, a circuit to measure a phase difference between the first video signal and the second video signal, a circuit to generate an output video signal comprising a number of output Vsync pulses and an output clock, and a PLL circuit to control the output clock period as a constant ratio of the input Vsync period, and maintain a constant number of output clock periods per a number of input clock periods. Also provided is a system to perform the method as above using the circuit as above, maintaining a constant ratio between the output clock period and a number of input clock periods.

Abstract: It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system.

Abstract: Methods of generating a pixel clock signal for a multimedia source are provided in which a transmission clock signal having a first frequency is generated from a reference clock signal that has a second frequency. The generated transmission clock signal is multiplied by a multiple to generate the pixel clock signal.

Abstract: The method adjusts the phase of a quantization clock signal for a video signal automatically based on a received analogue video signal. The method includes a step of determining a horizontal start position and a horizontal end position of a pixel-level transition within the analogue video signal, a step of determining a stable-period start position and a stable-period end position at each transition by sequentially changing an adjustable phase of the quantization clock signal, a step of calculating an appropriate phase of the quantization clock signal based on the determined timings of the beginning and end of the stable periods within the analogue signal, and a step of setting the phase of the quantization clock signal to the calculated appropriate phase.

Abstract: A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

Abstract: The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.

Abstract: Methods and systems are described for displaying enabling the transmission, formatting, and display of multimedia data after a hot plug event during a start-up dead period. In particular, approaches for transmission, formatting, and display of multimedia data in the absence or non-operation of a hot plug detect system or signal, so that multimedia information can be displayed in a proper format even during the dead period when no hot plug detect signal is received.