Abstract: A display apparatus includes a display panel, a memory, a bit-data convertor, a switch, and a gate driver. The display panel includes pixels. Each pixel is connected to one of the data lines and one of the gate lines. The memory stores a plurality of image data corresponding to a frame period. The bit-data convertor determines a plurality of bit data. Each of the bit data corresponds to a degree of change between adjacent image data among the plurality of image data, obtains a sum of the bit data, and outputs the sum of the bit data as a total count bit data value. The switch outputs a first pulse control signal corresponding to the total count bit data value. The gate driver generates a gate signal based on the first pulse control signal, and to output the gate signal to one of the gate lines.

Abstract: A method for transmitting spectrum information is provided. The method includes: sampling a first video of a scene by a first sampling device and sampling a spectrum video of a sampling point in the scene by a second sampling device, and processing the spectrum video to obtain a spectrum information of the sampling point; calculating estimated transmission ratio coefficients of the spectrum video according to color integral curves of the first sampling device; estimating a location of the sampling point in each frame of the first video; and transmitting the spectrum information of the sampling point to a plurality of scene points in the first video according to the estimated transmission ratio coefficients and the location of the sampling point in each frame of the spectrum video through a trilateral filtering algorithm.

Abstract: A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

Abstract: According to embodiments, a color signal processing circuit includes: an A/D converter configured to convert an analog television signal into a digital signal by using a clock; a color signal demodulation circuit configured to color-demodulate the television signal converted into the digital signal by the A/D converter; a clock generation section configured to generate the clock that is used by the A/D converter; and a frequency control section configured to control the clock frequency of the clock generation section on the basis of a color subcarrier frequency of a color signal included in the analog television signal and on the basis of the vertical synchronization signal frequency of the analog television signal.

Abstract: A method provides a bidirectional communication protocol for data communication between a first device and a second device. The method includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: Provided is a video signal processing device capable of judging the viability of phase locking at a PLL circuit and, in accordance with the judgment, automatically switching between the PLL circuit and a DLL circuit to use to generate a sampling clock of an input analog video signal, the device including an AD converter for AD converting an analog video signal, and a clock signal generating circuit for supplying a clock signal to the AD converter. The clock signal generating circuit includes: a PLL circuit for generating a first clock signal on the basis of a horizontal synchronous signal acquired from the analog video signal; a DLL circuit for generating a second clock signal on the basis of a composite synchronous signal acquired from the analog video signal; and a clock selecting portion for selecting and outputting either the first clock signal or the second clock signal on the basis of output of a PLL-dedicated phase comparator.

Abstract: In a receiver, a synchronization circuit (MIX2, OSC, C1, R1) provides a set of oscillator signals (OSI, OSQ) that are synchronized with a carrier of an amplitude-modulated signal. The set of oscillator signals (OSI, OSQ) comprises a quadrature oscillator signal (OSQ), which is substantially 90° phase shifted with respect to the carrier of the amplitude-modulated signal. A quadrature mixer (MIX2) mixes the quadrature oscillator signal (OSQ) with the amplitude-modulated signal so as to obtain a quadrature mixer output signal (MO2a). A phase-error corrector (PEC) adjusts the phase of the oscillator signals in response to a variation in the magnitude of an alternating current component (AC) in the quadrature mixer output signal (MO2a).

Abstract: A phase for an analog-to-digital converter sampling clock is determined. The analog-to-digital converter samples a video signal to generate pixel values. Differences of successive pixel values are compared to a threshold. The number of times the threshold is exceeded is counted for multiple phase values to create a phase profile. The threshold may be dynamic.

Abstract: A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

Abstract: A driver for driving a display panel and a method for reading/writing in a memory thereof and thin film transistor liquid crystal display (TFT-LCD) using the same are provided. The method of the present invention is a reading timing of memory which different than the prior reading timing of memory, so that, if using the method of the present invention in the driver even having only one memory, the tearing effect of the prior TFT-LCD can be solved and the whole power consumption thereof can also be reduced.

Abstract: An apparatus, method, system, and computer program and product, each capable of generating normalized image data from original image data are disclosed. To generate the normalized image data, feature information is extracted from the original image data, and predetermined image processing is applied to the original image data using the feature information.

Abstract: To provide an A/D converting circuit capable of improving an S/N ratio regardless of a color television system. An over-sampling A/D converting circuit according to an embodiment of the present invention includes: an A/D converter for over-sampling an analog video signal; a digital low-pass filter allowing passage of a signal component in a predetermined passing band out of the over-sampled signal; a down-sampling circuit for down-sampling the passed signal; and a color television system determining circuit for switching the passing band.

Abstract: A video signal processing circuit that uses a prescribed clock signal to process a digitized composite video signal. A clock generating means (2) generates the prescribed clock signal; a burst phase detecting means (3) detects color subcarrier phase information (p) in each line of the composite video signal; a phase difference calculation means (4) finds the phase difference between phase information (p) from the burst phase detecting means and a prescribed reference phase; a sampling phase conversion means (8) corrects the sampling phase of the composite video signal according to phase corrections (?b, ?t) obtained from the phase difference calculation means (4); a Y/C separation means (9) separates the luminance and chrominance signals from the composite video signal output from the sampling phase conversion means (8). Excellent two- or three-dimensional Y/C separation can be obtained regardless of the television broadcast system, even from a non-standard signal.

Abstract: We describe and claim an adaptive color burst phase correction system and method. The adaptive color burst phase correction system includes a signal detector to extract a color burst from a video signal, the color burst including a phase and an amplitude, an adaptive phase corrector to adjust the color burst phase responsive to corruption in the color burst, a Y/C separator to separate luminance and chrominance data from the video signal, responsive to the adjusted color burst phase, and a panel to display the luminance and chrominance data. The adaptive phase corrector includes a corruption detector to detect corruption in a color burst, a selector to select a phase correction value responsive to the detected corruption, and a phase adjuster to adjust a color burst phase responsive to the phase correction value.

Abstract: Digital broadcasting receiver, and method for compensating a color reproduction error therein, the digital broadcasting receiver including a channel decoder, a TP part for demultiplexing a TP stream from the channel decoder for being provided with a PCR (Program Clock Reference), and receiving a receiver side STC (System Time Clock), and providing a PCR jitter which is a difference between the PCR and an STC value, an STC compensating part for providing the STC value to the TP part from a system clock, and varying the system clock so that the PCR value and the STC value are identical, to generate a reference system clock in which the PCR jitter value becomes ‘0’, a decoder for receiving the reference system clock from the STC compensating part, and decoding a received picture, a display clock generator for providing a display clock generated by receiving the reference system clock as singular system clock, a video format and display processor for receiving the reference system clock and the display clock, and

Abstract: A software decoder for converting standard composite video to RGB color components without a phase-locked loop. Subcarrier phase recovery for each video line is accomplished by performing a single DFT computation on the color burst samples for the frequency closest to the subcarrier frequency. The recovered subcarrier phase is added for each line to the orthogonal subcarriers which are mixed with the modulated chrominance for decoding of color difference signals I and Q. Digital composite video capture and store circuitry may be used to buffer the acquisition of real-time video to the speed of a DSP used for software processing. Interpolation can be used in the processing of digital composite video to improve vertical line alignment. Multiple composite video formats, such as NTSC and PAL, can be decoded with minor modifications in the software decoder operation.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: A digital video encoder (16) receives a reference clock signal (REF_CLK27) for determining both a short term and a long term phase correction factor. A pulse detector (46) determines a number of sample clock (CLK324) time periods between the reference clock signal (REF_CLK27) and a clock signal (CLK27) that is derived from the data received by the digital video encoder (16). A phase increment generator (56) supplies an accumulator circuit (58) with a long term phase increment value based on the number of sample clocks and a TV_standard signal. A counter (60) and a phase look-up table (62) supply a short term increment value. The combined short term and long term increment values provide phase and frequency accuracy for the video subcarrier signal.

Abstract: A clock-recovery system is used to align a clock-phase with the RGB-signals. A frequency-synthesizing loop is applied for receiving a reference clock signal (CKREF) to generate a synthesized frequency. A fine-tuned frequency-synthesizing loop then receives a horizontal synchronization signal (HSYNC) to fine-tune the synthesized frequency into a fine-tuned synthesized frequency. A phase divider subdivides the fine-tuned synthesized frequency into a multiple phase segments for inputting to a multiplex controller. An analog sensor, receives and senses the RGB signals for generating encoded sensing data corresponding to voltage transitions of the RGB signals. A transition detector then applies the encoded sensing data for generating transition-detection data. A threshold triggering circuit compares the transition-detection data with a threshold data and triggering a RGB-phase data upon detecting the threshold data is exceeded by the transition detection data.

Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inc h to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment inc sc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by &Dgr;h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nonimal increment (nom_incsc) and a feed forwarded scaled version of &Dgr;h.

Abstract: The present invention overcomes the problem of image detail timing jitters in flat panel display devices by compensating for the phase difference between the dot clock derived by the Horizontal-sync signal and the display data. This is done by providing an apparatus and method for detecting the phase difference between the red, green and blue signal transitions and the dot clock signal that has been regenerated from the Horizontal sync signal. The detected phase difference is then applied, in a feedback fashion, to synchronize the dot clock phase with the signal transitions.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: A video/graphics overlay integrated circuit receives an analog composite video signal and a digital composite video signal and combines them in a predetermined format into an output composite video signal which is transmitted to a display device such as a television set. The digital video signal may be comprised of digital video, graphics data or a combination of digital video and graphics data. The digital video and graphics data are encoded by a digital encoder integrated circuit into a digital composite video signal. The digital composite video signal is coupled to the video/graphics overlay integrated circuit. An automatic phase correction circuit detects any phase difference between the burst signals of the analog composite video signal and the digital composite video signal.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: Receiving an instruction designating a frequency f by an MPU (1), a programmable clock generator (2) generates a dot clock D which has the frequency f. The dot clock D and a horizontal synchronizing signal H having a cycle T.sub.H are supplied to a counter (3). The counter (3) counts the number N of activations of the dot clock D during the cycle T.sub.H. The activation number N is supplied to a comparator (4), together with a predetermined number K which is designated by the MPU (1). The comparator (4) compares these numbers and supplies a comparison result C to the MPU (1). The MPU (1) updates the frequency f, in accordance with the comparison result C.

Abstract: A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value.

Abstract: A color subcarrier signal generator for use e.g, in a video converter measures the average error of the horizontal synchronizing signal frequency. The measured error is used as a compensator signal to control a direct digital synthesizer to generate a correct color subcarrier signal. The direct digital frequency synthesizer includes an address generator receiving the error signal and a look up table driven by the address generator.

Abstract: A digital color burst phase switch for determining phase shift of a color burst signal in a PAL video signal includes a phase selector for selecting either a first reference clock or a second reference clock in response to a PAL switch signal. A phase delay device delays the phase of either the first reference clock or the second reference clock selected by the phase selector to generate a third reference clock. A phase comparator compares the phase of the third reference clock to the phase of the color burst signal to generate a control signal. The control signal is integrated over substantially the entire color burst signal to generate an integration value. This integration value is compared to a threshold value in a threshold device to generate a correction signal.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: Chrominance signals of a digitized composite video signal are processed by including automatic phase control and automatic chroma control operations that use circuit elements that are concurrently available for both operations as well as for other signal processing operations. The automatic phase control operation calculates a phase error corresponding to a phase difference between a reference clock signal and a burst synchronization signal of the chrominance signal. The reference clock signal is generated in response to the phase error data, such that the phase error is minimized and the reference clock signal coincides with the burst synchronization signal. The automatic chroma control operation multiplies the chrominance signal by coefficient data corresponding to the difference between the chrominance signal and a reference value to generate a constant level chrominance signal.

Abstract: This invention is for a reference generator and demodulator for recovering information which has been phase, modulated on (or encoded on) a carrier. The inventive concepts described herein include a novel reference measurement circuit including a sampler and phase measurement circuit to measure the carrier reference's phase and/or frequency relative to a discrete time sampling phase and frequency, and a demodulator reference signal generator to generate properly phased reference signals for use by the phase demodulator circuit. The invention is particularly useful for decoding chroma difference signals of PAL and NTSC television video signals. It is suited to be implemented in digital form, operating on digitized signals thereby deriving all of the benefits normally expected of digital signal processing, including precision, freedom from drift and freedom from alignment. The invention is also particularly well suited to implementation by integrated circuit.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: A color signal reproducing circuit comprising a phase correction device receiving a gain-controlled composite color signal, detecting color burst signal in a composite color signal and correcting phase of the color burst signal by using a 3.58 MHz signal, first gate for receiving the gain-controlled composite color signal and passing only a color signal when a color burst pulse in the delayed horizontal synchronizing signal applied from the delay device is at a low level, and mixer for mixing the phase-corrected color burst signal and the color signal from the first gate to produce a phase-corrected composite color signal.

Abstract: A chrominance signal processing apparatus, where a chrominance subcarrier and a low-band converting chrominance subcarder are formed, uses a common oscillating signal to form the low-band converting chrominance subcarrier. The low-band converting chrominance signal processing apparatus includes an oscillator for producing an oscillating signal having a predetermined frequency, a chrominance subcarder generator receiving the oscillating signal to produce a chrominance subcarrier, a chrominance demodulator demodulating the chrominance signal incorporated in a composite video signal, a chrominance subcarrier generator receiving the oscillating signal to produce the low-band converting chrominance subcarrier, and a chrominance modulator receiving the chrominance signal demodulated in the chrominance demodulator and the low-band converting chrominance subcarrier to produce the low-band converting chrominance signal.

Abstract: A method and an apparatus for sampling a reference signal so as to generate an error signal indicative of a phase error between an actual sampling phase and a desired sampling phase. The desired sampling phase is displaceable from an optimum sampling phase, so as to facilitate the sampling of an NTSC color burst signal or to effect hue control during sampling of the modulated chroma sub-carrier. The reference signal is sampled at the frequency of said signal and a plurality of said samples are accumulated. After said samples have been accumulated, said accumulation is multiplied by the sine or by the cosine of the phase displacement angle between the optimum sampling phase and the derived sampling phase.

Abstract: A low range chroma signal reproduced from a recording medium is converted in the frequency by a frequency converter to obtain an original carrier chroma signal, then the carrier chroma signal is passed through a comb filter for removing a crosstalk and is output further through a phase shifting circuit, a burst signal of the phase shifting output is compared in the phase with a reference signal, the phase comparing output is smoothed by a filter, is then fed to a controlling terminal of a variable oscillator to control the oscillating frequency and is fed to a controlling terminal of the above mentioned phase shifting circuit to control the phase shifting amount. In this formation, a sub-APC loop including no comb filter is superimposed on a conventional APC loop and a response can be made until a high frequency. A color irregularity in a high frequency range (high range phase fluctuation of a carrier chroma signal) which has not been able to be removed can be reduced.