Abstract: Implementations generally relate to setting up a new television linked with an existing television. In some implementations, a method includes detecting, by a first television, a presence of a second television. The method further includes establishing communication with the second television. The method further includes sending a setup information request to the second television. The method further includes receiving setup information from the second television. The method further includes modifying one or more settings of the first television based at least in part on the setup information from the second television.

Abstract: A display driving device includes an interface, a clock generator, a sync signal generator and a timing controller. The interface receives a first vertical sync signal having a first vertical period, a first horizontal sync signal having a first horizontal period shorter than the first vertical period, and image data. The clock generator generates a clock signal having a predetermined frequency. The sync signal generator generates a second vertical sync signal using the first vertical sync signal, and generates a second horizontal sync signal having a second horizontal period different from the first horizontal period, using the clock signal, when a porch period included in the first vertical period is greater than a predetermined reference value. The timing controller drives a display panel based on the second vertical sync signal and the second horizontal sync signal.

Abstract: A video processing system for de-interlacing a video signal comprises a motion estimation block, a refinement motion estimation block, and a de-interlacer. The motion estimation block generates integer motion vectors for the video signal. The refinement motion estimation block generates fractional motion vectors as a function of the generated integer motion vectors and select frames of the video signal. The de-interlacer generates an output as a function of the generated fractional motion vectors and the selected frames of the video signal.

Abstract: An integrated circuit comprises a control input providing a connection to a capacitor. A delay circuit generates a delayed enable signal responsive to a provided enable signal. A second circuit performs a control function. A switching circuit responsive to the delayed enable signal connects the control input to the delay circuit in a first mode of operation and connects the control input to the second circuit in a second mode of operation.

Abstract: A monitoring apparatus includes a detection circuit, a filter circuit, an amplifying circuit, a regulation circuit, a delay and charging circuit, and a driving circuit. The detection circuit receives a video signal, and performs an operation to obtain an image signal from the video signal. The filter circuit obtains an average intensity of a luminance signal corresponding to the image signal. The delay and charging circuit charges an input capacitor when receiving a low level regulated signal from the amplifying circuit. The driving circuit activates an alarm when a charging voltage of the chargeable capacitor exceeds a predetermined value.

Abstract: Embodiments of the present invention may provide a clock and timing generation scheme for a video signal processor (e.g., a scaler), which enables fast switching between different input video standards without disturbing the output clock or timing. The scheme also may minimize the number of video frames that are dropped or repeated at the output. This may be achieved by locking the video's output timing to the input timing and also by utilizing a frame buffer to remove instantaneous discontinuities caused when an input is changed.

Abstract: An air-core stepping motor includes: a tubular stator including a yoke and a coil; a tubular rotor including a cylindrical magnet; and rotor support means for supporting the rotor rotatably with respect to the stator, the rotor support means including a sleeve fixed to the rotor, a holder fixed to the stator, and a ball held between the sleeve and the holder, the holder having a first holder member and a second holder member separated in a rotational-axial direction of the motor, the first holder member and the second holder member being assembled with the first holder member or the second holder member fitted to the sleeve, and being used thereafter with the first holder member or the second holder member disconnected from the sleeve.

Abstract: According to an aspect of the present invention, there is provided an electronic apparatus including: a detection unit configured to detect a start of a reproducing of a motion picture to be displayed on a display unit; a change unit configured to change a refresh rate of the display unit when the start of the reproducing of the motion picture is detected, the refresh rate being changed not by changing an operating frequency of the display unit, the refresh rate being changed by changing a blanking period, the blanking period being a period during which a drawing operation of a screen on the display unit is not performed; and a control unit configured to control the display unit to display the motion picture based on the changed refresh rate.

Abstract: An edge direction vector determination, which can be used for video interlaced-to-progressive conversion by motion-adaptive interpolation, has a coarse edge vector determination over a large search window followed by a fine edge vector determination over a small window plus confidence level assessment for field interpolation.

Abstract: A display apparatus comprises a user input unit; an image processor operating in one of a first image processing mode performing a first image processing operation and at least one second image processing operation on an input image signal, and a second image processing mode not performing at least one second image processing operation on the input image signal. A controller controls the image processor to operate in one of the first image processing mode and the second image processing mode, according to a manipulation of the user input unit. Accordingly, a display apparatus performs in an image processing mode in which an image processing time is reduced, according to a user's selection.

Abstract: Video signal processing systems and methods for detecting horizontal synchronization signals within video signals. Digital filtering methods are implemented for processing analog video signals to determine time varying characteristics of video signals to detect the starting and ending positions of horizontal synchronization pulses in a video signal with increased accuracy. In addition, adaptive methods are implemented for dynamically determining various video signal parameters over time, such as blanking level BL, threshold value (slice) level and synchronization level SL using information extracted from digitally filtered video signals.

Abstract: A video signal mode detector for automatically detecting and indicating the type of video signal being received in terms of its video signal characteristics, including horizontal line count and progressive or interlaced scanning.

Abstract: A clock generation apparatus is provided with a frequency phase error calculation circuit 120, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTO 121 on the basis of frequency information of a DTO 10 and phase error information from a phase comparator 7 and a digital LPF 8. Therefore, the clock generation apparatus can cope with a system that required plural clocks, and frequency spread is easily carried out by generating spread information by a frequency spread information generation circuit 90, and adding it in the DTO 121. As a result, interference to a video terminal from the clock can be reduced, and performance of a video terminal such as a television receiver can be exploited.

Abstract: A video synchronization signal detector for detecting occurrences of single and double frequency synchronization signal pulses present during a vertical synchronization interval.

Abstract: In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.

Abstract: A de-interlacing apparatus with a noise reduction/removal device. The noise reduction/removal device can include a motion prediction unit that predicts motion vectors between an image one period ahead of a previous image and a current image with respect to individual images which are sequentially inputted; a motion checking unit that applies the motion vectors predicted by the motion prediction unit to the image one period ahead of the previous image and two different images ahead of the current image in time, and checks whether the motion vectors are precise motion vectors; a motion compensation unit that compensates for motions in use of the motion vectors checked for preciseness thereof by the motion checking unit; and a noise removal unit that removes noise on images using the motion-compensated images by the motion compensation unit and the inputted images. Accordingly, the noise reduction/removal device can reduce or remove noise through simple procedures on noise-bearing images.

Abstract: An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the same period as that of the horizontal synchronous signal (HBK) of the digital video signal, the signal (EXT_H) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video; and means for generating a signal (EXT_F) having the same period as that of the frame synchronous signal (FRM) of the digital video signal, the signal (EXT_F) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video. The generated signals (EXT_F) and (EXT_H) are outputted as an external frame timing signal and an external horizontal timing signal of an external synchronous signal.

Abstract: To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured using the reference clock signal. The number of pixels disposed in the output frames is subsequently divided by the measured period. A fractional-N phase-locked loop circuit is adapted to multiply the result of the division with the frequency of the reference clock signal to generate the display clock signal. The display clock signal is also locked to the reference clock signal.

Abstract: A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1×N, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1×N, respectively, to output a first output clock signal with a frequency F1×N/P1 and a second output clock signal with a frequency F1×N/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.

Abstract: A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator provides programmability for the user to select line types for a frame to be displayed on a display. The line types defining rise and fall times, synchronization shapes, blanking levels and horizontal and vertical timings for providing a desired display format to different display types. A plurality of programmable parameters for pulse width, horizontal timing and voltage amplitude allow a user to define timing variations associated with a given line type. The display timing generator also includes a generic mode for allowing a programmer to select line types for particular groupings of lines.

Abstract: One embodiment of a method of frame detection may involve storing data indicative of a pulse duration and a number of successive occurrences of pulses having that pulse duration for each of several different pulse durations detected within a first field of a composite synchronization signal. This process may be repeated for one or more other fields of the composite synchronization signal. The data stored for each of the fields may be compared, and a frame signal may be generated dependent on an outcome of said comparing.

Abstract: A video decoder for decoding a composite video signal. The decoder includes an analog-to-digital converter (ADC), an input resampler, and a Y/C separator, all coupled in series. The ADC receives and digitizes the composite video signal to generate ADC samples. The input resampler receives and resamples the ADC samples with a first resampling signal to generate resampled video samples. The Y/C separator receives and separates the resampled video samples into luminance and chrominance components. The Y/C separator includes a delay element configured to receive the resampled video samples and provide a variable amount of delay. The variable amount of delay can be adjustable from line to line, and is typically based on an approximated duration of a video line.

Abstract: A method of measuring horizontal frequency, which comprises the steps of resetting an 8-bit counter, which counts horizontal synchronous pulses separated from a video signal, at a time point corresponding to an edge of a vertical synchronous signal separated from the video signal, causing a data latch portion, which is operative to latch count data obtained from a 16-bit counter operative to count clock pulses having a predetermined frequency, to latch the count data obtained from the 16-bit counter at a time point corresponding to an edge of a bit output signal obtained from the seventh bit position of the 8-bit counter, detecting a period which corresponds to 128 times a horizontal period of the video signal based on a difference between counted values represented respectively by a couple of count data latched successively by the data latch portion, and measuring horizontal frequency of the video signal by calculating the horizontal frequency on the strength of the period corresponding to 128 times the hori

Abstract: A signal processing method and apparatus in which a horizontal and/or vertical synchronizing signal related to a received video signal is monitored to determine if a relatively large change has occurred in the respective vertical and/or horizontal time period such that a change in video signal source may have occurred. Upon the detection of such a change, the operation of a phase lock loop (PLL) such as horizontal phase lock loop (HPLL) and/or vertical phase lock loop (VPLL) circuit is adapted as appropriate.

Abstract: The present invention is directed to a display device such as a liquid crystal display including: a horizontal clock counter and a vertical clock counter which count each clock signal every horizontal cycle and every vertical cycle for a valid data period of a data enable input signal; and an input signal generating section for holding a count value and generating an input signal in a driver IC and a driving circuit corresponding to a resolution of the display device which is obtained at that time by utilizing a count value held at a last time for a next horizontal cycle or a next vertical cycle, the display device being applicable to the driver IC and the driving circuit which can be used for the display device having various resolutions.

Abstract: The present invention is directed to a display device such as a liquid crystal display including: a horizontal clock counter and a vertical clock counter which count each clock signal every horizontal cycle and every vertical cycle for a valid data period of a data enable input signal; and an input signal generating section for holding a count value and generating an input signal in a driver IC and a driving circuit corresponding to a resolution of the display device which is obtained at that time by utilizing a count value held at a last time for a next horizontal cycle or a next vertical cycle, the display device being applicable to the driver IC and the driving circuit which can be used for the display device having various resolutions.

Abstract: A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator provides programmability for the user to select line types for a frame to be displayed on a display. The line types defining rise and fall times, synchronization shapes, blanking levels and horizontal and vertical timings for providing a desired display format to different display types. A plurality of programmable parameters for pulse width, horizontal timing and voltage amplitude allow a user to define timing variations associated with a given line type. The display timing generator also includes a generic mode for allowing a programmer to select line types for particular groupings of lines.

Abstract: A method and apparatus for converting a digital video signal, to a signal having a resolution that matches a display device, by using simple hardware alone. When a digital video signal is input together with a data enable (DE) signal and a dot clock (DCLK) signal, the number of clocks of the DCLK signal generated during an active period of the DE signal is counted and, based on the thus counted number of clocks, the resolution of the input video image is identified; then, based on the resolution thus identified, the pixel density of the input video signal is converted so as to form a video signal having a resolution that matches the display device. Alternatively, the resolution of the input video signal may be identified by counting the number of pulses of the DE signal generated during one vertical synchronization period.

Abstract: A horizontal synchronizing system, comprising: a source of a horizontal synchronizing signal; a source of first and second higher frequency horizontal drive signals; a phase detector for generating a first control voltage responsive to the horizontal synchronizing signal and the first horizontal drive signal; a source of a second control signal; and, a switch for selectively supplying the first control signal to the source of the drive signals for a phase-locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.

Abstract: A clock generating device for use in a digital video apparatus generates display clock matching an input video format. The clock generating device generates a clock of a frequency which is a predetermined number of times greater than the clock necessary for displaying video signals having a respectively different format, frequency-divides the generated clock, phase-locks the obtained stable frequency and supplies corresponding display clock. Video signals of a respectively different format can be displayed into a single display format, to thereby provide an effect of displaying a video signal without degeneration of a picture quality.

Abstract: A clock generator is provided which comprises a reference signal generator; a voltage controller/generator to generate a dot clock signal; a frequency divider to divide the frequency of the dot clock signal supplied from the voltage controller/generator; a phase comparator to detect a phase difference between the reference signal supplied from the reference signal generator and a signal supplied from the frequency divider; a frequency division ratio setter to set the frequency division ratio in the frequency divider to less than a quotient resulted from division of a total number of horizontal pixels in each of the video signals by a greatest common divisor of the total of horizontal pixels in the video signal having one format and total number of horizontal pixels in the video signal having the other format; and a frequency division ratio selector to select a frequency division ratio set by the frequency division ratio setter correspondingly to a format of a video signal.

Abstract: Device and method for processing a signal to a display, the device including a horizontal synchronizing signal detecting part for detecting a horizontal synchronizing signal from a picture signal, and a mode determining part for determining a mode of the picture signal by using a cyclic period of the horizontal synchronizing signal.

Abstract: A television signal receiver has: receiving means for receiving a television signal; detecting means for detecting a pulse of a video signal obtained from the receiving means; phase detecting means for detecting the phase of the pulse; video signal stabilizing means for conducting image-stabilization on the video signal obtained in the receiving means, in accordance with control information obtained from the phase detecting means and based on the reception disturbance state; and displaying means for displaying a video signal obtained from the video signal stabilizing means. According to this configuration, therefore, the video signal can be stabilized by the video signal stabilizing means, so that disturbance of an image can be reduced.

Abstract: The object of the invention is to provide a video switchover detection circuit that reduces the circuit scale and allows high-accuracy detection with a smaller-scale configuration.

Abstract: An apparatus displays pictures from sources having a plurality of horizontal frequencies. A scanning generator is operable at the plurality of frequencies and comprises an oscillator generating a signal. A divider with two selectable counts is coupled to the oscillator and divides the signal by a first count to generate a horizontal drive signal. A horizontal scanning amplifier generates a scanning signal responsive to the horizontal drive signal coupled thereto. A controller is coupled to the scanning amplifier and to the divider. In response to selecting another of the plurality of frequencies, the controller monitors the scanning signal and responsive to its presence inhibits selection of a second of the selectable counts. In the absence of the scanning signal the controller enables selection of the second of selectable counts and the divider generates a horizontal drive signal representative of the another one of the plurality of horizontal scanning frequencies.

Abstract: A technique for detecting three modes of video input signal and outputting a vertical sync signal based on the input signal. In a first mode, a standard video signal is received and a line counter is used to decode and output the vertical sync. In a second mode where a non-standard signal is received, line counter cannot be used, but a vertical sync is detected and output. In a third mode, no video input signal is received, yet a vertical sync is output in free-running mode so that a blank screen is displayed.

Abstract: A sync signal generating apparatus and method for video signal processor are disclosed comprising an image processor processing either an input digital television video signal or an input analog television video signal to display one of the signals; a display unit displaying an output signal of the image processor; a frame rate detector detecting a frame of the digital video signal and generating a frame rate signal; a display mode detector detecting whether an image to be currently displayed is a digital television image or an analog television image and generating a display mode signal; a clock generator generating a clock signal according to the display mode signal and the format signal to the image processor; a sync signal compensation unit generating a sync compensation signal based upon the display mode signal, the clock signal, and a vsync signal of the analog television video signal; and a sync signal generator resetting and compensating a sync signal based upon the sync compensation signal and the cl

Abstract: A sync frequency conversion circuit comprises first circuits for forming a write control signal changeable in synchronism with horizontal and vertical sync frequencies of an input video signal; a memory where the input video signal is written by the write control signal; a discriminator for discriminating the horizontal and vertical sync frequencies of the input video signal; a phase locked loop controlled by the discrimination result obtained from the discriminator, and serving to output a clock signal of a frequency changeable in accordance with such discrimination result; and second circuits for forming a read control signal from both of the discrimination output of the discriminator and the clock signal.

Abstract: A video display apparatus for pictures from broadcast sources having standard or high definition, which may also display computer generated images. To display this range of sources a horizontal frequency signal generator is selectably operable at a plurality of frequencies. The generator comprises an oscillator controlled for synchronized oscillation at a plurality of horizontal frequencies. A source of synchronizing pulses is coupled to an input of a phase detector which has another input coupled to the oscillator. The phase detector generates an output signal representative of a phase difference between the inputs. A processor is coupled to the phase detector for processing the output signal and generating a control signal for controlling the oscillator. The processor gain is controlled responsive to selected ones of the plurality of frequencies.

Abstract: A signal treatment circuit treats an input signal containing line sync pulses used for displaying data on a screen. The circuit contains a phase locked loop to control horizontal sweeping according to active edges of line sync pulses, and a filter circuit that filters equalizing signals from the input signals and provides a filtered input signal to the phase locked loop.

Abstract: A multi-standard television receiver in accordance with the present invention includes a plurality of video signal processing blocks having tristate functions at their output terminals, at least one memory block used in common for a plurality of video signal processing blocks and a video signal processing selection means for selecting one of the video signal processing blocks and independently controlling the output terminals of the video signal processing blocks using elements having a tristate function and can reduce power consumption by working only a selected video signal processing block and stopping the other video signal processing blocks. Further, using elements having a tristate function, possibility of element breakdown at selection and control of the elements can be removed.

Abstract: A synchronous control device is disclosed which is capable of obtaining stable synchronization regardless of the kind of image source even when the automatic synchronous control circuit cannot operate in the normal manner.The device includes a phase comparator, an integrator, a horizontal oscillation circuit, and a horizontal synchronous control circuit composed of a frequency measuring section consisting of a digital frequency measuring circuit, etc. and a control section consisting of a frequency determining circuit, an oscillation frequency control circuit, etc. The frequency measuring section measures the input horizontal synchronizing frequency and transfers it to the control section as digital data, and the control section determines the true value of the input synchronizing frequency by the frequency determining circuit while monitoring the transition of the frequency data per unit time.

Abstract: Disclosed is a synchronization circuit that can be applied in the field of monitors and, especially, in the field of television receivers. The disclosed circuit comprises circuits to analyse and correct the horizontal and vertical synchronization signals in order to neutralize the effect of the signalling present in the horizontal synchronization signal on the working of a phase-locked loop.

Abstract: A counter control circuit of a counter for measuring a pulse period of a video synchronization signal includes a main control unit having a synchronization signal input Sync, and a control signal producing unit including a stop signal generator, a latch signal generator, and a start signal generator. The outputs of the stop, latch and start signal generators are supplied to the counter for controlling the counter to count clock pulses fed from a clock generator in response to receipt of a start signal and output a count value in response to receipt of a latch signal. The main control unit produces sequential control signals during the input of the video synchronization signal differentiated by the clock pulses. The counter control circuit allows the counter to measure a pulse period of an input synchronization signal in a stable state that results in an accurate count value, since the count operation is first stopped and the count value is latched by the clock signal.

Abstract: A sync signal processing device for a combined video appliance capable of directly processing a personal computer (PC) signal through a television (TV) receiver circuit to achieve the horizontal and vertical driving and deflection. The device can prevent the vertical trembling phenomena of the displayed picture and on-screen display by compensating for the sync frequency difference between the PC signal and the TV signal. According to the devices either a TV sync signal or a PC sync signal is selected in accordance with a selected TV/PC mode after the PC sync signal is frequency-converted and the selected PC sync signal is processed through the TV sync signal processing circuit. Either the horizontal driving pulse signal form the TV sync signal processing circuit or the horizontal driving pulse signal produced from a separate horizontal oscillation circuit is selected and outputted to a horizontal output circuit in accordance with the selected TV/PC mode.

Abstract: In a video display operable at multiple horizontal scanning frequencies, a synchronized high voltage generator is substantially undisturbed during synchronizing source selection or interruption. The generator comprises a controlled oscillator generating a drive signal. A source of pulses synchronizes the controlled oscillator and has a plurality of scanning frequencies. A high voltage generator is coupled to the drive signal and generates a display energizing supply. The scanning frequencies occur in two frequency bands, and when synchronized the oscillator generates the drive signal having a frequency only in a higher frequency band of the two frequency bands. In a further inventive arrangement a high voltage generator for a video display is operable at a plurality of horizontal scanning frequencies and is controlled such that the high voltage supply remains substantially constant during an interruption of horizontal scanning pulses from the source.

Abstract: A semi-wide view display method and device using the same are provided with a semi-wide view function for arbitrarily converting an aspect ratio of a screen in a television. The method includes the steps of setting a display mode according to a user-selected aspect ratio of a television screen; receiving vertical and horizontal blanking pulses, controlling the width of the blanking pulse according to the display mode setting, and outputting the result; generating a television signal which is displayed on the screen and a blanking signal which is not displayed on the screen by inputting the generated blanking pulse; and displaying the television and the blanking signal to thereby control vertical/horizontal over-scanning and vertically lengthen a blanking period, in order to convert the aspect ratio of the displayed image.

Abstract: A synchronizing frequency of red (R), green (G) and blue (B) video signals is detected by a frequency detector. The resolution of the RGB video signals is calculated by a calculator. When the resolution of the RGB video signals is close to the resolution of a cathode-ray-tube (CRT), a high level signal is generated as a control signal from a control signal generator. When the high level signal is generated from the generator, the video bandwidth of the RGB video signals is limited by a video bandwidth limiting circuit to adapt the RGB video signal to characteristics of the CRT.

Abstract: Vertical and horizontal sync signals are separated from an NTSC signal inputted from an outside by an external input circuit and a luminance signal (Y) and chrominance signals (B-Y, R-Y) are extracted and converted into RGB data. External RGB data and RGB data formed by a software are processed and the resultant data is supplied to an output converting circuit. The RGB data is converted into analog signals of the luminance signal and chrominance signals of a television signal by using individual system clock signals and outputted. A clock generating circuit generates two kinds of dot clocks which are used for the output converting circuit. The dot clock which is generated from the clock generating circuit and is used for conversion of the luminance signal is phase matched so as to follow a jitter of a horizontal sync signal (H) separated by an external video input circuit.

Abstract: Disclosed is a horizontal oscillation circuit for a monitor performing a stable oscillation even at the start input such as a power input or a mode change. The horizontal oscillation circuit for a monitor includes an operation voltage delaying part for delaying a time period for an operating voltage to reach a voltage level and for outputting a delayed operating voltage, and a horizontal oscillator for inputting the voltage corresponding to the operating mode, the horizontal synchronizing signal and the delayed operating voltage and for outputting a stable oscillation voltage corrresponding to the operating mode. With an output of a stable oscillation voltage from the horizontal oscillation circuit, the horizontal output circuit of a monitor can be protected from being damaged by heat and a stable display can be obtained even at the start input such as a power input or a mode change.