Abstract: A method and apparatus for detecting copy protection included in an input video signal is described. Two types of copy protection are particularly addressed, including techniques that imbed copy protection pulses and copy protection phase flips in the video signal. A method for preserving copy protection is also presented, where the input video signal is first examined to determine if copy protection has been included in the input video signal. The input video signal then converted to component video data, which removes any copy protection present. An output video signal is then generated from the component video data, and when it was determined that the input video signal includes copy protection, the copy protection is recreated in the output video signal.

Abstract: A video formatter reformats progressive video using a film-based video film rate and a display refresh rate to determine a frame OFF period for a progressive video sequence. The video formatter inserts at least one black frame into the progressive video sequence to approximate the frame OFF period. Typically, the film rate is 24 frames per second (industry standard) and, thus, the display refresh rate can be a multiple of the frame rate (e.g., 96 Hz, 120 Hz, 240 Hz, etc.). Progressive video replicates a single frame of a film several times (“a progressive video sequence”) depending on a display's refresh rate. The black frame(s) is/are substituted at the end of this sequence instead of displaying the same image throughout for a single film frame.

Abstract: The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A method and apparatus for detecting copy protection included in an input video signal is described. Two types of copy protection are particularly addressed, including techniques that imbed copy protection pulses and copy protection phase flips in the video signal. A method for preserving copy protection is also presented, where the input video signal is first examined to determine if copy protection has been included in the input video signal. The input video signal then converted to component video data, which removes any copy protection present. An output video signal is then generated from the component video data, and when it was determined that the input video signal includes copy protection, the copy protection is recreated in the output video signal.

Abstract: The present invention is directed to a display device such as a liquid crystal display including: a horizontal clock counter and a vertical clock counter which count each clock signal every horizontal cycle and every vertical cycle for a valid data period of a data enable input signal; and an input signal generating section for holding a count value and generating an input signal in a driver IC and a driving circuit corresponding to a resolution of the display device which is obtained at that time by utilizing a count value held at a last time for a next horizontal cycle or a next vertical cycle, the display device being applicable to the driver IC and the driving circuit which can be used for the display device having various resolutions.

Abstract: A method and system for including non-graphic data in an analog video output signal of a set-top box. Graphics data is generated from and represents non-graphic data using software or firmware that is executed by a processor, system-on-a-chip integrated circuit, or some other component of the set-top box. The graphics data is alpha blended with video data that is extracted from a digital television signal. This alpha blending results in an alpha blended digital video signal. The alpha blended digital video signal is converted into the analog video output signal by a digital encoder function, which is preferably included in the system-on-a-chip integrated circuit. The alpha blending is also preferably performed by the alpha blending function of the system-on-a-chip integrated circuit. The analog video output signal can then be input into an analog video recorder.

Abstract: The present invention is directed to a display device such as a liquid crystal display including: a horizontal clock counter and a vertical clock counter which count each clock signal every horizontal cycle and every vertical cycle for a valid data period of a data enable input signal; and an input signal generating section for holding a count value and generating an input signal in a driver IC and a driving circuit corresponding to a resolution of the display device which is obtained at that time by utilizing a count value held at a last time for a next horizontal cycle or a next vertical cycle, the display device being applicable to the driver IC and the driving circuit which can be used for the display device having various resolutions.

Abstract: A horizontal display positioning circuit for a CRT-type display device includes a microcomputer, a horizontal deflection circuit, and a horizontal positioning control circuit configured between the microcomputer and the horizontal deflection circuit, for outputting a horizontal sync signal having a predetermined duty width. The microcomputer, which receives synchronizing signals from a host computer and discriminates a video mode according to the received synchronizing signals, outputs a horizontal sync signal having a given polarity. The horizontal deflection circuit includes a horizontal oscillating circuit which generates a horizontal deflection signal, a horizontal drive circuit which performs waveform correction of the generated horizontal deflection signal and drives an output transistor, and a horizontal output circuit which includes the output transistor and produces a sawtooth current through a deflection coil based on the operation of the output transistor.

Abstract: A technique for detecting three modes of video input signal and outputting a vertical sync signal based on the input signal. In a first mode, a standard video signal is received and a line counter is used to decode and output the vertical sync. In a second mode where a non-standard signal is received, line counter cannot be used, but a vertical sync is detected and output. In a third mode, no video input signal is received, yet a vertical sync is output in free-running mode so that a blank screen is displayed.

Abstract: A display mode selection method for selecting one display mode with respect to an input display signal from a table which defines a horizontal scanning frequency, a vertical scanning frequency and a resolution for a plurality of display modes, includes the steps of storing the plurality of display modes in the table in a plurality of blocks so that display modes having mutually overlapping tolerable ranges of the horizontal scanning frequency are included in the same block, obtaining a block number with respect to the input display signal by substituting a horizontal scanning frequency of the input display signal into a calculation formula which describes the block number of the blocks as a function of the horizontal scanning frequency, and selecting a display mode with respect to the input display signal from a display mode of the obtained block number by making a reference to the table.

Abstract: An improved high-performance vertical sync separator which can reliably operate during high frequency and non-standard video signal conditions and that utilizes a device-independent methodology. The synch separator includes a signal separator circuit having an input port for receiving a composite signal. A measuring device connected to the input port measures a first and second characteristic of the composite signal. A processor receives and compares the first and second characteristics, and recovers a vertical sync signal from the composite signal.

Abstract: A semi-wide view display method and device using the same are provided with a semi-wide view function for arbitrarily converting an aspect ratio of a screen in a television. The method includes the steps of setting a display mode according to a user-selected aspect ratio of a television screen; receiving vertical and horizontal blanking pulses, controlling the width of the blanking pulse according to the display mode setting, and outputting the result; generating a television signal which is displayed on the screen and a blanking signal which is not displayed on the screen by inputting the generated blanking pulse; and displaying the television and the blanking signal to thereby control vertical/horizontal over-scanning and vertically lengthen a blanking period, in order to convert the aspect ratio of the displayed image.

Abstract: In a synchronization stabilizing circuit and a television signal receiver, the follow-up range (TX) of the synchronizing signal (SH) is changed based on the judged result (J1) that it is judged whether or not the synchronizing signal (SH) itself exists and the judged result (J2) that it is judged whether or not the input signal exists in a follow-up range (TX), so that the signal can be synchronized easily in a short period even if the frequency of the synchronizing signal (SH) is deviated.

Abstract: An arrangement for stabilizing a horizontal synchronization signal, serving as an input signal for a phase-locked loop (PLL) for generating a clock signal, by separating the horizontal synchronization signal from a composite synchronization signal including both horizontal and vertical synchronization signals. A horizontal synchronization gate signal is generated for outputting a pulse signal approximately in phase with the horizontal synchronization signal and having at least the pulse width of the horizontal synchronization signal in accordance with the composite synchronization signal and a clock pulse signal having a predetermined frequency. The horizontal synchronization signal is retrieved from the composite synchronization signal in accordance with a logical product when matching the polarity of the horizontal synchronization gate signal with the polarity of the composite synchronization signal.

Abstract: The present invention relates to a synchronizing signal generation circuit equipped with a PLL circuit. A pulse signal having a time constant that is broader than the clock width of a horizontal synchronizing signal included within synchronizing signals and that moreover contains steady-state phase error of the PLL circuit is generated and inputted to a phase comparison inhibiting circuit by way of a signal conversion circuit. The logic level of the pulse signal is then varied for the active interval and the inactive interval of the vertical synchronizing signal, phase comparison of the horizontal synchronizing signal and the reproduced horizontal synchronizing signal being inhibited during the active interval. The reproduced horizontal synchronizing signal is generated based on the output of two frequency dividers.

Abstract: A composite synchronization extraction circuit is particularly suited for receiving composite video signals containing closed captioning data in raster scan line 21 by means of a signal CMOS integrated circuit device. A dual mode voltage clamp is realized in CMOS technology. The clamp includes temperature compensated current sources in the form of complementary current mirrors through which a clamped composite synchronization node of is charged and discharged, the output of which controls a transistor for charging the composite synchronization node. Detected pulse amplitude is set by slicing the incoming pulse at the back porch level and then doubling the amplitude with an amplifier and comparing that level with the back porch level as derived from a sample-and-hold device. The slice voltage level is maintained without an off-chip capacitor by an analog-digital-analog conversion process.