Abstract: An apparatus for driving a display panel comprises a receiving circuit of a TV broadcasting wave. The writing and reading operations of the pixel data to/from the memory are performed synchronously with the self-advancing clock signal, thereby preventing a disturbance of a display image upon channel switching. The display driving apparatus according to another aspect of the invention has two frame memories to alternately store pixel data and a memory control apparatus to control the writing and reading operations to/from the frame memories which makes a scanning line interpolation processing apparatus constructed by a memory, an arithmetic operating circuit, and the like unnecessary. Furthermore, the driving apparatus can be altered to allocate storage in a memory for pixels which are to be displayed in one picture plane. This storage allocation allows a motion image and the still image to be simultaneously displayed.

Abstract: A method and device is described herein for displaying a television picture comprised of several standard aspect ratio images on widescreen and standard aspect ratio video monitors. A widescreen image including several smaller aspect ratio images are assembled and broadcast. A receiver with a widescreen monitor display can display the entire widescreen image. A receiver with a conventional aspect ratio monitor display can display a combination of the smaller aspect ratio images. The device includes a frame store for storing image information, image configuration logic for determining a configuration of image information, and frame address logic to write image information to frame store with a configuration according to image configuration logic.

Abstract: A method and device for providing instant replay in an MPEG video decoder. The method and device provides non-MPEG frame tags for correlation of the frames in the decompressed domain to the frames in the compressed domain.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: A video signal capturing apparatus has a converter unit that converts an input video signal into digital video data and a digital video data writing control unit that controls writing of the digital video data converted by the converter unit in a memory. Thereby, digital video data for an external processing apparatus that uses the digital video data stored in the memory is captured. A separator unit separates a horizontal synchronizing signal from the input video signal. Based on the horizontal synchronizing signal thereby separated, a writing instructing unit instructs that the portion of the digital video data corresponding to an image information transmission be written in the memory. Thereby storage of unnecessary data is avoided in contrast with an apparatus that captures all the data including synchronizing signals.

Abstract: A video signal processing circuit uses a buffer memory for reducing or expanding video signals in the generation of child images to be displayed within a display window. Image size data, stored in a header within the buffer memory, and a reduced video signal are prevented from representing different image reduction ratios which might otherwise occur when the reduction ratio is changed. At the time of changing the reduction ratio, image size data SIZ are calculated from a write enable signal based on reduction ratio data K, for a one-field period just after the change by an input video clock generator 22. The calculated image size data are written to a header together with a reduced video signal in a field memory 2, and a flag bit SP indicating the change in the reduction ratio is also written to the header for the one-field period just after the change.

Abstract: A display device includes a plurality of input timing control circuits for generating a plurality of first clock signals in synchronization with a corresponding plurality of horizontal synchronization signals received via multiple channels, an output timing control circuit coupled to receive the first clock signals for generating a second clock signal, and a plurality of video memory circuits for storing a plurality of digital video data received via the multiple channels. The writing operations of the video memory circuits are respectively controlled by the plurality of input timing control circuits and the reading operation of each of the video memory circuits is controlled by the output timing control circuit. The display device further includes an output buffer memory circuit coupled to the video memory circuits for storing the plurality of digital video data from the video memory circuits.

Abstract: The invention relates to an architecture making it possible to store and transfer still or moving video images, the said architecture comprising at least one input circuit (E1, E2, . . . , En) allowing access for data intended to make up video images, a memory area (M) making it possible to store video images, at least one video image output circuit (S1, S2, . . . , Sj) and a video bus (B) intended to provide for the transfer of information between the memory area (M), the input circuit and the output circuit, characterized in that the memory area (M) is a general-purpose memory and in that the video bus (B) has a width L greater than or equal to the width of the memory area (M).The general-purpose memory is operated in a centralized manner by a control circuit (CTRL).The invention applies to computer platforms dedicated to the transfer of Broadcast quality images or alternatively to video devices for built-up image animation.

Abstract: A method and apparatus for transmitting video over telephone lines is provided. FM data is produced representative of a video picture to be transmitted and synchronization data concerning the transmitted picture is also produced. The FM data and the synchronization data are transmitted via telephone lines to a receiver. A pair of memories is provided in the receiver. The receiver uses the synchronization data to coordinate the storage and display of the received pictures. One memory displays the picture while the other memory is being loaded. The memories are toggled so that the memory from which the previously stored data is displayed becomes the memory being loaded and the memory being loaded becomes the memory from which previously stored data is displayed. Alternatively, one memory is a load memory while the other memory is a display memory. After the incoming picture is stored in the load memory, it is transferred to the display memory.

Abstract: A system and method for generating the display of multiple screen digital television includes a size controller to adjust the image size by cutting or enlarging the outer portion of the image before the image is reduced to fit the size of a selected PIP window. The size controller also adjusts the image sizes for the main display window if the input image data format does not have a standard image size. The size controller facilitates the processing of image format with special or unconventional image sizes.

Abstract: An FM teletext broadcast receiver having a page memory function of holding designed specific page data upon completion of an FM teletext broadcast program includes a data storage section. The data storage section includes a data storage area for storing received data, a state bit table for indicating the use state of each block in the data storage area, an information table for managing program data stored in the data storage area, a page memory state bit table in which a bit data value indicating whether page data in each block in the data storage area is held upon completion of a program is set and held, and a page memory information table in which table data of predetermined management items for each block in which the page data is held/set is stored. The data storage area is shared between a program data storage area and a page memory storage area to attain flexible memory allocation.

Abstract: A video display monitor apparatus has a composite input circuit, which receives either a composite TV signal or an additional composite television signal supplied from a video player such as a video cassette recorder, separates horizontal and vertical synchronizing signals, Y and C video signals from the received composite television signal, and transforms the separated Y and C video signals into analog R, G and B video signals. Two video processing circuits and a timing control circuit are provided for the display monitor apparatus. The timing control circuit performs timing control for the video processing circuits, in response to the synchronizing signals and additional horizontal and vertical synchronizing signals applied from a personal computer. The viewing area of the image formed by video signals from the computer is disposed within the viewing area of the image formed by the TV video signals in the form of picture-in-picture.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: An input processing section reduces the content of an input video signal according to reduction ratio data, and the reduced video signal is stored in field memories. A display processing section reads a reduced video signal from the field memories to execute window display processing thereto according to video size SIZ data and video position data (X, Y). In this event, an input video clock generator, controlling a writing operation to the field memories, computes video size SIZ data from the reduction ratio data, and writes the SIZ data as a header, along with the reduced video signal, into the field memories via the input processing section. The SIZ data is read to be output to the display processing section and a display video clock generator for controlling reading.

Abstract: An on-screen display (OSD) vertical blanking signal selection circuit for a display apparatus comprises: a microcomputer for generating a reference oscillating signal in response to vertical and horizontal synchronous signals from a video card; an HV processor for generating a flyback transformer (FBT) drive signal and horizontal and vertical drive signals in response to the reference oscillating signal from the microcomputer and the horizontal and vertical synchronous signals from the video card; an FBT for generating a high voltage in response to the FBT drive signal from the HV processor and for supplying the generated high voltage to a cathode ray tube; a horizontal deflection circuit for controlling horizontal deflection of electron beams in a cathode ray tube in response to the horizontal drive signal from the HV processor; a vertical deflection circuit for controlling a vertical deflection of the electron beams in the cathode ray tube in response to the vertical drive signal from the HV processor; and

Abstract: A system and method for altering the appearance of interference in a video signal caused by spurious interference generated by repeated high speed digital memory write operations affecting video processing in analog circuitry in thereceiver. In one particular embodiment, a picture-in-picture television receiver is provided wherein both the main and sub-pictures are processed on a single IC including analog processing circuitry, as well as a small picture memory array to which small picture video samples are repeatedly being written. The visibility of spurious interference in the picture is reduced by periodically altering the clock timing during the repetitive high speed writing operation to redistribute the interference so as to be less noticeable to the television viewer.

Abstract: An input video signal is reduced according to size reduction ratio data K in an input processing section and written into alternate field memories. The written reduced video signal is alternately read from the field memories in a display processing section and processed for window displaying. Video reduction control sections are provided on the respective input and display sides, so that various signals, such as RHOLD, ADCANS, RACK signals, etc., are exchanged therebetween. When a size reduction ratio data K is changed, on the display side a read memory is fixed on a first field memory and size data is fixed, while on the write side video data is written into a second field memory, based on the new reduction ratio. After updating the size data on the display side, video data is read from the second field memory at the new reduction ratio.

Abstract: A device for displaying image signals received from a plurality of monitoring cameras are displayed on sub-screens, and a method therefor. First, a sub-screen displaying mode is set, and the number of sub-screens to be divided is input. When the number of channels of input image signals is greater than that of sub-screens, the numbers of channels to be displayed in a continuous mode and the locations of sub-screens to be operated in switching mode are input. The channels of the continuous mode are displayed continuously on corresponding sub-screens, and other channels alternately displayed on the rest sub-screens.

Abstract: Pattern data is generated in accordance with horizontal and vertical synchronizing components of a video signal. The pattern data and the video signal are stored in a memory. The video signal is written in an effective image period, while pattern data is written in other periods. Write and read addresses for the memory are generated in accordance with the horizontal and vertical synchronizing components of the video signal. Thus, pattern data is written over the video signal corresponding to the position at which display is required. Whether the output read from the memory is a video signal or pattern data is discriminated by a signal discrimination circuit in accordance with the read address. Pattern data and the video signal are individually signal-processed. In accordance with a result of the discrimination performed by the signal discrimination circuit, the output from a pattern data processor and the output from a video signal processor are switched and displayed by a monitor.

Abstract: A slow Phase Locked Loop (PLL) is utilized to prevent an abrupt change to a video display containing multiple images, when the source of the synchronization is changed. Such displays include Picture in Picture (PIP) television systems and computer displays. By appropriate buffering and memory management, visual disruptions can be minimized by slowly synchronizing the display synchronization signals to the new synchronization source. The slow synchronization also produces a less disruptive visual image when the source, or channel, of a single image display is changed, and allows for smooth visual transitions on displays having inertial elements, such as color wheels.

Abstract: An integrated circuit for manipulating digitized video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, reordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device has memory for temporarily storing sequences to be manipulated and data read from the external memory; a circuit for decoding information about the manipulations to be performed; address circuitry for transferring the data between the device and the external memory; circuitry for configuring the device by means of a remote processing unit; circuitry for processing the data read from the external memory; and circuitry for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

Abstract: The invention provides an electrical program guide system and method by which a desired program can be rapidly selected directly from among a large number of programs with certainty. A program selection screen as a multi-screen is formed from nine reduced screens reduced to one third in the horizontal and vertical directions from screens of programs broadcast on different broadcasting channels. A plurality of such program selection screens are transmitted to a reception side. On the reception side, the program selection screens are stored into a virtual frame memory so that reduced screens of them may make a single virtual screen. From among the reduced screens of the virtual frame, desired 3.times.3 reduced screens are read out and displayed on a multi-screen of full motion. A viewer finds and directly selects a desired program from within the 3.times.3 reduced screens of full motion displayed as the multi-screen.

Abstract: A video signal outputting apparatus includes an A/D converter, and video signals Y1-1 and Y3-1 outputted from the A/D converter are written into areas C1 and C3 of a VRAM, and therefore, images according to the video signals are displayed on a monitor. Then, video signals Y1-2 and Y3-2 are outputted from the A/D converter, and written into an area C5 of a further VRAM and the area C1 of the VRAM, respectively. Images according to the video signals Y1-2 and Y3-1 are displayed on the monitor at a timing that writing of the video signal Y1-2 is finished, and images according to the video signals Y1-2 and Y3-2 are displayed at a timing that writing of the video signal Y3-2 is finished.

Abstract: A digital satellite broadcast receiver having a simultaneous multi-channel search function is disclosed, in which the currently broadcasting programs on the respective channels are displayed onto a plurality of divided windows respectively through one transponder, thereby providing a convenience to the channel search of the users. The number of the channels is detected by utilizing the program specific information (PSI) of the transport stream which is transmitted from a satellite. The screen is divided into as many as the number of the channels so as to set windows. Then the coding type of the picture header which is contained in the transport stream is read to detect the I picture. Then the I pictures of the relevant channels are displayed onto the respective divided windows. Then if the user selects one channel from among the displayed channels, then the selected picture is displayed in the original size.

Abstract: In a television receiver and a display method thereof, the television receiver includes a video signal processing circuit for receiving a video signal, converting the signal into a video display signal, and outputting the signal therefrom; a video signal storage circuit for receiving the video display signal from the processing circuit, recording the signal for a predetermined period of time, writing the video display signal in an overwriting manner after lapse of the predetermined period of time, and repeating the recording operation at an interval of the predetermined period of time; a switch circuit for receiving the video display signals from the video signal processing and storage circuits, combining the signals with each other in a switching fashion, and outputting a resultant signal therefrom; a control circuit for controlling the video signal storage circuit and switch circuit in response to an indication signal supplied from an external device, combining with each other the video display signals from

Abstract: Two MPEG-encoded digital data streams are simultaneously decoded in a digital entertainment terminal to provide Picture-in-Picture (PIP) and Picture-on-Picture (POP) capabilities for a conventional television. A primary MPEG-encoded data stream is decoded using a digital video processor optimized for MPEG2 decoding or a dedicated MPEG2 decoder system. A secondary MPEG-encoded data stream is partially processed by filtering the B frames of the secondary MPEG-encoded data stream and using the corresponding I and P frames in a partial decoding arrangement to obtain decompressed video data providing a limited-resolution representation of a second program. Partial decoding may also be performed using only I frames. The partial decoding may be implemented through execution of software by a general-purpose microprocessor. Alternatively, the media processor may perform the partial decoding during the idle intervals of the dedicated media processor.

Abstract: An implementation efficient video decoder suitable for use as a picture in picture decoder is described. In one embodiment, the video decoder receives primary and secondary bitstreams with the secondary bitstream including the video data intended to be displayed as inset pictures. The decoder uses many of the same circuit components on a time shared basis to decode both the main and inset pictures reducing the amount of circuitry required to implement the decoder. In one embodiment a preparser discards the majority of DCT coefficients in the secondary bitstream and the remaining data is variable length decoded and then variable length encoded using a non-MPEG compliant coding scheme prior to storing the inset picture data in a coded data buffer. Re-encoding of the selected inset picture data in this manner greatly reduces data storage requirements and simplifies the circuitry required to subsequently decode the inset picture data.

Abstract: An image displaying apparatus includes a line memory from which each line period segment of a first video signal is read during a half line period to produce a first half line period video signal segment, a frame memory from which each of line period segments contained in each frame period portion of a second video signal is read during a half line period, with a time reference set up in accordance with a synchronous signal contained in the first video signal, to produce a second half line period video signal segment, a signal selector operative to extract alternately the first and second half line period video signal segments to form a synthesized video signal for display, a dual image display portion for displaying images forming double window pictures in response to the synthesized video signal for display, a first timing signal generator for supplying the frame memory with a writing control signal, and a second timing signal generator for supplying the frame memory with a reading control signal, wherein t

Abstract: An apparatus and method for centralized processing of PIP images from a plurality of digital video sources includes a centralized processing device having a plurality of service drivers for outputting digital video data representing full screen images, and samplers for selectively sampling the data from the service drivers to form reduced screen images. A PIP bus channels the sampled data for access by various users. The sample data is selectively stored in buffers and is output to a display device when triggered by input/output triggers. The triggered output data representing reduced screen images is then combined by a video switch to form picture-in-picture images.

Abstract: A picture pause selecting apparatus and method for a double-wide television for pausing a picture selected by a user. The apparatus operates according to the user selection regardless of the picture mode and regardless of which picture the user selects in the double-picture mode. The apparatus has first and second memories for storing each frame of the left and right picture signals. First and second switches selectively output paused signals and left and right picture signals from first and second memories.

Abstract: A video display apparatus comprising a memory of fields for plural images, a device for judging whether even-number field or odd-number field, and a frame synchronizing device for reading and selecting fields, in which, if the input has one type of field only, these plural images are displayed simultaneously while keeping correct interlacing.

Abstract: Disclosed is a method and apparatus for processing two analog composite video signals to be displayed to a human observer. The system includes at least a first and a second video source for generating first and second analog composite video signals respectively, and a selector coupled to the first and second video sources. The selector is operative to supply either the first or second analog composite video signal to one input of a video processor and independently and simultaneously supply either the first or second analog composite video signal to a second input of the video processor. The video processor is operative under control of a CPU to generate an output analog composite video signal comprised of a portion of the analog composite video signal supplied to the video processor's first input and a portion of the analog composite video signal supplied to the video processor's second input.

Abstract: The OSD includes a plurality of holding circuits for outputting to a mixing circuit pixel data for characters or patterns synchronously with a horizontal synchronization signal, wherein the pixel data for the characters or patterns to be displayed are supplied to the holding circuits by a memory through a plurality of channels, the number of which is equal to the number of the holding circuits, so that a display signal for displaying the pixel data in a plurality of display areas is generated by the mixing circuit.

Abstract: Allows a video broadcast viewer to pause at anytime while viewing a program, and upon returning to be able to view the intervening segment. The video received during the pause period is stored and available for recall upon user command. The storage medium is circular in so much that the memory, upon becoming filled to capacity continues to write incoming information data over the previously stored data. The storage circuits employs a sequential access storage device and/or a direct access storage device. The storage circuit has a high speed memory input buffer and a high speed memory output buffer to account for the relatively long READ and WRITE access times of the storage device employed. At the end of the pause period, the user can view the stored video. The user has a choice between catching up to the regular broadcast or watching the remaining program video in a delay mode.

Abstract: An apparatus for generating a plurality of picture-in-picture/picture-out-picture (PIP/POP) screens, capable of achieving a fast tuning for a plurality of channels. In accordance with the invention, automatic gain control data associated with each channel is stored in a tuning memory upon an initialization thereof. Video data stored in a buffer video memory is displayed and stored in a main video memory. Write and read operations of these video memory are controlled in a handshake fashion using a flag. Upon a channel change, previously stored automatic gain control data and tuning frequency are used, thereby achieving a fast tuning. The apparatus of the invention can provide fast quasi-moving PIP/POP screens.

Abstract: A double-screen simultaneous viewing circuit for simultaneously displaying two pictures on the main screen of a extra-wide television is provided. The two pictures each have a 4-to-3 aspect ratio and are displayed on left and right subscreens of the main screen. The viewing circuit includes first and second analog-to-digital converters for respectively converting first and second video signals of the two pictures into digital signals. The first and second video signals are respectively converted according to first and second clock signals which have equal frequencies and which are respectively synchronized with synchronizing signals of the first and second video signals. The digital video signals are stored in first and second memories based on the first and second clock signals, and the digital video signals are read from the first and second memories based on a third clock signal.

Abstract: A method and an apparatus for simultaneously displaying two independent video signals are described.

Abstract: An integrated circuit (22) processes baseband video signals to produce a picture-in-picture (PIP) channel for a video monitor (26). A discretionary control circuit (64) on the integrated circuit monitors parental discretionary control data on a predetermined horizontal line (21) of the baseband video signal. The discretionary control data is a value that represents the amount and degree of sex and violence in the presently viewed program. The parent or responsible party stores a threshold value in a television control circuit. The discretionary control circuit compares the discretionary control data to the threshold value. If the discretionary control data is less than the selectable threshold, then the PIP channel is displayed. If the discretionary control data is greater than the selectable threshold, then the PIP channel is blanked.

Abstract: A television channel display comprises remote controller signal receiver for receiving a channel number determined by a user, an MCU for receiving a signal output from the remote controller signal receiver, a memory for storing and outputting audio signals of the channel number and a broadcasting station name according to a control signal output from the MCU, an audio mixer for mixing the audio signal of the channel number and the broadcasting station name output from the memory, an aural processor for processing audio signals of an input broadcasting program, a multiplexer for selecting and outputting the audio signals of the audio mixer and the aural processor under a control of the MCU, and a speaker for converting and outputting audio current outputs from the multiplexer into an audio signal.

Abstract: An image display apparatus such as a television receiver has a frame memory for storing video signals. The image display apparatus displays a combination of main and auxiliary images on a display raster based on the video signals stored in the frame memory. Specifically, the image display apparatus displays a plurality of auxiliary images surrounded by respective frames, and responsive to a control signal from a remote control unit, for example, individually changes the manner in which the frames are displayed respectively around the auxiliary images. For example, the color of the frame displayed around one of the auxiliary images is changed when that one auxiliary image is selected.

Abstract: A HDTV system having a PIP function for implementing a PIP image by reconstructing an intraframe image with low resolution, includes a first tuner & channel decoder for receiving a video signal for a PIP via an antenna, a first depacketizer for receiving a signal generated in the first tuning & channel decoder and separating and outputting the same, a second tuning & channel decoder for receiving a video signal for a main screen via an antenna, a second depacketizer for receiving a signal generated in the second tuner & channel decoder and separating and outputting the same, a PIP decoder for receiving the video bit stream of the first depacketizer to reconstruct only the intraframe into a PIP image, a main video decoder for receiving the video bit stream of the second depacketizer and outputting a main image, a multiplexer for multiplexing the outputs of the PIP decoder and the main image decoder, and a VDP portion for receiving the output of the multiplexer and converting the luminance and chrominance signa

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: A display apparatus wherein a video signal of a child picture read out at a double speed is inserted accurately with a high resolution into a parent picture of another video signal having a double frequency. Control signals for designating a write area and a read-out area of a four field sequence memory provided for forming a double speed field frequency is formed in accordance with odd/even number field discrimination signals for write and read-out video signals, a vertical synchronizing signal prior to double speed conversion and a double speed synchronizing signal for a parent picture so that, even when the parent picture is scrolled, passing of the read-out side memory area does not take place. Where the parent picture is formed from a video signal of the interlace system by a line double speed, the double speed child picture video signal is delayed, upon reading out in an even-numbered field, by one horizontal scanning period so that lines may be overlapped between the parent and child pictures.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Implementation efficient video decoder for decoding multiple bitstreams to provide picture-in-picture capability in a digital video display device is disclosed. The video decoder includes a full resolution video decoder and a reduced resolution video decoder. The reduced resolution decoder decodes and downsamples video images using the same video memory device used by the full resolution decoder. By using a sufficient amount of downsampling, the amount of memory required to implement the video frame memory and decoder buffer required by the reduced resolution video decoder is reduced to a point where the frame memory and decoder buffer can be implemented using excess memory which is left over from the implementation of the full resolution decoder frame memory and decoder buffer. Accordingly, the present invention avoids or reduces the need to provide additional memory for frame storage when implementing picture-in-picture capability in a digital video display device.

Abstract: A method and apparatus for compensating for a position of a main picture displayed on a display screen of a display includes a sub-picture processor, a chroma processor and a display controller. The sub-picture processor receives an intermediate frequency signal of a sub-picture, and produces a sub-picture video signal of a predetermined aspect ratio from the intermediate frequency signal. The chroma processor receives a main picture video signal representing the main picture, and the sub-picture video signal. The chroma processor generates a composite video signal from the main picture video signal and the sub-picture video signal, and outputs the composite video signal to the display. The display controller controls the sub-picture processor and the display such that the main picture and the sub-picture are displayed on the display screen with a position of the main picture shifted on the display screen in a first mode of operation.

Abstract: A menu type multi-channel display system utilizing picture-in-picture (PIP) function and a page up/down mode. The present invention first comprises a first and second tuner to receive broadcasting signals and to output each of the broadcasting signals on a channel. The present invention further comprises a main screen selecting module to select either one of said first and second tuner or a line input signal and to output at least one main screen signal. The present invention further comprises a sub-screen selecting module to select either the first tuner, the second tuner, or a line input signal, and to then output a subscreen signal. The present invention further comprises a VCR signal processing circuit to screen-process the output signals from a reproduction output module of the main screen selecting module and to output a screen signal.

Abstract: A display is to be produced based on video signals having aspect ratios of 4:3 and 16:9. Controller 21 turns on switches SW1 and SW2 so that the digitalized video signal of the first picture is compressed at a rate of 3/8 in the time axis. Simultaneously, the video signal of the second picture is converted digitally, written into memory 14 in synchronization with the first picture video signal, read out based on a delay of 3H/8 from the synchronization with the first picture video signal, and sent to a digital processing circuit 13. The controller 21 controls the digital processing circuit 13 so as to compress in the time axis the video signal of the second picture at a compressing rate of 5/8. Also, the controller 21 controls a vertical amplitude switching signal generator 19 to adjust a vertical deflecting current in a deflecting circuit 18 based on an operation by the audience.

Abstract: An automatic clock-setting apparatus and method, which can recognize clock-displaying characters as numerals included in a television broadcasting signal when the clock-displaying characters are displayed on a screen, and which can automatically set a current time of a built-in timer of a television or a video cassette recorder by the recognized numerals. According to the invention, it is possible to set a clock exactly and to make the clock-setting operation by the user convenient.

Abstract: A television receiver has horizontal reducing filter and a vertical reducing filter independently responsive to a first filter control signal and a second filter control signal for reducing auxiliary luminance/chrominance signals indicative of a sub-picture at an arbitrary aspect ratio, and a display unit reproduces a main picture and a reduced auxiliary picture on a screen in an overlapped manner.