Abstract: An image recording apparatus includes an image sensor. Image data of an object imaged by the image sensor is recorded on a recording medium to which an FAT system is adopted. A recording area of the recording medium is divided into a plurality of clusters, and available clusters can be dispersedly distributed. When formatting the recording medium, a CPU increases a cluster size as a capacity of the recording medium is larger, or the recordable number of frames of the recording medium is greater.

Abstract: An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A decoding processor (12) decodes a current block of a generated picture using lines of previously decoded image data from the memory (14) that are selected in dependence upon a motion vector (V1) for the current block. In order to improve access efficiency to the memory (14) the decoding processor (12) concatenates fetches into bursts for different sections of lines of previously decoded data that lie within a predetermined range within the memory addresses of the memory (14).

Abstract: An apparatus and method for generating compressed image data, and outputting decoded images using the compressed image data. A compressed image data generation unit receives and compresses image data taken from a first camera arranged to generate an additional image and inserts the compressed image data into a specified area of the compressed image data generated using a picture image received from a second camera arranged to generate an ordinary image. An image output apparatus receives the compressed image data including the compressed picture image data, determines whether the compressed picture image data exists. If the compressed picture image data are present, the apparatus decodes the image data to generate a three-dimensional stereoscopic image as output using the ordinary image and the additional image. However, if the image output apparatus is not capable of three-dimensional image generation, it only provides the ordinary image.

Abstract: Disclosed herein is an apparatus and method for transposing data. The apparatus includes a pair of line memories, a pair of memories and output units. The line memories horizontally read image data a frame of which is composed of K×L byte data (row length: K bytes, column length: L bytes), and alternately storing data arrays each having a K×N byte size (N?2). The memories alternately reads the image data from the line memories on an N-byte-at-a-time basis and each store a data array corresponding to one frame. The output units vertically address the data arrays stored in the memories on an N-byte-at-a-time basis and output the addressed data arrays.

Abstract: This invention teaches an apparatus and method for merging information transmitted in vertical blanking interval (VBIs) of several services into a single VBI. The system includes a pair of memories for each service wherein each memory is toggled between a read and write cycle. While the first memory is in a write cycle, the second memory is in a read cycle and vice versa. A field programmable gate array (FPGA) controls the first and second pairs of memory to merge the VBIs.

Abstract: A method for managing vertical format converter line memories includes writing a number of first input video lines into the VFC line memories, writing an additional video line into the VFC line memories, and reading respective pixels of the first input video lines and the additional input video line from the VFC line memories in parallel. The reading of respective pixels is commenced prior to completion of the writing of the additional video line. A digital video receiving system includes a somewhat similarly configured video processor.

Abstract: A frame memory device is employed in a digital camera, for example, to output raster-scanned digital color image signals at lower resolution than that of original image signals. The order of sequentially received original raster-scanned digital color image signals is rearranged, and the rearranged signals are sequentially stored in a memory having a two-dimensional address structure such that vertical addresses represent the order of entry of respective scan lines that constitute the image signals and horizontal addresses represent the order of entry of respective signals that belong to each of the scan lines. The stored rearranged signals are subsampled and read out while skipping horizontal and vertical addresses of the memory at regular intervals. The image signals may comprise YCBCR color signals having a sampling ratio of 4:2:2. Sequentially received C signals in the order of CB?CR?CB?CR, for example, are rearranged in the order of CB?CB?CR?CR.

Abstract: A video processing circuit for preventing generation of contour noise irrespective of varied directions of light emission schemes. A first video signal and a second video signal delayed by a predetermined field are received, a first motion detection result is output when a signal level of the first video signal is greater than that of the second video signal, and a second motion detection result is output if the second video signal is greater than the first video signal. A flag is established according to the first motion detection result, and a third video signal generated by delaying the first video signal is output. The lighted pattern of the third video signal is switched according to the second motion detection result and the flag.

Abstract: An apparatus and method for displaying an out-of-range mode which has a resolution higher than a mode supported by a monitor is provided. The method for displaying an out-of-range mode in monitor displaying includes the steps of (a) sensing received horizontal and vertical synchronizing signals and determining a display mode, and (b) adjusting a sampling rate so that a received video signal is displayed in a supported display mode in a case where the display mode is a mode excluding a supported display mode as a result of determination in step (a). The out-of-range mode which has a resolution higher than a mode supported by an LCD monitor so that a user's system can be easily and conveniently converted into a supported mode without additional apparatus or equipment, can be displayed in the LCD monitor.

Abstract: Each functional block constituting a pipeline resets its own memory device in synchronization with a timing that last pixel data of one line is processed and output. A reset controlling unit in a first functional block includes an attribute signal generation circuit for generating an attribute signal indicating whether or not each pixel data being input is last pixel data and attaches this attribute signal to the pixel data by transferring in synchronization with corresponding pixel data. When the processed pixel data is output, the attribute signal of the corresponding pixel data is referred to control resetting the memory device. Other functional blocks control resetting their own memory devices using an attribute signal synchronized with the pixel data and transferred from previous functional block.

Abstract: A source image (S) that is distorted by camera optics is transformed into a corrected image (T) by using a tabular imaging rule. This transformation occurs directly during the reading out from the image sensor and in real-time. No, one or several target pixels in the target image (T) are assigned to each source pixel of the source image.

Abstract: Disclosed are an apparatus and a method for compensating for an interlaced-scan type video signal for stably displaying the video signal in the LCD panel. An aft part of 264th data of a first field and a fore part of 23rd data of a second field are stored in memories. A present video signal is determined whether the present video signal is a first field signal or a second field signal through an equalizing pulse period. If the present video signal is the first field signal, a fore part of 23rd data is copied to the first data field, and if the present video signal is the second field signal, the aft part of the 263rd data is added to the second field data. In case of a PLA-type video signal, first data represent 23rd data, and final data represent 313rd data.

Abstract: A method of processing video data in a receiver/decoder including at least one port (31) for receiving data and memory means (40) including a data buffer area (45A0, 45A1) for storing incoming data for display, and a graphics buffer area (45Ai) for storing graphics data, said method including passing graphics data stored in the graphics buffer area to the data buffer area for combination with display data stored therein.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: A method for scrolling MPEG-compressed pictures consists in decoding a sequence of pictures (34, 35, 36) or any two pictures to be viewed by a MPEG decoder (5) and storing the sequence of pictures (35, 35, 36) or any two pictures in MPEG decoder memory. Then the sequence of pictures (34, 35, 36) or any two pictures is formed as a group of pictures (37), which is transferred to the first screen buffer (24) which is active. In the following step, any another compressed picture, after decoding in the MPEG decoder (5), is stored in a MPEG decoder memory as a decoder new picture and then is transferred from the MPEG decoder memory to the first screen buffer (24), where its edge line perpendicular to the intended scrolling direction is adjoined to the external edge of the group of pictures (37).

Abstract: A personal optical viewer enables a person to view images of how the person looks wearing an accessory and compare images of how the customer looks wearing different accessories. A seller provides an accessory to a person. A capturing device captures a photograph or a video of the person and stores the image in a memory device. The personal optical viewer displays each image to the person and the person chooses which images to keep, reject, delete, or compare. The personal optical viewer replaces rejected images with other images stored in the memory device, and when the stored images have been exhausted the personal optical viewer automatically enlarges the remaining displayed images.

Abstract: There is provided a multi-screen synthesis apparatus that can execute display of video data and update of an OSD image without causing a user to feel a visual sense of incongruity, and reduce system costs. Periodic video source data and a periodic OSD image data are written into a unified memory reserved for planes. The video source data and the OSD image data are read from the unified memory, based on a synthesis layout, for simultaneous display on a single display in a synthesized state. Video data to be written into the unified memory is decimated in units of a frame on an input video source-by-input video source basis. The decimation of the data is controlled based on display priority of the video data determined based on a multi-screen display layout.

Abstract: A double-rate signal achieved by subjecting a video signal to double-rate conversion is supplied to a scan line number converter. In the converter, the portion of the effective scan lines of the double-rate signal is written into a frame memory on the basis of a signal achieved by multiplying horizontal and vertical synchronous signals based on the double-rate signal. In the effective scan line section of HDTV signal, the video signal written in the frame memory is read out on the basis of horizontal and vertical reference signals based on'the HDTV signal. Out of the effective scan line section of the HDTV signal, a pedestal level signal written in a memory is read out on the basis of the horizontal and vertical reference signals based on the HDTV signal, thereby achieving HDTV signal whose vertical scan line number is equal to 1125 lines.

Abstract: Signal processing is enhanced using a filtering arrangement that re-uses data in a register array for filtering consecutive pixel blocks. According to an example embodiment of the present invention, consecutive blocks of pixel data corresponding to an image and sharing an edge therebetween is filtered. The consecutive blocks of pixel data are read and loaded into first and second halves of a register array, and pixel data in registers on opposite sides of the edge is filtered and returned to the register array. After filtering, data in the first half of the register array is unloaded and written back to the memory. Data in the second half of the register array is then shifted to the first half of the register array and additional pixel data is read and loaded into the second half of the register array. The additional pixel data corresponds to the image, is consecutive to and shares an edge with the pixel data shifted to the first half of the register array.

Abstract: Disclosed are a method of constructing information on associate meanings between segments of a multimedia stream, which can describe the cause/effect or abstract/detail relationship between segments of the video streams to efficiently browse the video stream and a method of browsing a video using the same. The present invention defines the cause/effect or abstract/detail relationship between the segments, event intervals, scenes, shots, etc. existing within one video stream or between the video streams, and provides a method of describing the relationship in a data region based on the content of a video stream as well as a method of browsing a video by using the information on the cause/effect or abstract/detail relationship obtained by the aforementioned method. Accordingly, a video browsing on associate meanings is available with easy manipulation and easy access to a desired part, thereby providing an effective video browsing interface for easy browsing of desired segments in a short period of time.

Abstract: Method for controlling a memory in a digital system, including the steps of (a) dividing the memory into a plurality of fixed sized memory blocks, (b) defining at least one of the memory blocks as a compression/decompression region, (c) assigning compression priorities to rest of the memory blocks except the memory blocks defined as the compression/decompression region, and (d) making the memory blocks to deal with an external data received according to an external command, and carrying out compression/decompression of data required in the dealing with the external data at the compression/decompression region according to the compression priorities.

Abstract: An image binarization method having highest fidelity for multi-digitized luminance data, and a binary image creation method by which images can be obtained in real-time without post-processing. Thresholds in binarization are not fixed, but set in accordance with changes in luminance, thus allowing real time images to be obtained.

Abstract: A system and method for processing YCbCr video data stored in a paged memory with reduced page breaks. A method is disclosed for retrieving YCbCr planar video data in 4:2:0 format from paged memory. A page of the paged memory containing Y data is accessed; Y data corresponding to M pixels of video data is then retrieved, where M is a value greater than or equal to two. The retrieved Y data is then stored in a shift register. Similar steps are taken to access, retrieve and store Cb and Cr data. Within the shift register, the Y, Cb, and Cr data is stored as sets of planar video data. The Y, Cb, and Cr data is retrieved from the shift register as a series of pixel data for generating pixels on a video display unit.

Abstract: The invention relates to the simultaneous operation of items of electrical apparatus, such as but not exclusively, a broadcast data receiver and a DECT telephone system. A problem with this type of apparatus is that the operating frequencies of the same can overlap and in turn cause interference in the operation of the respective items. The invention provides a method for identifying the overlap of the RF ranges of the apparatus, and having identified the same, adjusting the operating characteristics of one of the items to allow the interference to be avoided or minimized and the opportunity for the items of apparatus to be combined into one unit.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: An adaptive filter is adjustable for performing scaling operations. During a scaling operation, the adaptive filter stores scaled data in a memory such that more data samples may be retrieved during a subsequent scaling operation. The size of a finite impulse response filter used during the subsequent scaling operation may be adjusted to access the additional data samples.

Abstract: The present invention relates to a method for decoding and storing digital broadcasting signals which is capable of freely adjusting size and position of a broadcasting video window by preventing a frame buffer conflict between storing and fetching timing of the decoded data which can be occurred depending on the position and the size of the video window displayed on a screen, without expanding memory or upgrading speed of the decoder.

Abstract: A memory mapping method for mapping a data array into a memory. The memory mapping method provides the two-directional access in the data array. The memory mapping method first equally divides each row of the data array into some basic units based on the number of the columns of the data array. Next, a predetermined number of adjacent basic units in the same column are arranged into a basic memory block. Finally, the basic memory blocks are mapped into the memory.

Abstract: Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.

Abstract: The present invention provides advanced encoding and advanced reconstruction apparatus and methods enabling low bitrate, enhanced coding and quality-enhanced reconstruction, among other aspects. Preferably operating in accordance with a super-domain model, the invention enables the superimposed use of advanced coding tools such as for determining the susceptibility of image data to optimization and degradation avoidance. Other preferred tools also include multi-dimensional diffusion, registration, meta data utilization, advanced constructs, image representation optimization and efficiency optimization. Advanced decoding further enables maximized utilization of received enhanced image data and other information, also preferably in accordance with a super-domain model. Advanced encoding preferably comprises reverse-superresolution encoding and advanced decoding preferably comprises advanced superresolution decoding, which can further be conducted in a distributed and/or cooperative manner.

Abstract: “An image processing system, in which bit shuffling is done in order to maintain image quality, stores digitized video data bits stream in a conventional memory, such as a DRAM. The image processing system is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the DV-SD standard, or “Blue Book”). The image processing system receives a number of blocks associated with a first video frame and stores these blocks in the DRAM. The image processing system receives and stores blocks associated with a second video frame in the DRAM. The image processing system, processes the blocks of the first video frame while storing the blocks of the second video fame.

Abstract: An architecture for video decompressor to efficiently access synchronously memory includes a synchronous memory device having an A-bank and B-bank for being stored with image data, and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display. The image data has a plurality of scan lines and every four scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (4N+0)-th and (4N+1)-th scan lines, and the B-bank is sequentially stored with the (4N+2)-th and (4N+3)-th scan lines, where N is a non-negative integer, so as to always perform memory operations by alternately accessing the A-bank and B-bank.

Abstract: A method of implementing on screen display (OSD) function and a device thereof are provided. The method includes the steps of storing the graphic data in a dynamic random access memory (DRAM), obtaining the displaying information and a sequence for the graphic data by an OSD decoder, and showing the graphic data by an address generator on a screen according to the displaying information and the displaying sequence. The device includes a dynamic random access memory (DRAM) for storing the graphic data, an OSD decoder for obtaining a sequence according to the stored graphic data, and an address generator electrically connected to the DRAM and the OSD decoder for showing the graphic data on a screen according to the sequence.

Abstract: Video data formatting apparatus and method in which an input signal is converted (transcoded) into an intermediate compressed video signal, where the intermediate compressed video signal has a GOP format in which each GOP contains fewer pictures than a GOP associated with the input video signal. A metadata signal which indicates data defining coding decisions is derived from the input video signal. A data quantity allocation is generated to control the transcoding into the intermediate video signal, whereby each picture of the intermediate video signal is transcoded so as not to exceed a respective data quantity allocation.

Abstract: A multi-standard channel decoder for real-time digital broadcast reception has a plurality of processors connected to a sample-based communication unit for sample-based processing and connected to a block-based communication unit for block-based processing. The channel decoder is able to use the same processors to channel decode sample-based transmissions such as 8-VSB broadcasts and block-based transmissions such as COFDM broadcasts.

Abstract: In a device for controlling the displaying of characters for a video system, the memory for storing information relating to the displaying of the characters is partitioned into two areas. The first area (Z1, Z1′) is for storing, at fixed addresses, data and parameters for general control of the display. The second area (Z2) which is divisible into spaces (B1, B2, B3) of variable sizes stores, in each of the spaces, control parameters and data relating to the displaying of a row of characters, wherein the spaces are chained together by virtue of a parameter, the address of the next memory space, stored in each space. This memory architecture offers multiple possibilities for modifying the display parameters from one row to another within one and the same “screen” whilst optimizig the size of the memory used.

Abstract: Plural encoders operating in parallel to achieve a desired data rate have their respective outputs combined by an autonomously operating arrangement for transfer of data to a direct memory access arrangement from respective encoders in order in response to a signal asserted upon completion of encoding and output of encoded data corresponding to a predetermined portion of input data. buffering of encoder output can be either internal or external to the encoders. Zero bytes which may be inherently generated at the beginning and end of an encoder output stream may be suppressed to improve encoded signal quality and efficiency.

Abstract: In order to reduce memory requirements in a chip for demodulating digital video broadcast signals, symbol data values stored for a channel equalisation process have their scattered pilots removed, to achieve a 9% reduction in memory space required. This is achieved by providing a write pointer and a read pointer, the write pointer being arranged to exclude carriers carrying scattered pilots, and the read pointer being arranged to read the stored symbol data, but to add nominal data values at positions of excluded scattered pilots.

Abstract: A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.

Abstract: A system and a process for providing a video-based human computer interaction environment are disclosed. A modular framework defining an integrated presentation space is exported when the application is executed on a client. It includes an interactive video presentation interface, a pre-recorded video database and a database for recording the users' response videos. The user or administrator can manage the pre-recorded video database. The user can play the pre-recorded video in the video database. The user can record response video as video input to the computer according to each pre-recorded video. The user can preview the recorded video response.

Abstract: In a method of controlling a memory (5) to allow for a display of at least two images, write and read speeds of writing image data into and reading image data from the memory (5) are measured (9-15) to predict a crossing where a write action overtakes a read action or reversely, where a new field of said image data is written (13, 3) into the memory (5) from a same initial position as from which a previous field of the image data was written into the memory (5) if no crossing is predicted, and the new field of said image data is written (13, 3) into the memory (5) from an end position in the memory (5) at which an end of the previous field of the image data was written into the memory (5) if a crossing is indeed predicted, the memory (5) having a size being larger than that needed for one field but less than that needed for two fields of the image data at its largest read-out size.

Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: An information processing apparatus includes an address generation circuit for generating an address signal. A memory operates for storing an information signal containing a video signal in response to the address signal. The address signal is periodically updated. A compression processing circuit operates for reading out the information signal from the memory, and subjecting the readout information signal to a compressively encoding process. A head of every frame represented by the information signal is detected. A state of the address signal is stored which corresponds to the detected frame head. Detection is made as to whether or not the information signal becomes discontinuous. The updating of the address signal and also the operation of the compression processing circuit are suspended when it is detected that the information signal becomes discontinuous. Detection is made as to whether or not the information signal returns to a normally continuous state after the information signal becomes discontinuous.

Abstract: A television receiver, in which if a tuner can receive a signal of the television broadcast form of either television wave broadcasting or CATV broadcasting, a microcomputer executes channel preset processing so that signals of television wave broadcasting can also be received although the processing is predicated on CATV broadcasting, then determines signals of which television broadcast form can be received. If the microcomputer determines that the signals of the television wave broadcasting can be received, it makes a reference to the memory positions of the preset contents. To cause the tuner to receive a station-existing channel, the microcomputer matches the target memory position with the channel of television wave broadcasting for receiving the channel.

Abstract: New and improved methods and apparatus for code packing in a digital video system. Among others, a method of transferring a data block to a storage device is disclosed. The storage device can include a plurality of compartments. The method includes receiving a plurality of length values. Each length value can correspond to a data block from a plurality of data blocks. The method further includes filling a first compartment of the storage device with a portion of data from a first data block, searching the length values to identify one of the plurality of data blocks having a length value less than a threshold value, and filling a second compartment with a remaining portion of the data from the first data block. In one embodiment, the second compartment can correspond to the identified data block.

Abstract: The invention concerns a method of increasing the storage capacity of service information data (SI) in a receiver for digital TV transmissions, such as e.g. in accordance with the MPEG 2 and the DVB standard. The increase takes place to enable keeping a larger quantity of service information data ready for recall, which is used to create the display of an interactive electronic program guide that is shown as an “On Screen Display” (OSD) on the screen. Such a program guide is designed to make the transmission choice easier and to automate the adjustment of the receiver for the desired transmission. The object of the invention is to provide a solution which makes it possible to expand the storage capacity, especially the mentioned cache area, without additional hardware. To achieve the object the unoccupied area of the image memory (MPEG-RAM) is used as a cache area by the video decoder (V-DEC) while graphic displays are shown on the full screen surface as a “Full Screen OSD”.

Abstract: A video compression technique is provided which reduces motion estimation computations. A digital signal processing system employs external memory. Detection speed is improved by loading a succession of refined search windows are loaded on-chip. By so doing, the search involves fewer accesses to external memory and so completes in a shorter amount of time.

Abstract: A system for transferring video data includes a difference detector for detecting the difference between a current field information and the preceding field information. The preceding information is obtained from an entered interlaced video signal. An interpolator generates current display frame information in response to an interpolation based upon the current filed information with regard to an area of the video signal in which there is a difference value between successive fields that exceeds a predetermined threshold value. The interframe difference between the current display frame information and preceding display frame information is detected by the difference detector. Only the interframe difference is transferred over a system bus to enable a frame display to be presented on non-interlacing display device.

Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: An image motion compensating address generator is disclosed including a mode selector for selecting a field mode or frame mode according to a video mode signal and a slice position signal, an address selection controller for controlling the generation of addresses according to the video mode signal and a motion coding type signal, a Y-direction read address generator for producing a Y-direction read address in units of processed block, an X-direction read address generator for dividing the processed block into four phases in the X-direction and generating an X-direction read address, an X-direction write address generator for delaying the processed-block position signal and a field processed-block clock signal, and generating the X-direction write address of four phases, a Y-direction write address generator for producing a Y-direction write address, and a read & write controller for selecting outputting the X-direction and Y-direction read and write addresses according to a read/write selection toggle si