Abstract: A block to raster converting circuit which is adaptable to all formats with a single circuit is realized. Macro-block data is mapped into a frame memory (13) on the basis of a particular format whose data size (X) in the horizontal direction provides a max condition. When writing, for each macro-block row (MBRi), the address of the first data in the initial macro-block (IMBi) is specified, on the basis of which address the column and row addresses are regularly switched according to the data array in the macro-block (MB). When reading, for each macro-block row (MBRi), the address of the initial data is specified, on the basis of which address the row address is switched every time data in each horizontal line in the macro-block row (MBRi) has been read and every time data at a turn of the column address in the frame memory (13) has been read. The column address is sequentially switched.

Abstract: A liquid crystal display control apparatus includes a display on/off data generation circuit for generating plural display on/off data per pixel corresponding to M (M>N, M and N being integers) frame periods of a video output signal in N frame periods of a video input signal on a unit pixel basis in response to gray-scale data of pixel units included in the video input signal, a write control circuit for writing display on/off data per pixel corresponding to M frames of the video output signal generated by the display on/off data generation circuit into a frame memory during N frame periods of the video input signal, and a read control circuit for sequentially reading out, from the frame memory, display on/off data corresponding to M frames of the video output signal written in the frame memory in synchronism with one display scan period of the video output signal, thereby the data written in the frame memory is not gray-scale data but display on/off data of one bit, therefore, a data bus width at a time o

Abstract: A video graphics system wherein a large quantity of video data is independently and selectively made available to plural video display devices. The large quantity of video data can be contributed to by plural sources of video data of differing formats. Further, the display devices can also be of varying types, each requiring a different input data format. A multi-sourced video distribution element, also referred to as a hub, serves as an interface between one or more sources of video display data and one or more video display devices. One source of data can be identified as a base image, and other sources of data can be utilized for overlay images integrated into the base image. The base image and any integrated overlay images are provided on a pixel bus internal to the hub. The hub can then be configured as an interface to one or more types of video display devices and/or to another hub.

Abstract: A method and device is described herein for displaying a television picture comprised of several standard aspect ratio images on widescreen and standard aspect ratio video monitors. A widescreen image including several smaller aspect ratio images are assembled and broadcast. A receiver with a widescreen monitor display can display the entire widescreen image. A receiver with a conventional aspect ratio monitor display can display a combination of the smaller aspect ratio images. The device includes a frame store for storing image information, image configuration logic for determining a configuration of image information, and frame address logic to write image information to frame store with a configuration according to image configuration logic.

Abstract: An image processing device comprises an SIMD (Single Instruction stream Multiple Data stream) calculating unit (101) for performing operations, such as motion compensation, motion prediction, DCT (Discrete Cosine Transform) processing, IDCT (Inverse Discrete Cosine Transform) processing, quantization, and reverse quantization by means of a pipeline operation unit that can be program-controlled by an outside unit, a VLC (Variable Length Code) processing unit (102) for performing variable-length encoding processing and variable-length decoding processing according to a given encoding method, an external data interface (103) for performing a data transfer between the image processing device and an outside unit, and a processor (105) for decoding an instruction held by an instruction memory (104), and for performing a programmed control operation on the SIMD calculating unit (101), the VLC processing unit (102), and the external data interface (103).

Abstract: An information recording and reproducing apparatus includes a solid-state memory medium for memorizing serial moving-image information and a reproducing circuit for reproducing a plurality of pieces of moving-image information from the solid-state memory medium in parallel.

Abstract: Frame-rate control electronic provides gray-scale display control algorithm for STN LCD devices and constant brightness display with randomized pattern algorithm. Even distribution control of phase number reduces screen flicker and stabilizes gray-scale display. Randomized and scrambled phase number control eliminates screen beating artifacts, such as when image includes dither and checker patterns. Programmable parameters, such as tuning value, phase number matrices, and frame offset numbers, may be chosen flexibly to optimize conditions to certain display.

Abstract: During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient capacity to store complete video pictures do not have the necessary access time to perform image processing in real time. The invention therefore provides for the writing of picture blocks from a picture memory to a fast access memory. Only the pixels in the access memory are accessed when the image processing operation is performed. During the read-out, a further block from the picture memory is simultaneously read into the access memory. As a result, fast access to the picture data is possible in conjunction with little additional outlay in respect to memory. Areas of application for the method are in the image processing of video pictures.

Abstract: Disclosed is an inexpensive and miniaturized digital video disc playback device having a system decoder capable of error correcting and data buffering by means of a single memory without employing separate error correcting and data buffering memories. The inventive system decoder for demodulating, error correcting, deinterleaving and descrambling of data reproduced from a disc in the digital video disc playback device, includes a memory and a memory controller for generating memory control signals for accessing the memory to record and read data when demodulating, error correcting and descrambling the reproduced data.

Abstract: A system and method of controlling a memory of an HDTV video decoder is disclosed which has a video bit stream write buffer, a bit stream read buffer, a motion compensate buffer, a store buffer and a display buffer and outputs request signals to read/write a data from/into an external memory every time it is needed in order to decode an input video bit stream. The method includes the steps of prioritizing the request signals output and sending an authorization signal in response to each of the request signals.

Abstract: A system and method for decoding and displaying a video bitstream representing video images and displaying the video images. The present invention discloses a split memory manager design which is particularly adapted to display MPEG-2 format video images. In addition, the present invention discloses a novel way of managing the video memory used in a video decode and display system. Finally, an intraframe video data compression system and method is disclosed to complement the disclosed video decoding and displaying system.

Abstract: Decoding images encoded on MPEG requires I and P pictures to be held for a long period of time for B picture reproduction, resulting in a greater amount of memory capacity necessary. This image data decoding apparatus has a reverse quantization section, a reverse DCT section, a sequence managing section, a motion compensating section, and a DRAM control section. Reverse quantization and reverse DCT operations are performed on input encoded image data. The sequence managing section determines the type of input pictures and detects sequences where more than one B picture is continuously input. I and P pictures are necessary for the decode operation of B pictures, so they are held in any frame bank. However, a B picture which has already been displayed is unnecessary, so one bank is shared by two B pictures which are continuously input. This results in a smaller number of necessary banks.

Abstract: A multimedia information transfer system includes a multimedia server and a client server system coupled with the multimedia server through a communication network and transfers data transmitted from the multimedia server to a server of the client server system. The multimedia server stores data streams of the multimedia information and reproduces the information. The client requests the multimedia server to transfer data, stores the transferred data block and displays the stored data block concurrently with the storage of the next coming data block.

Abstract: A system and method for transmitting blocks of compressed data in an ATM network is disclosed. Compressed data blocks representing a movie are labeled prior to transmission with the amount of data in each block and information regarding the compression ratio of each block and the time into the movie at which the block displays. A server in the system first determines the size of the receiver buffer, and then the minimum number of consecutive blocks that would fit in the buffer. It then determines minimum rate in bits per second by dividing the buffer size by the number of blocks, times 8 bits/byte, times the duration of each block in seconds. The server further instructs the receiver to wait before decompressing and displaying data by an amount of time sufficient to receive the amount of data from the first blocks of compressed data that is equal to the amount of data in the largest compressed data block in the file.

Abstract: The invention relates to an architecture making it possible to store and transfer still or moving video images, the said architecture comprising at least one input circuit (E1, E2, . . . , En) allowing access for data intended to make up video images, a memory area (M) making it possible to store video images, at least one video image output circuit (S1, S2, . . . , Sj) and a video bus (B) intended to provide for the transfer of information between the memory area (M), the input circuit and the output circuit, characterized in that the memory area (M) is a general-purpose memory and in that the video bus (B) has a width L greater than or equal to the width of the memory area (M).The general-purpose memory is operated in a centralized manner by a control circuit (CTRL).The invention applies to computer platforms dedicated to the transfer of Broadcast quality images or alternatively to video devices for built-up image animation.

Abstract: A memory system for B frames of pixel data, where each B frame includes a plurality of sections, and where each of the plurality of sections includes pixel data corresponding to the top and bottom fields of a frame. The memory system includes a memory organized into a plurality of segments for storing the pixel data, where the number of segments equals the number of frame sections plus two additional segments. However, each of the segments is half the size of a frame section. The memory system also includes a segmentation device for receiving and separating pixel data according to the top and bottom fields of each frame. The segmentation device tracks the segments to determine two available segments of said memory, and for each section of each frame, stores pixel data from the top field into one of the available segments and stores pixel data from the bottom field into the other available segment of the memory.

Abstract: A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8.times.8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16.times.

Abstract: A method of a storing a picture in a memory such that bandwidth can be reduced when retrieving an array portion of the picture from the memory, and a memory architecture are disclosed. The memory is subdivided into a plurality of words for storing a picture having rows and columns. The picture is partitioned into two or more stripes each having a predetermined number of columns. The number of bytes in one row of one stripe is equal to the number of bytes in one word, for storing the data in one row of a stripe in one word. For the case of progressive video sequences or images the memory is organized in frame structure. For the case of interlaced video sequences or images, the memory is organized in field structure. For a frame picture to be stored in a frame organized memory or a field picture to be stored in a field organized memory, the data in the first row of one of the stripes is stored in a first word.

Abstract: A decoded video signal which was encoded in accordance with a standard, such as MPEG-2, is encoded "on the fly" using a lossless linear predicted coding technique and stored in a compressed form in a RAM. A separate encoding technique is provided for B pictures and for I or P pictures. The compressed B pictures are decompressed for display. The compressed I or P pictures are decompressed for display or for use in decoding other P or B pictures.

Abstract: An apparatus for controlling a display memory for storing decoded picture data is disclosed, that comprises a data dividing portion for dividing decoded picture data as one macroblock in a vertical direction, a write address generator for generating the binary value of a write address necessary for writing the divided picture data to the display memory, a slice counter for counting the number of slice lines of picture data that has been written to the display memory, a rotate-shifter for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted, a means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted, a read address generator for generating the binary value of a read address necessary to read picture data from the display memory, a rotate-shifter for rotating and shifting the binary value of the generated read address to the left by a

Abstract: Processes, devices and systems for creating, manipulating and displaying images employing variable-geometry pixels. Pixels may vary in size, shape or position. Storage and transmission requirements may thus be reduced; as well as an increase in apparent resolution.

Abstract: A digital video disk reproducing device utilizes a single memory both for error correction and for data buffering. The device designates a unit number to each sector of the memory and determines first, second and third regions. The first region corresponds to an absolute value of a unit number obtained by subtracting a unit number Y of a sector where a data read/write operation is completed during the descrambling from a unit number X of a start sector in an error correction block where the error correction is completed. The second region corresponds to an absolute value of a unit number obtained by subtracting a unit number Z of a sector where the data is completely transferred to the audio/video decoders or the ROM decoder from the unit number Y. The third region corresponds to an absolute value of a unit number obtained by subtracting the unit number Z from a unit number W of a sector where a writing operation of demodulated data is completed.

Abstract: Methods and apparatus for performing packet synchronization recovery and error detection operation on packets including a CRC check byte, e.g., MCNS packets, are described. The present invention uses a memory during a sync acquisition mode of operation to serve as a storage device for the output of a first function circuit. The delayed bits are used as the input along with current bits from the packet stream to a second function circuit. The second function circuit generates a syndrome byte of interest. When the received packets are error free and the decoder is properly aligned with the packet structure of the bitstream, the syndrome byte of interest will assume a preselected value, e.g., 47 Hex. Once packet synchronization has been achieved, the relatively few bits output by the first function circuit which are required as delayed inputs to the second function circuit are identified and stored using a delay register which is much smaller than the memory.

Abstract: An image data decoding and displaying apparatus is equipped with a decode map set for storing decoded data for every frame into an empty areas in a memory. This set contains a plurality of maps each describing a memory area for a frame. A map is changed by a unidirectional counter for every start of a decode operation in frames. A display map set is also provided with a bidirectional counter. Normally, these two counters are incremented every time a frame is decoded and displayed, respectively, so the same maps are referred to from decode operation and display operation. In the display operation, bidirectional counter is decremented by one if data is not decoded in time for display, so that a map for an immediately preceding picture is referred to. In such a case, the previous picture is displayed twice in place of the current picture. Display transition from the current picture to the previous one is performed smoothly changing maps consistently for these pictures.

Abstract: A binarization processing apparatus for converting multi-value image data into binary image data is constructed by pixel groups in which pixels to be binarized are divided into a plurality of groups, a plurality of memories which correspond to the pixel groups and hold data in a binarization processing step, a control unit which performs the reading operation for one of the plurality of memories and simultaneously performs the writing operation for the other memory, and a unit for performing the converting process on the basis of an error diffusing method. The plurality of memories have a single common input/output port.

Abstract: A multi-channel memory system for holding video image data employs a particular form of interleaving in each channel to achieve optimum performance. Data representing luminance and chrominance components are written into the memory in respectively different channels such that the luminance information occupies one part of a memory row while the chrominance information occupies another part. The channel assignment is cycled within a memory row and is changed from one row of the memory to the next such that all luminance information in the row is contiguous and all chrominance information is contiguous yet luminance information and its corresponding chrominance information may be accessed in a single operation using all three channels. The memory is organized in three channels, each channel including two devices and each device including two banks.

Abstract: In a decoding/displaying device, the memory capacity or mapping to B pictures is set in consideration of a decoding waiting period, thereby avoiding the competition between a write-in operation and a read-out operation for a memory. Therefore, the decoding operation of coded picture data can be performed with no decoding waiting period.

Abstract: An electronic camera records files of photographed images in such a manner that files of images photographed under different photographing circumstances (e.g., different exposure modes, compression rates, or photographing dates/times) can readily be distinguished. In certain preferred embodiments, a data management index corresponding to a first photographing circumstance is recorded at a first hierarchy level and a file name assigned to an image photographed under the first photographing circumstance is recorded in association with the file management index at a hierarchy level different from the first hierarchy level. A second data management index corresponding to a second photographing circumstance or a file name assigned to an image photographed under a second photographing circumstance is also recorded at the first hierarchy level.

Abstract: A method of retrieving image information is disclosed in which a reference block is selected which overlies three sections of an image stored in a memory having two banks. Exactly two of the sections of the image are stored in the same bank of the memory. A sequence in which to read the three sections is selected such that the two sections in the same bank are not read consecutively. Each section of the image underlying the reference block is read in the selected sequence to retrieve the image information.

Abstract: A video port interface that determines the amount and type of incoming data by reading information from certain memories. A first memory indicates a first format of the incoming data. A second memory indicates a second format of the incoming data. Finally, a third memory indicates a number of lines of the first format that will be received. The video port interface reads all three memories at the beginning of each frame, then counts incoming lines until it reaches the line indicated by the third memory. At the end of that line, the video port interface switches from processing the data in the first format to processing data in the second format.

Abstract: An apparatus for decoding an encoded digital video signal for the reproduction of an original video image signal comprises an image data partitioning circuit for dividing difference pixel values on the basis of the current macro block into four equal-sized current subblocks, motion compensation units and a formatter for providing predicted current macro block data, adders for providing the reconstructed current macro block signals by combining the predicted current macro block data and the difference pixel data. The motion compensation units have four memories for storing the reconstructed current macro block signals as the divided previous subblock data.

Abstract: A television signal format converter is provided for converting without loss of picture information any high definition television format to or from a given recorder/player format. An interface converts between RGB and luminance/chrominance inputs and between analog and digital inputs. The interface couples any proposed high definition television format to a plurality of pairs of memories. A clock and control circuit controls addressing of the memories for reading and writing so that conversion is performed between any high definition television format and the format required for a given high definition digital video tape recorder or any other comparable recorder.

Abstract: An image processing apparatus for storing image data into or from a frame memory is disclosed. The image data includes plural pieces of element data arranged in a matrix form of first predetermined numbers of rows and columns. The image processing apparatus includes a memory controller for controlling access to the frame memory for writing or reading the image data in or from the frame memory. The memory controller is configured to access the frame memory in either a raster unit consisting of one line of plural pieces of element data in the first predetermined numbers of rows and columns or a block unit consisting of plural pieces of element data arranged in a matrix of second predetermined numbers of rows and columns. The second predetermined number is smaller than the first predetermined number. A raster access address generator is connected to the memory controller and generates a raster access address for accessing the frame memory to write or read the image data in the raster unit.

Abstract: Reverse playback of MPEG video from a random access source takes advantage of the symmetry of B frames within an IB data stream. The IB data stream is processed by a parsing algorithm to identify within the B frames during playback those bits associated with motion vector identification and values to develop a parsed B frame table. When the IB data stream is output from the storage source for reverse playback, the IB data stream is rearranged into a reversed IB data stream. As each B frame is processed prior to input to an MPEG decoder, the parsed B frame table is used to manipulate the appropriate bits within the B frames to turn forward motion vectors into backward motion vectors, and vice versa. Then when the B frame is decoded by the MPEG decoder the respective motion vectors are associated with the appropriate I frames within the reversed IB data stream to produce accurate decoding of the B frames during reverse playback.

Abstract: In order to increase a coded data buffer size and provide an OSD area within a 16 Mbit memory for picture signals of NTSC and PAL systems, a display data area of the memory is made 2(N+1)/4N times a frame when a picture size is large.

Abstract: An image data recording method in a digital still video camera capable of selecting one of the single shot mode for photographing and recording only a single image and the sequential shot mode for sequentially photographing and recording a plurality of images comprises the steps of distinguishing whether a recorded image was photographed in the single shot mode or in the sequential shot mode, giving a file name correspondingly to the photographed image, and recording the photographed image. File names for each single shot image may be stored at a given hierarchy level. A name (e.g., a subdirectory name) representative of a plurality of sequential shot images may be stored at the same level as the single shot file names and file names of the sequential shot images stored under the representative name at a different hierarchy level.

Abstract: A full-search block matching motion estimation processor includes a memory management unit for buffering search data of a (2P+N).times.(2P+N) search area, and a processor element array unit. The search area is divided into rows of the search data, and the memory management unit has N output bus lines and sequentially outputs the rows of the search data at the output bus lines. The processor element array unit includes an array of processor elements, each of which has at least one reference data input, at least one search data input connected to one of the search data inputs of the processor elements on the same row of the array and further connected to one of the output bus lines of the memory management unit, a partial sum output, and a partial sum input connected to the partial sum output of a preceding one of the processor elements on the same row of the array.

Abstract: A random access memory of a digital video decompression processor is mapped to enable the reconstruction of successive video frames of pixel data represented by a compressed video bitstream. A FIFO buffer is provided in the RAM for the compressed video bitstream. A first luminance anchor frame buffer and a first chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B-frames. A second luminance anchor frame buffer and second chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict the B-frames. A first B-frame luminance buffer is provided in the RAM and sized to store less than 100% of the amount of luminance data in a first B-frame field. A second B-frame luminance buffer is provided in the RAM and sized to store at least 100% of the amount of luminance data in a second B-frame field.

Abstract: A hierarchial search for moving image encoding determines a motion vector by comparing a target block to sets of blocks selected according to the results of previous comparisons. Typically, each set of blocks includes a central block and four blocks offset on x and y axes. Blocks most similar to the target block provide co-ordinates of a center block in a next stage of the search. The hierarchial search searches regions indicated by previous comparisons to be similar to the target block and thereby reduces the number of comparisons and the search time required to find a motion vector. A motion estimation circuit for the hierarchial search includes: five processing elements which compare the target block to five blocks; a first memory that asserts a target block pixel value to the processing elements; a second memory that asserts five search window pixel values to the processing elements.

Abstract: A method and apparatus for a computer graphics system identifies the format of video pixel data in a data stream having a plurality of data formats including a first pixel data format and a second pixel data format, the second pixel data format being a YUV format. The method comprises the steps of (a) receiving pixel data; (b) selecting an output channel in response to at least one particular value of at least one bit of each received pixel datum wherein the particular value identifies the data format as either the first pixel data format or the YUV format; and (c) providing the pixel data to the selected output channel. Also provided is a circuit in a video graphics controller and a computer system having such circuit according to the method.

Abstract: A conventional definition camera acquires video data relating to a portion of an image to be televised and stores the data in a higher definition capacity store. The camera is panned and tilted to acquire data relating to other parts of the image. A motion detector determines the degree of movement of the camera and controls the writing of data to the store. A spatio-temporal interpolator interpolates the video data to correct for spatial or sensitivity incompatibilities. The output from the store may again be spatio-temporally interpolated by an interpolator under control of the motion detector to compensate for movement within the image to be televised. In a further embodiment image data is acquired by a plurality of overlapping lower definition sources.

Abstract: A method and apparatus for efficient motion vector detection is disclosed that provides an expanded search window with a plurality of motion processors. The internal search window of each motion processor is arranged as a set of N row by M column rectangular subblocks. An address generator circuit scans a stream of pixel data values out of a reference frame memory while a set of delay circuits route the stream of pixel data values to the input paths for the internal subblocks and match input timing for the motion processors.

Abstract: An improvement in solving the problem of the wraparound state. A moving image is coded in an encoder. The resulting coded data is supplied to a buffer through a multiplexor and stored in the buffer. The address used for storing the coded data in the buffer is generated in an address controller. The coded data supplied from the encoder is combined with the address in the multiplexor in a multiplexing manner.

Abstract: An apparatus for decoding an encoded digital video signal for the reproduction of an original video image signal comprises an image data partitioning circuit for dividing difference pixel values on the basis of the current macro block into four equal-sized current subblocks, motion compensation units and a formatter for providing predicted current macro block data, adders for providing the reconstructed current macro block signals by combining the predicted current macro block data and the difference pixel data. The motion compensation units have four memories for storing the reconstructed current macro block signals as the divided previous subblock data.

Abstract: A temporally-pipelined predictive encoder/decoder circuit for encoding or decoding an input signal containing a sequence of data frames received at a particular frame rate and frame data rate into an output signal having an equal frame rate employs a plurality of N predictive encoders/decoders. An input buffer may be used to extract the information for each data frame in the input signal and supply such information to a corresponding one of the encoders/decoders at rate of 1/N of the particular frame data rate. Each encoder/decoder generates corresponding encoded/decoded information as it is received as well as provides digitized frame information to the encoder/decoder processing the next received image frame. The encoded/decoded information is provided to corresponding frame buffers which temporarily store such information.

Abstract: The invention concerns the simultaneous display of video data and text data on a computer display. The invention stores both types of data in display memory. Transition codes mark the separation between the two types. The invention converts each type of data into signals which a CRT display can understand. The invention changes the type of conversion, as appropriate, when transition codes are reached.

Abstract: In a Video processor, an analog composite video signal is converted by an A/D converter (10) to a digital bit sequence in response to a system clock pulse. By using the system clock pulse and horizontal and vertical synchronizing pulses separated from the composite signal, a horizontal blanking interval and a vertical blanking interval are detected by control circuitry (21.about.24) and the read/write operations of a field memory (12) are disabled during the horizontal and vertical blanking intervals and enabled at other times. The picture information from the memory is converted by a D/A converter (13) to analog form in response to the system clock pulse. A multiplex of a digital pedestal level signal and a digital synchronization level signal is supplied to the D/A converter (13) when the memory is disabled.

Abstract: An image motion compensating address generator is disclosed including a mode selector for selecting a field mode or frame mode according to a video mode signal and a slice position signal, an address selection controller for controlling the generation of addresses according to the video mode signal and a motion coding type signal, a Y-direction read address generator for producing a Y-direction read address in units of processed block, an X-direction read address generator for dividing the processed block into four phases in the X direction and generating an X-direction read address, an X-direction write address generator for delaying the processed-block position signal and a field processed-block clock signal, and generating the X-direction write address of four phases, a Y-direction write address generator for producing a Y-direction write address, and a read & write controller for selectively outputting the X-direction and Y-direction read and write addresses according to a read/write selection toggle sign

Abstract: There is provided an image memory system of a solid-state camera in which a solid-state memory device which is divided into a plurality of memory areas is used as an image recording medium, wherein digital data of one pixel is supplied in parallel to the solid-state memory device and recorded into the individual memory areas in the solid-state memory device every bit, one of the memory areas is selected, and binary image data is written into the selected memory area. With the system, a variety of image data can be stored at a high speed in the serial copy mode or document mode without sacrificing the serial copy speed.

Abstract: A structure and a method for providing a video signal encoder under the MPEG-1 and MPEG-2 standards are provided. In one embodiment, a novel scheme for mapping an image to an external memory allows fetching of video data by either field of frame. In addition, an automatic reload of a DMA channel memory allows automatic fetching of an entire 20.times.20 luma reference picture area, or a 12.times.12 chroma reference picture area, while crossing the minimal number of DRAM page boundaries. A novel dequantization instruction in the CPU of the video signal encoder allows efficient oddification of DCT coefficients according to MPEG-1 and MPEG-2 standards.