Abstract: A memory allocation method and apparatus is disclosed in which the macro blocks are grouped into a plurality block sets and stored in the memory as block set. By grouping and storing the macro blocks, an efficient reading of the data is achieved.

Abstract: A device for transferring serial data includes a first temporary memory for temporarily storing the serial data supplied from an input terminal; a first-memory for storing the data supplied from the first temporary memory; a second temporary memory for temporarily storing the serial data supplied from the input terminal; a second memory for storing the data supplied from the second temporary memory; a first transfer state detecting circuit for generating a first control signal indicative of that the serial data supplied from the input terminal is being transferred, a second transfer state detecting circuit for generating a second control signal indicative of that the serial data supplied from the input terminal is being transferred; a control circuit for deciding that the first and the second control signal have not arrived in response to the arrival of a transfer command signal, thereby transferring the data from the first temporary memory to the first memory and transferring the data from the second tempora

Abstract: An image processing device comprises an SIMD (Single Instruction stream Multiple Data stream) calculating unit (101) for performing operations, such as motion compensation, motion prediction, DCT (Discrete Cosine Transform) processing, IDCT (Inverse Discrete Cosine Transform) processing, quantization, and reverse quantization by means of a pipeline operation unit that can be program-controlled by an outside unit, a VLC (Variable Length Code) processing unit (102) for performing variable-length encoding processing and variable-length decoding processing according to a given encoding method, an external data interface (103) for performing a data transfer between the image processing device and an outside unit, and a processor (105) for decoding an instruction held by an instruction memory (104), and for performing a programmed control operation on the SIMD calculating unit (101), the VLC processing unit (102), and the external data interface (103).

Abstract: This invention discloses a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image. The DRAM includes two separate banks, a first bank and a second bank. Each bank is capable of operating in page mode to read and write the data words. The two dimensional image is organized in a two dimensional grid pattern of cells, each cell containing an M by N matrix of pixels. The words associated with each cell occupy one page or less of a bank. Each cell is assigned a particular one of the two banks so that all data words associated with that particular cell are read from and written to one particular page of that particular bank. The assignment of banks to cells is done such that each cell is associated with a different bank than any bordering cell which is also either in the same row or in the same column.

Abstract: An image processing apparatus in which a time base corrector and an image coding apparatus are integrated so as to use a common memory, thereby realizing a simple circuit arrangement. The apparatus performs control of writing each line of input image data to an image memory in turn while reading image data from the image memory in predetermined coding units, in the following manner: when a picture of the image data has been written, if the number of data units, each corresponding to the coding unit, is equal to or below a first threshold, then a picture is skipped in the image data writing operation, and when a picture of the image data has been read, if the number of written lines is equal to or below a second threshold, then the same picture is again read in the image data reading operation.

Abstract: A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Abstract: A video decoder for decoding data at a high rate uses a plurality of slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices are allocated to decoders optimally in response to busy signals providing improved performance over known methods. The invention decodes HDTV signals using a plurality of ordinary television resolution decoders. Multiple data streams are also decoded.

Abstract: During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient capacity to store complete video pictures do not have the necessary access time to perform image processing in real time. The invention therefore provides for the writing of picture blocks from a picture memory to a fast access memory. Only the pixels in the access memory are accessed when the image processing operation is performed. During the read-out, a further block from the picture memory is simultaneously read into the access memory. As a result, fast access to the picture data is possible in conjunction with little additional outlay in respect to memory. Areas of application for the method are in the image processing of video pictures.

Abstract: A system which utilizes dual-port memory to seamlessly display video frames on a raster scanned display device. Dual port memory is partitioned into a ‘single frame buffer’ having sufficient capacity to buffer a full video frame, and an ‘extension buffer’ which is a contiguous extension of the single frame buffer. The two sections together comprise an ‘extended buffer’. As long as the video memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using the single frame buffer for each frame. When the write and read addresses are closer than a predetermined number of lines, the incoming video data for the next several new frames is written using the ‘extended’ buffer, and also read therefrom. After the write and read addresses are again sufficiently separated, video data is written and read using only the single frame buffer.

Abstract: The memory (MM) is addressed, depending on the format, with address words (MDC) formed at least from the high-order bits of the identifier (ID) of each cue, and possibly padded out with check or selection words (MS) making it possible either to designate consecutive addresses or to select some of the latter from each memory cell (CM) depending on the low-order bits of the identifier. This allows continuous addressing of the memory irrespective of the format used, thereby optimizing the memory size and avoiding a structural or software modification of the addressing system with each change of format.

Abstract: A system and method for decoding and displaying a video bitstream representing video images and displaying the video images. The present invention discloses a split memory manager design which is particularly adapted to display MPEG-2 format video images. In addition, the present invention discloses a novel way of managing the video memory used in a video decode and display system. Finally, an intraframe video data compression system and method is disclosed to complement the disclosed video decoding and displaying system.

Abstract: It is disclosed herein that a system for reducing video data memory in VGA-to-TV converters that convert computer video signals to TV compliant signals for display on regular TV screens. By closely tracking two pointers, one being a write pointer responsible for writing incoming video data into the video data memory and the other being a read pointer responsible for reading out the stored video data in the video data memory, the memory is efficiently used for buffering the video data. To ensure that the read pointer always retrieves the valid video data at its own speed, an address monitoring process is provided to monitor the address difference between the write pointer and the read pointer. When the monitoring process detects that the read pointer may soon surpass the write pointer, a control process is placed on the write pointer to prevent the read pointer from passing over the write pointer.

Abstract: The present invention provides a video encoding apparatus including a video processor for performing video processing on input video data, a variable length encoder for performing variable length encoding on the processed (quantized) video data and for supplying the encoded data and a generated bit quantity, a DRAM for storing the encoded data that is output as a bitstream, a bitstream output circuit for computing, based on a value found by subtracting the generated bit quantity from a set bit quantity predetermined in advance, a period taken to read from the DRAM the bitstream and for outputting the bitstream as output video data in the computed period, and an arbiter for controlling the operations of the video processor, the variable length encoder, the DRAM, and the bitstream output circuit.

Abstract: A video server with a file storage system for a disk drive in which the disk is logically divided into radial zones and sequential portions of files are stored in different zones according to a predetermined order of zones so as to reduce the average seek time during interleaved access to multiple files. When two files are stored with sequential portions of a first file located sequentially around the inside radius of the R/W surface and sequential clusters of a second file located sequentially around the outside radius of the R/W surface and the clusters of the files are read interleaved (taking turns) then the average seek time for reading the files is approximately equal to the maximum seek time. When the sequential clusters of the files are intentionally dispersed in a pattern in the zones, then the average seek time for reading the files is approximately 1/2 the maximum seek time.

Abstract: A video camera comprises a solid state image pickup device, a pulse generator to supply a transfer pulse to read out signals of the solid state image pickup device, A/D converters to convert the signals read out from the solid state image pickup device into the digital signals, and a dynamic RAM which operates in the high speed page mode to store the digital signals. The video camera has a reading circuit in which the time which is required to read out at least one line of the solid state image pickup device is shorter than the maximum permission time to write into the same RAS address in the high speed page mode and the period of the transfer pulse is an integer times as long as the period of the original oscillation clock of the pulse generator.

Abstract: A decoder system is provided for decoding an input video signal. A buffer memory hold slices of reconstructed B-pictures for display. The decoder is controlled in accordance with an amount of available memory in the buffer (the amount of available memory in the buffer depends both on how much data has been decoded and also upon how much data has been displayed). In addition, a buffer memory input controller controls into which locations of the buffer memory the slices of the reconstructed B-pictures are stored. As a result, only 2.53 frames of buffer memory are required.

Abstract: A decoding apparatus decodes efficiency coded picture data. The efficiency coded picture data are first decoded per predetermined picture unit, such as slice. The decoded picture data are stored into a memory. Writing and reading to and from the memory are controlled as follows: A writing operation of a first picture unit to the memory starts when a reading operation of a second picture unit from the memory is finished. Here, the second picture unit precedes the first picture unit and display locations of the first and second picture units are identical to each other. The writing operation goes into a waiting mode while the reading operation is being executed.

Abstract: A system and method for decoding fixed length data words comprising variable length objects is disclosed having the ability to decode a variable length DCT in every clock cycle. The system includes multiple floating point registers, preferably two, for holding the fixed length data words, and a tracking arrangement, including a summation block and a total used bits register, where the summation block sums bits used for each variable length object with the contents of the total bits used register to form the total number of used bits. The total used bits are fed back and summed within the total used bits register.The system also has a rotating shift register, which is a circular buffer, and a multiplexer arrangement which transfers variable length objects from the floating point registers to the rotating shift register. The tracking arrangement counts the bits used in transferring variable length objects to the rotating shift register.

Abstract: The present invention relates to a method for regulating, in the read mode, memory areas of a circuit for decompressing a video data flow compressed according to an MPEG standard, with respect to the writing rate of the compressed data flow into the memory areas, the decompression circuit issuing a flow of image data at the rate of signals for horizontally and vertically synchronizing the images issued by a circuit for coding according to a color television standard, this method including generating a clock signal having a fixed frequency for reading from the memory areas and for generating the horizontal and vertical synchronization signals, and shifting the occurrence of an edge triggering the vertical synchronization signal based on a signal indicative of the state of a buffer memory associated with the memory areas.

Abstract: A memory controller for controlling accesses to a memory storing display entities including network application data displayed on a display screen of a television system. For performing a display screen refresh operation, the network application data is retrieved with a predetermined period. Accordingly, the memory controller determines an expected time for receiving the next request for retrieving the network application data for screen refresh. The memory controller blocks any lower priority memory access requests from a few clock cycles prior to the determined expected time. As a result, the requests for retrieving network application data can be serviced in an acceptable time.

Abstract: A memory controller for controlling accesses to a memory storing display entities including network application data displayed on a display screen of a television system. For performing a display screen refresh operation, the network application data is retrieved with a predetermined period. Accordingly, the memory controller determines an expected time for receiving the next request for retrieving the network application data for screen refresh. The memory controller bolcks any lower priority memory access requests from a few clock cycles prior to the determined expected time. As a result, the requests for retrieving network application data can be serviced in an acceptable time.

Abstract: A system and method for altering the appearance of interference in a video signal caused by spurious interference generated by repeated high speed digital memory write operations affecting video processing in analog circuitry in thereceiver. In one particular embodiment, a picture-in-picture television receiver is provided wherein both the main and sub-pictures are processed on a single IC including analog processing circuitry, as well as a small picture memory array to which small picture video samples are repeatedly being written. The visibility of spurious interference in the picture is reduced by periodically altering the clock timing during the repetitive high speed writing operation to redistribute the interference so as to be less noticeable to the television viewer.

Abstract: Memory addressing apparatus and method for block scan and raster scan in an apparatus for processing image data of which the horizontal resolution is H and the vertical resolution is V. The memory addressing apparatus includes a horizontal counter for outputting a value sequentially incremented by a write or read signal for storing or reading image data in or from the memory, a vertical counter for outputting a value sequentially incremented by a horizontal synchronizing signal included in the image data, and an address generator for generating an address for raster scan or block scan according to a control signal by the horizontal and the vertical count values. Accordingly, memory address generating functions for raster scan and block scan are integrated into one unit, thereby the amount of required hardware is reduced, and simple design and structure of the apparatus reduce manufacturing cost.

Abstract: A digital video disk reproducing device utilizes a single memory both for error correction and for data buffering. The device designates a unit number to each sector of the memory and determines first, second and third regions. The first region corresponds to an absolute value of a unit number obtained by subtracting a unit number Y of a sector where a data read/write operation is completed during the descrambling from a unit number X of a start sector in an error correction block where the error correction is completed. The second region corresponds to an absolute value of a unit number obtained by subtracting a unit number Z of a sector where the data is completely transferred to the audio/video decoders or the ROM decoder from the unit number Y. The third region corresponds to an absolute value of a unit number obtained by subtracting the unit number Z from a unit number W of a sector where a writing operation of demodulated data is completed.

Abstract: A device for reversing an image of an object includes selector for selecting a reverse mode and control signal generator for generating a plurality of control signals. The control signal generator outputs a down-counting signal when the reverse mode is selected. A memory stores image data when the memory receives a store-enable control signal from the control signal generator and outputs the stored image data when the memory receives an output-enable control signal from the control signal generator. The device also includes an address generator for generating an address at which the image data is stored in the memory according to a control signal received from the control signal generator. During the reverse mode, the address generator generates an address to sequentially access the memory, beginning with a last address of the memory according to the down-counting signal.

Abstract: A video apparatus with image memory function has a memory of three ports (one for write, two for read), memory read control units corresponding to two independent read ports and adapted to read a desired area (first area) from a first read port and an area (second area) which contains the first area and is wider than the first area from a second read port, and a memory write control unit. With this construction, an input video signal is written to the memory, starting with a write head address designated by the memory write control unit, the first and second fields to be read during the next field are determined during the period of vertical blanking, a next write head address is determined to be after the first area, and a signal of the first area is delivered as an output video signal.

Abstract: A method and apparatus for single-buffered display capture which eliminates a "tearing" problem inherent in certain conventional video display techniques. A video signal including a sequence of frames each having an even field and an odd field is applied to a video capture circuit. First and second sets of lines each representing a different subset of all the lines in a given even or odd field are captured in the video capture circuit and displayed by a video display circuit. The video capture circuit captures the first set of lines in an even field of the video signal during a time period in which the video display circuit displays the second set of lines in the even field. The video capture circuit also captures the second set of lines in an odd field of the video signal during a time period in which the video display circuit displays the first set of lines in the odd field.

Abstract: A multi-channel memory system for holding video image data employs a particular form of interleaving in each channel to achieve optimum performance. Data representing luminance and chrominance components are written into the memory in respectively different channels such that the luminance information occupies one part of a memory row while the chrominance information occupies another part. The channel assignment is cycled within a memory row and is changed from one row of the memory to the next such that all luminance information in the row is contiguous and all chrominance information is contiguous yet luminance information and its corresponding chrominance information may be accessed in a single operation using all three channels. The memory is organized in three channels, each channel including two devices and each device including two banks.

Abstract: A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes various slave devices which access a single external memory, wherein these slave devices include reconstruction logic or motion compensation logic, a reference frame buffer, display logic, a prefetch buffer, and host bitstream logic, among others. Each of the slave devices is capable of storing or retrieving data to/from the memory according to different frame storage formats, such as a scan line format, a tiled format, and a skewed tile format, among others. The frame memory interface is easily re-configurable to each of these different formats, thus providing improved efficiency according to the present invention. The slave device then generates a request to the memory controller.

Abstract: A motion picture decoder uses a synchronous dynamic random access memory (SDRAM) as a frame memory in which the SDRAM is used, to store one frame of a video signal. By using an SDRAM which can operate at high speed, one frame of motion picture data is appropriately recorded in the SDRAM to enable rapid processing and complicated predictions of the motion compensation using the frame memory.

Abstract: A four-buffer MPEG decoder is provided for decoding MPEG video frames. A four-buffer frame controller and control method manage the four frame buffers including decoding, displaying and discarding of I-frames, P-frames and B-frames so that video data decoding is accelerated. The four-buffer frame controller and control method frees one frame buffer when the frame buffer contains obsolete data, defined as data which is no longer useful for decoding additional frames and for which storage is not necessary for displaying pictures in a correct temporal order. One example of an obsolete frame is a B-frame that is displayed. Another example is a P-frame for I-frame which is no longer used for motion compensation and has been displayed.

Abstract: According to an information signal correction processing apparatus of the invention which includes a plurality of clip circuits, a knee circuit, an adder, and a controller, an information signal which has been obtained through the clip circuits by clipping an input information signal in accordance with a plurality of clipping characteristics which have been arbitrarily set and an information signal which has been obtained through the knee circuit by voltage dividing the input information signal in accordance with a voltage dividing ratio which has been arbitrarily set are added by the adder and, when the resultant signal is outputted, the plurality of clipping characteristics and the voltage dividing ratio are respectively controlled by the controller, so that the information signal can be processed without being deteriorated.

Abstract: When a storage unit 18 records the title of a picture or the like with the ASCII codes along with the picture data and reads out the data for transfer. A DMAC controller 2a transfers the ASCII codes along with the picture data stored in a buffer circuit 22 in a lump to a frame memory 1 at a high transfer speed without interposition of a CPU 8. The memory controller 2 interprets the ASCII codes stored in the frame memory 1 to form picture data of letters or characters associated with the ASCII codes and writes the data in the frame memory 1. The picture data stored in the frame memory 1 is read out and routed to a monitoring device 15 so that the letters or characters associated with the ASCII codes are displayed along with a picture corresponding to the picture data.

Abstract: In a color image display system formed of a monochromatic CRT or like image display device (102) having a screen (103) for display of images and a rotary filter (106) comprising color filter sections (106R, 106G and 106B) of a plurality of colors; image signals are read from memories (130R, 130G, 130B) at a rate higher than they are written in the memories, so as to reduce flickers. The problem of passing of the reading address over the writing address is solved by reading the image signal of prominent color taking a period in which the passing over occurs. High frequency components of other color image signals are extracted and added to the image signal of each color to thereby enhance the definition of the picture.

Abstract: A B-frame processing apparatus including a motion compensation apparatus in the unit of a half pixel for an image decoder adapted to a video appliance such as HDTV. According to the apparatus, motion compensation in the unit of a half pixel is performed in real time with respect to the image having been motion-compensated by frame memories, the half pixel motion-compensated image data is added by an adder to the image data provided from a restoring section, and then the added image data is provided to the frame memories for performing motion compensation in the unit of a pixel, while the order of the input image is adjusted corresponding to the display order of the final output image.

Abstract: Pre-oddification of quantized discrete cosine transform (DCT) coefficients representing video data reduces high frequency noise that accumulates over multiple stages of encoding/decoding due to oddification in the decoders. The quantized DCT coefficients are inverse quantized, and the resulting inverse quantized coefficients are summed. If the sum is even, then the last quantized coefficient ?7,7! is adjusted to reduce high frequency energy accumulation at that coefficient. The last quantized coefficient may be set to zero, or may be incremented/decremented by "1" in the opposite manner than oddification occurs in the decoders. Further the values of a quantization matrix may be set, either manually or automatically as a function of the complexity of the video data, to assure that it is possible for the sum of the inverse quantized coefficients to be odd.

Abstract: A method for decoding and displaying video signals using a memory buffer, in which a speed of a write operation for a memory buffer is adjusted to avoid overtaking a read operation for the same memory buffer. A display controller and a video MPEG engine contend for access to a DRAM memory buffer controller, and have their relative priorities set so that the video MPEG engine operates to write to the memory buffer at a relatively slow speed during a time period when the display controller is reading from that same memory buffer, and to write to the memory buffer at a relatively fast speed during a time period when the display controller is not reading from the memory buffer. The relatively slow speed is preferably much slower than the reading speed of the display controller, while the relatively fast speed is preferably much faster than the display controller.

Abstract: An image processing apparatus for storing image data into or from a frame memory is disclosed. The image data includes plural pieces of element data arranged in a matrix form of first predetermined numbers of rows and columns. The image processing apparatus includes a memory controller for controlling access to the frame memory for writing or reading the image data in or from the frame memory. The memory controller is configured to access the frame memory in either a raster unit consisting of one line of plural pieces of element data in the first predetermined numbers of rows and columns or a block unit consisting of plural pieces of element data arranged in a matrix of second predetermined numbers of rows and columns. The second predetermined number is smaller than the first predetermined number. A raster access address generator is connected to the memory controller and generates a raster access address for accessing the frame memory to write or read the image data in the raster unit.

Abstract: An image processing apparatus, for an image recording and reproducing system, comprises a means for writing a given field image signal in a field memory, and a means for reading out the field image signal written in the field memory. The reading means reads out individual lines in sequence in a first field of the field image signal and also reads out a plurality of lines in a second field of the field image signal concurrently.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A high precision image signal is converted into digital data including a pedestal level and is written in a memory. An original frame is divided into a plurality of frames, and image data is read out from the memory for every divided frame. At the time of reading out of the image data on the left side of the divided frame, that image data is read out in the same order as the order of writing to the memory. At the time of reading out of the image data on the right side on the divided frame, that image data is read out in an order inverse to the order of writing to the memory. At the time of read out, the data of the pedestal level written in the memory is repeatedly read out, whereby a blanking period of the still video format is formed.

Abstract: Reverse playback of MPEG video from a random access source takes advantage of the symmetry of B frames within an IB data stream. The IB data stream is processed by a parsing algorithm to identify within the B frames during playback those bits associated with motion vector identification and values to develop a parsed B frame table. When the IB data stream is output from the storage source for reverse playback, the IB data stream is rearranged into a reversed IB data stream. As each B frame is processed prior to input to an MPEG decoder, the parsed B frame table is used to manipulate the appropriate bits within the B frames to turn forward motion vectors into backward motion vectors, and vice versa. Then when the B frame is decoded by the MPEG decoder the respective motion vectors are associated with the appropriate I frames within the reversed IB data stream to produce accurate decoding of the B frames during reverse playback.

Abstract: In a moving picture data decoding apparatus, the storage of reference picture data in a picture memory is executed by dividing the picture memory into two memory areas. An address generator generates an address so that the reference picture data adjacent to the division may be doubly written into the two memory areas. As a result, the processing can be effected in a predetermined access time period irrespective of the read-out location.

Abstract: A data collision avoidance circuit is utilized in a memory write control circuit of an image signal processing apparatus for preventing the write and read clocks of a FIFO memory from colliding. The circuit contains a write enable signal generating unit, a window pulse section set up unit, and a write enable signal control unit. The write enable signal generating unit generates a write enable signal in response to the write control odd/even field signal to write the data into the FIFO memory. The window pulse section set up unit generates a window pulse signal having a predetermined pulse width. The time interval of the predetermined pulse width is designed to be greater than a time interval during which write and read clocks of the FIFO memory can potentially collide, and the window pulse signal is generated in response to a read control odd/even field signal.

Abstract: In the motion prediction processor outputting the encoding type designating the inter-frame or intra-frame prediction coding and the motion vector in case of performing the inter-frame prediction coding, the coordinate values of the currently processed block are outputted and an offset is supplied to the address for reading out the reference region from the reference frame memory. The evaluation data for estimating the coding quantity in case of performing the inter-frame prediction coding is also outputted. An n number of the motion prediction processors are arranged and respectively associated with reference frame memories. The reference regions different from the same block are supplied to the n motion prediction processors and the motion prediction processor with the least evaluation data is selected from among the motion prediction processors whose reference regions are comprised within the picture. The motion vector outputted by the thus selected processor is corrected and outputted.

Abstract: The present invention is a system and method for retrieving segments of stored video programs using closed caption text data. The closed caption text data is extracted from video programming signals received by the invention. Text records based on the extracted closed caption data are generated. Each text record is derived from the closed caption data for a single continuous video segment to which the text record serves as an index or key in retrieving this video segment. Preferably, each text record (a) has sufficient content to adequately describe the content of the video segment to which it serves as an index; and (b) corresponds to a video segment focused on a small number of topics. To accomplish (a) and (b) the present invention generates each text record so that it has a predetermined maximum length and so that it is derived from the closed caption data for a single uninterrupted speaker.

Abstract: A video camera comprises a solid state image pickup device, a pulse generator to supply a transfer pulse to read out signals of the solid state image pickup device, A/D converters to convert the signals read out from the solid state image pickup device into the digital signals, and a dynamic RAM which operates in the high speed page mode to store the digital signals. The video camera has a reading circuit in which the time which is required to read out at least one line of the solid state image pickup device is shorter than the maximum permission time to write into the same RAS address in the high speed page mode and the period of the transfer pulse is integer times as long as the period of the original oscillation clock of the pulse generator.

Abstract: A computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed.

Abstract: In a color image display system formed of a monochromatic CRT or like image display device (102) having a screen (103) for display of images and a rotary filter (106) comprising color filter sections (106R, 106G and 106B) of a plurality of colors; image signals are read from memories (130R, 130G, 130B) at a rate higher than they are written in the memories, so as to reduce flickers. The problem of passing of the reading address over the writing address is solved by reading the image signal of prominent color taking a period in which the passing over occurs. High frequency components of other color image signals are extracted and added to the image signal of each color to thereby enhance the definition of the picture.