Abstract: In shuffling used as an efficient coding method for an input digital video signal, input digital television signals of different standards are judged in an input judging circuit, the judged information is sent out into a memory write control circuit and a memory read control circuit. The memory write control circuit determines the offset value of the vertical address according to the judgement signal, and writes the input signal at a position corresponding to the screen of the determined shuffling region of the shuffling range corresponding to each signal in the shuffling memory, or writes the block out of the shuffling range into the shuffling memory according to the specified control method in the vacant region of the shuffling range. The memory read control circuit changes over the offset value of the vertical address to be read out from the memory and the address control according to the judgement information.

Abstract: A simultaneous write/read control apparatus for a FIFO memory simultaneously controls write and read operations of video data constituting a video frame with an odd field and an even field. A control portion controls the write and read operations of the video data with respect to the FIFO memory and generates a first write enable signal. An unwritten interval signal generator uses information used for controlling the FIFO memory and generates an unwritten interval signal for preventing the video data from being written in the FIFO memory. A second write enable signal generator receives the first write enable signal and the unwritten interval signal from the control portion, and generates a second write enable signal which causes the input video data not to be written in the FIFO memory during an unwritten interval designated by the unwritten interval signal and causes the input video data to be written in the FIFO memory during the other intervals. The second enable signal is supplied to the FIFO memory.

Abstract: A method and apparatus are disclosed for interpolating pixels to obtain subpels for use by a video decompression processor. A prediction area is defined from which subpels are necessary to decompress a portion of a video image. Instead of reading all of the pixels from the prediction area and then processing them together to perform the necessary interpolation, portions of the pixel data are read and simultaneously averaged using in-place computation in order to reduce hardware requirements. Rounding of subpixel results is achieved using the carry input of conventional adders to add a binary "1" to the averaged pixels, which are subsequently truncated to provide the interpolated subpels.

Abstract: A video signal processing apparatus processes plural kinds of video signals and is used for displaying each one of the processed outputs of the plural kinds of video signals on the same screen. In the video signal processing apparatus, a memory used for a subtitle processing circuit and a memory used for a helper signal separation circuit are used in common by providing a switching means to switch according to an input video signal. A subtitle processing circuit magnifies a video signal with a letter box format such that a horizontally long picture is inserted in a picture with a 4:3 aspect ratio on a horizontally long screen with 2:1 or 16:9 aspect ratio. The helper signal separation circuit is used for receiving a television signal such as an EDTV 2 system which has a helper signal to improve picture quality.

Abstract: A structure and a method for providing a video signal encoder under the MPEG-1 and MPEG-2 standards are provided. In one embodiment, a novel scheme for mapping an image to an external memory allows fetching of video data by either field of frame. In addition, an automatic reload of a DMA channel memory allows automatic fetching of an entire 20.times.20 luma reference picture area, or a 12.times.12 chroma reference picture area, while crossing the minimal number of DRAM page boundaries. A novel dequantization instruction in the CPU of the video signal encoder allows efficient oddification of DCT coefficients according to MPEG-1 and MPEG-2 standards.

Abstract: A multiple video data bus architecture permits high speed data transfer among the various circuit elements of a fluoroscopic imaging processor. This permits simultaneous acquisition, storage, display, and image enhancement of high resolution, i.e., 2K.times.2K images. A memory interface circuit compresses the video data for storage in bulk memory. The processor supports several high-resolution monitors which can respectively display radiographic images from different subjects, so that review and diagnosis can occur remotely.

Abstract: A system for converting a digital input signal having a vertical and horizontal dimension into a digital output signal having a different horizontal and vertical dimension than that of the digital input signal. The digital input signal is fed into a first memory which stores the input signal. A horizontal resampling filter is used for converting the horizontal dimension of the digital input signal to the horizontal dimension of the desired output signal. The output from the horizontal resampling filter is transposed so that the vertical dimension of the output signal is oriented in a horizontal orientation. The transposed signal is then stored in a second memory. The transposed signal with the resampled horizontal dimension from the second memory is fed into a vertical resampling filter which converts the vertical dimension information of the transposed signal to the desired format of the output signal.

Abstract: A method for organizing and addressing memory of a digital video image is provided for one and two dimensional image processing using fast page mode accessing of memory, and also for displaying composite digital video images. A DRAM (12) is mapped to address locations storing segmented memory, non-segmented memory, line pointer tables, and horizontal description tables. The lines of a digital image are organized in DRAM (12) in either segmented memory or non-segmented memory. For segmented memory, each line of the image is broken up into equal line segments of pixels. Vertically aligned columns of line segments in the image are then stored in one or more rows of the DRAM (12). For non-segmented memory, each line is stored in a format where rows of DRAM (12) each represent a line of image data.

Abstract: An architecture for a memory with a wide word, e.g. n-byte, width particularly suited for use as a high definition video frame store memory (80), and an accompanying organization for storing pixel data therein to facilitate efficient block and raster access therefrom. Specifically, the memory relies on storing n-byte wide words (n=(m.sub.1 .times.m.sub.2)) across m.sub.2 independent m.sub.1 -byte wide memory segments, with pre-defined positional offsets between respective m.sub.1 -byte words (203)("nibbles") stored in successive memory segments. All these segments are simultaneously accessed on a read or write basis. During a memory write operation, all the nibbles in an n-byte wide input word are appropriately shuffled to yield the proper inter-segment offsets prior to being written into the memory as a collective n-byte memory write word. During a read operation, all the nibbles read from memory in a collective n-byte memory read word are appropriately shuffled to yield an n-byte output word.

Abstract: A television signal receiving system includes a deinterleaving network (18) containing first and second deinterleaving functions associated with respective memory address controllers (20, 25). One or the other of the deinterleaving functions is selected for use by a multiplexer (30) in response to a Deinterleaver Select control signal. Deinterleaving is accomplished by controlling the read/write addressing of a memory (35) by the selected deinterleaving function.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A television receiver equipped with an internal device produces a deferred source signal in order to alter the amount (X) of deferment in order to allow for a replay or skipping of a portion of a program being viewed. The change in deferment is followed automatically by a resumption of the initial value of deferment. This allows for instant replay or fast forward and subsequent return to the initial condition in an automatic manner.

Abstract: A storage mechanism utilizing a single data recorder from which multiple channels of compressed video data may be simultaneously accessed. The data access to and from the data recorder via a single data access path takes place at a higher data rate (f.sub.1, f.sub.2) than the data rate (f.sub.3, f.sub.4) at which that compressed data needs to be decoded to support a video signal. A video router is used to direct the reproduced data stored within two data channel buffers to respective JPEG decoders where they are decompressed into a signal suitable for driving two digital monitors. In operation, a segment of compressed video data for one channel is recovered from the data recorder and stored within one of the buffers from which it is continuously read at a lower data rate (f.sub.3, f.sub.4). The data recorder then cues to another part of the medium from which data for the second channel is reproduced and stored within another buffer. The process is then repeated.

Abstract: An image processing memory integrated circuit used for a signal processing circuit is disclosed. In the bidirectional prediction, pixel values for two-frame images are stored in a memory cell array. The stored pixel values are read on the basis of address of two-dimensional block. The read pixel values of the two images in the block are added by an adder at an appropriate ratio. The resulting inter-image prediction signal and the interpolation signals are outputted to the outside. In the unidirectional prediction, pixel values for one-frame images are stored in a memory cell array. From the memory cell array, pixel values of two-dimensional block expanded from the above-mentioned block are read. The read pixel value is adaptively added to the pixel value delayed by a predetermined number of pixel from the read pixel value through an adder at an appropriate ratio.

Abstract: An adapter for use in a multi-media workstation includes a device which accepts real-time video information at a first size, reduces the size to a selected one of a plurality of available sizes and places the reduced real-time video information into a selected area of the video memory of a computer graphic display device. Thereafter, the scaled real-time video information is displayed with other computer graphics applications, in a sub-window of the screen of the display device.

Abstract: A motion estimation coprocessor for use in a video data system. The motion estimation coprocessor may be used with a video memory that subdivides a P row.times.Q column image of pixels into several pages. The page structure enables efficient loading of video data into the coprocessor. The motion estimation coprocessor may perform several block matches simultaneously. The motion estimation coprocessor may perform exhaustive block matching or use a hierarchical search.

Abstract: A process for synchronizing a scanning circuit of a device for the display of images acquired by a camera having a scanning circuit controlled by a given acquisition clock. The device comprises an input buffer, a processor making it possible to reconstitute each image entering the buffer, a display store in which the images are recorded after processing and a controller able to control the reading or writing of the images in the display store. The process is characterized in that it consists of applying to the scanning circuit an arbitrary clock signal independent of the image synchronization of the signal received. Also, the reading and writing of the display store is controlled in order to obtain repetitions or suppressions of images on display thus absorbing any delay or advance. Further, the processor should have a faster than necessary image compression (average time of one image).

Abstract: A digital television receiver having an STM memory is provided with a receiving unit to receive a broadcasting signal, a producing circuit to produce an image signal and a voice signal from the received broadcasting signal, a memory which is used to record the image signal and the voice signal and has a plurality of probe electrodes and a recording medium arranged so as to face the probe electrodes, a display for converting the image signal outputted from the memory into the video image, and a speaker for converting the voice signal outputted from the memory into the voice sound. The memory further has a voltage applying circuit for applying a voltage to the portion between each probe electrode and the recording medium. The image signal and the voice signal are digital signals.

Abstract: A video signal processing apparatus for processing a video signal having: a memory circuit for receiving a video signal and storing received video signal; a synchronization signal separation circuit for separating a synchronization signal included by the received video signal, and transmitting the synchronization signal; a first counter for transmitting count data by performing a counting operation in synchonization with the synchronization signal transmitted from the synchronization signal separation circuit or by spontaneously performing the counting operation; a second counter for transmitting count data by spontaneously performing the counting operation; a memory control circuit for controlling writing or reading of the video signal to and from the memory circuit in accordance with the count data transmitted from the first counter; a first decoder for resetting the second counter in accordance with a value denoted by the count data transmitted from the first counter; and a second decoder for resetting the

Abstract: A spatial light modulator array with adaptable multiplexed memory architecture. The modulator has an array of individually controllable pixels, where a predetermined number of pixels are assigned to a memory cell (16). The memory cell receives data from an input bus (14). On a signal (22), the memory cell transfers its data to a secondary memory (18), and to the activation circuitry (20) of one of its assigned pixels. On a second signal, the pixel responds to the data on the activation circuitry. When the display time of the data is less than the load time for the memory cell, the secondary memory is set with a second signal (24) so as to make the pixel dark and another control signal makes the pixels respond to the memory. In this way, the load time is lengthened and the data rate remains relatively low, even though the number of bits of intensity may not be the same as the number of bits of intensity used to determine the number of pixels assigned to each memory cell.

Abstract: In an image processing device, an analog-to-digital converter (ADC) transforms an image generated by an imaging device and having a high pixel density to a corresponding digital image signal. A YC processor processes the digital image signal to output an image signal in the form of a luminance signal and chrominance signals. A memory controller includes an address generator capable of generating a particular address signal for thinning, or reducing, the image signal. The address signal is fed to a frame memory. When the image signal is written to or read out of the frame memory, an image represented by the image signal is thinned by the address signal. The thinned image data are coded by a compander and then written to a memory card or reproduced by a playback circuit. The reproduced image signal appears on a video monitor or similar display.

Abstract: A video motion compensation apparatus comprising an X-read address generation circuit for generating X-read address components in response to a macro block address and an X-motion vector component, a Y-read address generation circuit for generating a Y-read address component in response to a macro slice address and a Y-motion vector component, a write address generation circuit for generating X and Y-write address components in response to the macro slice address and the macro block address, a multiplexing circuit for multiplexing the Y-read address component, the X-read address components and the X and Y-write address components to generate read and write addresses of first and second frame memories, and a data processing circuit for reading video data from a location of one of the first and second frame memories corresponding to the read address from the multiplexing circuit, adding the read video data to inverse discrete cosine transform video data and writing the resultant video data into a location of th

Abstract: A memory device for a digital video system, capable of receiving video data in a packed format and transmitting that video data in a planar format. In other operating modes, the memory device receives video data in various packed formats and transmits that video data in a packed format. The memory device is suitable for a flexible digital video system in which video data may either be displayed in real time as it is generated (using packed format data) or compressed for storage and future display (using planar format data).

Abstract: A method and system for compressing color video or other image data for transmission over a low cost, low bandwidth bus (or other transmission link). Preferred embodiments implement lossless compression and include a frame buffer for storing data compressed in accordance with the invention, and circuitry for decompressing and transforming compressed data read from the frame buffer. The image data are typically organized as a sequence of frames, each comprising a sequence of pixels. Data compressed in accordance with the invention are stored in cells in memory, with each cell storing the same number of pixels. The inventive method is denoted as "cell based image compression" ("CBC"). Advantages of CBC include increasing available data transmission bandwidth and lowering required system power as a result of minimizing transfer of redundant color information to and from memory as well as fast random single pixel reads and writes.

Abstract: Apparatus for processing a video signal representing distribution of optically-perceptible information over a video raster includes a video combiner for receiving an input video signal and a delayed video signal and combining the input video signal and the delayed video signal to provide an output video signal. A memory receives and temporarily stores the output video signal and provides the delayed video signal, and read/write circuits access the memory so that pixels of the output video signal are spatially translated relative to the video raster when the output video signal is written into and read from the memory.

Abstract: A motion estimation coprocessor for use in a video data system. The motion estimation coprocessor may be used with a video memory that subdivides a P row.times.Q column image of pixels into several pages. The page structure enables efficient loading of video data into the coprocessor. The motion estimation coprocessor may perform several block matches simultaneously. The motion estimation coprocessor may perform exhaustive block matching or use a hierarchical search.

Abstract: A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control.

Abstract: A microcomputer-controlled electronic device such as a video camera has a signal processor for processing an input signal supplied thereto. The signal processor is controlled by a system controller comprising a microcomputer. The system controller supplies a test signal, read from a memory, to the signal processor, and receives a processed test signal from the signal processor. The system controller also assesses the processed test signal from the signal processor for adjustment of the signal processor based on a command from an adjusting device connected to the video camera, while at the same time controlling operation of the signal processor.

Abstract: An image data storage/processing apparatus is provided, which is particularly applicable to an electronic still camera, for example. The image data storage apparatus uses a dynamic RAM as a frame memory for temporarily storing image data representative of a field of an image to be recorded. The frame memory includes at least first and second memories. In the apparatus, there is provided a control so that the image data corresponding to the adjacent two pixel lines on the field are continuously read out in such a manner that they are simultaneously read out from the first and second memories, and the image data corresponding to one of the two pixel lines are read out with delay by the time required for reading out of the image data corresponding to the other pixel line. The image signal processing apparatus is capable of performing processing for writing in and reading out of various types of image data with a single memory.

Abstract: In a picture encoding apparatus, detection of a moving vector of half-pixel precision is executed by using a single clock without increasing the number of frame memories. Time-series input pixel data is transformed into parallel pixel data; the parallel pixel data obtained through the transformation is interpolated to thereby generate interpolating data on each pixel in an area specified by a moving vector of one-pixel precision. The interpolation data is output in parallel as pixel data on a plurality of interpolation block areas obtained by displacing by 1/2 pixel the block area specified by the moving vector at one-pixel unit, thereby making it possible to quickly obtain interpolation data solely on a region around the area specified by the moving vector at one-pixel unit.

Abstract: A scheme is provided for processing previous frame data in a motion compensated digital video system to interpolate pixels used in reconstructing a current video frame. Pixel data from a previous video frame is arranged into sub-blocks containing a plurality N of pixels. The sub-blocks are stored in a memory to enable the retrieval of at least one sub-block per memory access cycle. A plurality M of sub-blocks are retrieved from the memory in response to a displacement vector associated with a portion of a current video frame. M is less than or equal to N and the M sub-blocks are retrieved in no more than M memory access cycles. A subset of pixels is chosen from the selected plurality of sub-blocks for use in interpolating pixels for the current video frame portion. The subset of pixels is processed over no more than N memory access cycles to provide N interpolated pixels for the current video frame portion.

Abstract: A system and method are provided for encoding and decoding data in a video processor system wherein image data values represent a plurality of successive images. A current image is stored into a block of memory locations and later read from the block of memory locations, encoded and transmitted. In addition to being transmitted, the encoded data values are also decoded in order to provide companded image values. The companded image values are then stored into the same block of memory locations as the current image. The data values representing the current image are simultaneously read from the memory block while the companded values are being stored into the same memory block under the control of a number of pointers and a number of synchronization flows. Additionally, the companded data values are simultaneously read from the same memory block for the purpose of performing motion estimation.

Abstract: A data converter for converting interlaced image data into a non-interlaced format is disclosed. The converter comprises a buffer memory capable of storing upto N such scan lines of the interlaced image data for performing, per input pixel clock pulse, a read and then a write operation, wherein the N represents the number of scan lines per field; a horizontal address generator for, upon receiving each of input pixel clock pulses, generating a horizontal address by sequentially counting the number of pixel clock pulses received after each of input H/SYNC pulses received; and a vertical address generator for generating, upon receiving each of the input H/SYNC pulses, generating one of a series of vertical addresses for outputting the interlaced image data in the non-interlaced format.

Abstract: Compressed image data received by a receiving circuit 11 is stored once in a buffer memory 12. When the quantity of the compressed image data in the buffer memory 12 reaches a predetermined quantity (for example, a quantity corresponding to one-fourth of compressed image data corresponding to one frame), the compressed image data is read out and is applied to an expanding circuit 13 to perform data expansion processing and then, the expanded image data is displayed on a monitor display device 18 through a video demodulating circuit 14. The above-mentioned operations are repeated, to sequentially display an image which is near completion. Consequently, an image can be partially reproduced and displayed even while the compressed image data is being received.

Abstract: If previously stored transmitters allocated to certain program settings in an entertainment electronics appliance are reallocated to the usual program settings, e.g., because of a changed transmitter distribution arrangement due to a change of location, time consuming reprogramming becomes necessary. The present invention concerns obtaining a simple sequencing process for reallocating previously stored channels to the desired program setting number. A microprocessor receives a command, and within a time window determined by the command, reads previously programmed data concerning two selected program settings from a main memory into a first auxiliary memory, and from this auxiliary memory into a second auxiliary memory, interchanging the channel numbers, and from the second auxiliary memory into the main memory again, so as to keep the same program numbers.

Abstract: A video field memory device for multi-broadcasting system employs upper and lower half memory cell arrays for storing a video signal according to the largest scanning bit and the largest scanning line of the multi-broadcasting system, and the upper and lower half memory cell arrays having the scanning bits of 1023.times.4 and the scanning lines of 313.times.4 corresponding to the largest one of various television broadcasting systems. Thus, the video field memory device for multi-broadcasting system for varying the scanning bits or the scanning lines can select a broadcasting system in a single chip by using a external TYPE signal, independent of the scanning bits or the scanning lines for each television broadcasting system.

Abstract: A video storage and synchronization system has one of more frame memories and an output buffer providing a selectable delay. Incoming video signals are digitized and routed to the memories and/or to the buffer. Stored signals are read out from the memories in synchronism with the incoming signals and can be mixed with the incoming signals before processing in the output buffer.

Abstract: An image coding apparatus for sequentially coding an input image signal that is supplied at a predetermined frame rate at a rate that is independent of such a frame rate, thereby obtaining a coding image signal for transmission from which frames are thinned out.

Abstract: A multiple serial access memory which includes a dynamic random access memory array is disclosed. The array is randomly addressed to input blocks of data. Address signals are provided to the array to output rows of data. A plurality of serial output ports are coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register having a length equal to the width of the memory array. The shift register is responsive to a first timing signal for latching a row of data from the array. A second timing signal actuates the shift register to shift a row of latched data. The serial access selector coupled to the shift register outputs a selected portion of the shifted data from the serial output port.