Abstract: A receiver apparatus includes: a broadcast receiver that receives a broadcast stream, a first time code being added to each first unit of first image data of the broadcast stream; a communication receiver that receives a communication stream via a network, a second time code being added to at least each first unit of second image data of the communication stream, the second image data being synchronized with the first image data and reproduced; a criterion time generator configured to generate criterion time; a time code processor configured to obtain the first time code added to the received broadcast stream and the second time code added to the communication stream at a predetermined timing, and to calculate an amount of delay of the second time code behind the first time code; and an adjuster configured to adjust the criterion time with reference to the amount of delay.

Abstract: Multi-threaded implementations of deblock filtering improve encoding and/or decoding efficiency. For example, a video encoder or decoder partitions a video picture into multiple segments. The encoder/decoder selects between multiple different patterns for splitting operations of deblock filtering into multiple passes. The encoder/decoder organizes the deblock filtering as multiple tasks, where a given task includes the operations of one of the passes for one of the segments. The encoder/decoder then performs the tasks with multiple threads. The performance of the tasks is constrained by task dependencies which, in general, are based at least in part on which lines of the picture are in the respective segments and which deblock filtering operations are in the respective passes. The task dependencies can include a cross-pass, cross-segment dependency between a given pass of a given segment and an adjacent pass of an adjacent segment.

Abstract: An application management server includes: a terminal management table storage unit configured to store terminal device identification data for identifying a terminal device and information indicating whether or not transmission of notification data is necessary while correlating the terminal device identification data with the information; a registration request reception unit configured to receive from the terminal device, a registration request for registering transmission of notification data, and update the terminal management table storage unit based on the registration request; a release request reception unit configured to receive from the terminal device, a release request for releasing transmission of notification data, and update the terminal management table storage unit based on the release request; a via-broadcasting notification transmission unit configured to perform a process of including notification data in a broadcasting signal and transmitting the notification data; and a via-communicatio

Abstract: A video input section acquires a video signal formed of a plurality of frames. A frame separator separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals. A plurality of parallel processors perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator. A frame combiner combines the separated video signals on which the plurality of parallel processors have performed the video processing.

Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.

Abstract: A segment allocation determination unit of an image decoding device determines an allocation of segments, in accordance with processing capabilities of the image decoding units, so that the processing times of the image decoding units are equal. When a first error detection unit detects an error, a segment allocation determination unit performs control so that the segment including the error is allocated to an image decoding unit to which a predicted reference image of the segment is allocated. When any of second error detection units detect an error, the segment allocation determination unit controls allocation of the next series of segments with consideration to a bit amount skipped due to the error. This enables providing an image decoding device that can efficiently realize decoding with a plurality of image decoding units even when an error is detected.

Abstract: Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.

Abstract: There is provided a video processing device capable of reducing the influence of a disturbance of an input vertical synchronization signal. When the synchronization signal detecting unit detects an input of the input-side vertical synchronization signal at a predetermined cycle, the synchronization signal control unit outputs the input-side vertical synchronization signal, which has been input, as an output-side vertical synchronization signal, and, when the synchronization signal detecting unit detects an input of a next input-side vertical synchronization signal before the predetermined cycle elapses after the output of the output-side vertical synchronization signal, a next input-side vertical synchronization signal input before the predetermined cycle elapses is not output as a next output-side vertical synchronization signal, and an input-side vertical synchronization signal input further next is output as the next output-side vertical synchronization signal.

Abstract: Embodiments of the present invention are directed to parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. One embodiment of the present invention is a family of video encoders and decoders (“codecs”) that can be incorporated within cameras, cell phones, and other electronic devices for encoding raw video signals into compressed video signals for storage and transmission, and for decoding compressed video signals into raw video signals for output to display devices. A highly parallel, pipelined, special-purpose integrated-circuit implementation of a particular video codec provides, according to embodiments of the present invention, a cost-effective video-codec computational engine that provides an extremely large computational bandwidth with relatively low power consumption and low-latency for decompression and compression of compressed video signals and raw video signals, respectively.

Abstract: A method and computer-readable medium for content adaptively decoding video content is disclosed. A computer-readable medium stores instructions for controlling a computing device to decode a bitstream encoded via a plurality of encoders. The bitstream is divided into portions and each portion has an associated model chosen from a plurality of predefined models. The instructions comprise routing each portion via an input switch to one of a plurality of decoders based on the associated model of the portion.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract: Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters.

Abstract: The focus position of each projection apparatus is changed depending on the configuration state of a projection system comprising a plurality of projection apparatuses.

Abstract: A synchronous, multi-stream decoder provides synchronous playback of multiple streams of encoded digital data (e.g., MPEG streams) for use with, for example, a digital video streaming tool. The decoder includes a parser and decoder for each stream and a decoder engine for determining a target time for the decoders to complete their respective decoding processes. A next target time is preferably computed during a pause of the parsers after a current target time has been reached. In one embodiment, a next target time is computed by computing an average of the differences of stored playback times of the last N decoded frame sets.

Abstract: A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an external memory system or local memories 204—0 to 204—3 according to a thread under control from a host processor. Processor units (PU) arrays 202—0 to 202—3 perform image processing by a different thread from the thread of the SCUs 203—0 to 203—3.

Abstract: The present invention provides a digital TV. The digital TV comprises a memory, a signal processing module, and a processor. The memory is for storing a regular program code. The signal processing module is for receiving and processing a data signal, and for generating an interruption signal. The processor coupled to the memory and the signal processing module is for receiving the interruption signal and reading the regular program code from the memory, and for executing the regular program code to realize functions of the digital TV. The memory is divided into a plurality of blocks, and the processor accesses the memory by block. Each block includes a first sub-block storing a specific program code. When the processor receives the interruption signal, the processor reads the specific program code of the first sub-block of the currently-accessed block and executes the specific program code.

Abstract: Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation, results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.

Abstract: A system and method are disclosed for receiving a group of video channels at a client device, selecting a display set from the group of channels, and sending a communication to a display for displaying each channel in the display set in parallel wherein each one of the channels in the display set is displayed in one of a plurality of picture in picture (PIP) displays for a predetermined time.

Abstract: Provided is a motion compensation method and apparatus. The motion compensation method includes performing register setting for motion compensation of an mth macroblock of a current image, performing prediction for the mth macroblock simultaneously with performing register setting for motion compensation of an (m+1)th macroblock, and performing reconstruction for the mth macroblock based on a prediction result simultaneously with performing prediction for the (m+1)th macroblock. By parallely processing motion compensation on macroblocks, the amount of time required for motion compensation of the macroblocks can be reduced.

Abstract: Direct macroblock mode techniques for high performance hardware motion compensation are described. An embodiment includes a hardware motion compensation graphics display device driver. More specifically, an embodiment mitigates a macroblock data parsing bottleneck in the display device driver by directly generating macroblock instructions and storing them in a dedicated buffer. For example, an embodiment includes an independent direct memory access instruction execution buffer for macroblock instructions separate from the direct memory access instruction execution buffer for all other hardware motion compensation instructions. Other embodiments are described and claimed.

Abstract: Disclosed is a receiver system, capable of receiving RF signals on television channels of multiple bandwidths. The receiver system includes a tuner, an analog IF filter, an ADC, a mixer module, one or more digital filters, an AGC module and a controller. The tuner converts an RF signal into an IF signal using a mixer frequency. The analog IF filter filters out a fixed band signal from the IF signal. The ADC module converts the fixed band signal into a digital signal, which is filtered by digital filters. The output of the digital filters is converted to a base band signal and the power level of the base band signal is controlled by the AGC module. The controller selects a mixer frequency from a group of mixer frequencies based on a function of power of the output of the AGC module by applying each mixer frequency to the tuner.

Abstract: Streaming data may be decoded by dividing a process for decoding the streaming data into two or more tasks based on data dependencies between the two or more tasks. The two or more tasks may be executed in parallel on three or more processors in a way that balances a processing load of executing the two or more tasks among the three or more processors.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: According to the invention, the video data to be processed and the configuration data are transferred to the module via one and the same data bus. These modules are advantageously chained in series on a common bus which transfers to each module both the configuration data and the video data to be processed. Preferably, dead time or “blanking” periods between two picture frames transmitted on this bus are used in order to insert the configuration data.

Abstract: A distorted aberration correction processing apparatus includes DRAM and SRAM for storing an object image from an optical system. Further, the distorted aberration correction processing apparatus includes: a first address control circuit for reading out a pixel in the DRAM on a unit basis of an area including a plurality of the pixels along a curve corresponding to a distorted aberration of an optical system and writing the read-out pixel in SRAM; and a second address control circuit for reading out a pixel in the SRAM on a pixel basis and outputting the pixel read out on a pixel basis to an output portion so as to suppress the distorted aberration of the optical system. The first address control circuit effects control so that the signal of the areas is sequentially read out in a predetermined order, and the second address control circuit effects random access control.

Abstract: Presented herein are systems, methods, and apparatus for real-time high definition television encoding. In one embodiment, there is a method for encoding video data. The method comprises estimating amounts of data for encoding a plurality of pictures in parallel; generating a plurality of target rates corresponding to the plurality of pictures based on the estimated amounts of data for encoding the plurality of pictures; and lossy compressing the plurality of pictures based on the target rates corresponding to the plurality of pictures.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: In a digital video processing system for processing full-motion video in computer terminal systems, two main rendering paths are created for a computer terminal system: a screen buffer path and a full-motion video path. The screen buffer path renders a desktop display from a screen buffer within the terminal system. The full-motion video path decodes a video stream and then processes the decoded video stream with a video processing pipeline to fit the video frames within a destination video window within the desktop display. The video processing pipeline performs clipping, blending, chroma resampling, resizing, and color converting of the video frames in pipelined stages with minimal memory accesses. A video adapter then combines the desktop display with the processed digital video for a final terminal display.

Abstract: Described herein is a method and system for parallel processing video data. The system having parallel encoder devices can create a balance between quality of service and delay. In order to maintain quality, compression parameters in a group of pictures can be produced by one encoder device and used by another encoder device for estimation during the encoding of another group of pictures. Compression parameters of different picture types may be stored separately and used for the encoding of a future pictures of the same type. The generation and passing of compression parameters introduces a delay based on the time it takes to encode one or more pictures.

Abstract: This document discusses, among other things, systems and methods for receiving a local input video signal, processing the video signal, and providing a processed video signal to a local digital television display panel. A communications port includes an Ethernet or other communications network connector for allowing access to the video signal processing system by a remote device. This allows a remote user to remotely diagnose, debug, and even modify operation of the video signal processing system. In certain examples, this involves downloading a Lua script that can take partial or complete control over operation of the video signal processing system from resident instruction code. In certain examples, the video signal processing system includes pipelined image analysis or processing stages. Video signal data intermediate to such processing, or the processed video signal being provided to the local display can be communicated to the remote user.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract: This document discusses, among other things, systems and methods for receiving a local input video signal, processing the video signal, and providing a processed video signal to a local digital television display panel. A communications port includes an Ethernet or other communications network connector for allowing access to the video signal processing system by a remote device. This allows a remote user to remotely diagnose, debug, and even modify operation of the video signal processing system. In certain examples, this involves downloading a Lua script that can take partial or complete control over operation of the video signal processing system from resident instruction code. In certain examples, the video signal processing system includes pipelined image analysis or processing stages. Video signal data intermediate to such processing, or the processed video signal being provided to the local display can be communicated to the remote user.

Abstract: A signal processing system with multiple electronic apparatus. A controller checks and determines whether or not the electronic apparatus are electrically connected and are compliant for performing a cooperative signal processing. For example, when a TV signal processor is not connected to another apparatus, a signal processing circuit performs normal signal processing. When the TV signal processor is connected to another compliant apparatus, the TV signal processor cooperates with the compliant electronic apparatus as if they were a single apparatus and performs optimal processing of an input signal. In an ID table stored in the controller, processing information concerning processing tasks to be shared with the compliant electronic apparatus is associated with the function ID of the compliant electronic apparatus.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: An enlarged image is displayed using a plurality of television sets. A television set serving as a master device and television sets serving as slave devices convert an input image into partial enlarged images and display the resultant partial enlarged images so that the partial enlarged images displayed on the respective television sets form, as a whole, a complete enlarged full image. The master device and slave devices perform mutual authentication with each other. If the authentication is successfully passed, the operation mode is set so that displaying of an enlarged image is allowed.

Abstract: A control method for integrating a display device with a digital television (DTV) module, which includes the steps: (A) using the display device to execute a system program; (B) determining whether the display device is in a digital television mode; (C) further determining whether the display device receives an instruction when step (B) decides that the display device is in the digital television mode; (D) further determining whether the instruction received is for the digital television module when step (C) decides that the display device receives the instruction; and (E) using the display device to send the instruction to the digital television module through a serial bus and to receive and process a response of the digital television module when step (D) decides that the instruction is for the digital television module.

Abstract: A plurality of processing portions sequentially performs a plurality of processing operation on an information signal. In this case, the plurality of processing portions is provided with a control-command-added information signal to which control commands are added for controlling the processing piece to be performed by some or all of the plurality of processing portions, for each predetermined unit of the information signal. The processing portions respectively separate the control command and the information signal from the control-command-added information signal. The information signal thus separated is then processed on the basis of the separated control command for controlling the processing to be performed by this processing portion. The separated control command is added to the post-processing information signal for each predetermined unit thereof, thereby determining a control-command-added information signal to be output.

Abstract: In a signal transmitter for a multiple differential transmission system including a signal transmitter and a signal receiver connected via three signal lines, first and second differential drivers generate first and second output signals of bipolar four values and having a first signal voltage level, and inverted first and second output signals, responsive to first and second bit information signals. A third differential driver generates a third output signal of bipolar four values having a second signal voltage level, and an inverted third output signal, responsive to a third bit information signal. The first output signal and the inverted third output signal are combined and transmitted to the first signal line, the second output signal and the inverted first output signal are combined and transmitted to the second signal line, and the third output signal and the inverted second output signal are combined and transmitted to the third signal line.

Abstract: In a signal transmitter for a multiple differential transmission system including the signal transmitter, a signal receiver, and a signal transmission path including first to third signal lines, first to third differential driver transmit first to third output signals and inverted first to third output signals from the first to third output signals responsive to first to third bit information signals, the first output signal and the inverted third output signal are combined and transmitted to the first signal line, the second output signal and the inverted first output signal are combined and transmitted to the second signal line, and the third output signal and the inverted third output signal are combined and transmitted to the first signal line. The first to third differential drivers of the signal receiver detect polarities of terminal voltages generated across terminal resistances connected between adjacent signal lines and output bit information signals.

Abstract: Appliance and method for processing a plurality of high resolution multimedial operative programs and functions, wherein the appliance is integrated with a television receiver screen, and is adapted to permit to set and display such operative programs and functions on to the television screen. Appliance comprising main electronic control means, video signal processing means, audio signal processing means, input selector means for analog and digital video and audio signals of any kind, and first, second and third electronic control means for data for personal computers and television receivers, wherein the main electronic control means are adapted to control and manage the data exchange among them and the control means of the appliance and the external electronic appliances and/or systems, for displaying the images and reproducing the sounds.

Abstract: There is provided an information processing apparatus in which a great number of users can use thin clients, and in which various services such as simultaneous picture distribution are realized in an integrated manner, an information processing system, and a controlling method of the information processing apparatus. The apparatus capable of executing plural OSs includes image transmitting devices having: a GPU for receiving a drawing instruction signal of a screen output from the OS and generating an image signal of a display screen; and a communicator for transmitting the image signal of the display screen to a terminal that operates as a thin client. The devices compressively code the image signal to a digital motion picture by a coding unit as necessary. Then, the devices transmit the coded signal from the communicator. The apparatus dynamically assigns the devices to the OSs corresponding to the respective terminals via VMM.

Abstract: A digital broadcasting receiver which updates a channel map in adequate timing, is provided with a channel storage portion which stores in advance physical number information which is numerical information to identify a receivable physical channel, and virtual major channel number information which is numerical information of a virtual channel that corresponds to the physical channel in corresponded manner with each other, and a MPU is provided with a channel setting portion which sets a physical channel to be received, a virtual information obtaining portion which obtains the virtual major channel number information that corresponds to the physical channel via a receiving portion, a number judging portion which judges whether or not the obtained virtual major channel number information agrees with the virtual major channel number information which is stored in the channel storage portion, and a number updating portion which writes the obtained virtual major channel number information in the channel storage p

Abstract: A receiving apparatus for receiving a digital television broadcast includes an amplification unit that amplifies radio frequency signals supplied from an antenna at a predetermined gain to output the amplified radio frequency signals, a channel selection unit that selects a broadcast wave from the radio frequency signals output from the amplification unit to produce output signals, a demodulation unit that processes the output signals to demodulate content data transmitted on the broadcast wave, and a control unit that controls the gain of the amplification unit so that the signal level of the output signals becomes a predetermined value. The control unit controls the gain of the amplification unit using the control start value and changes the control start value in accordance with the result of processing by the demodulation unit.

Abstract: A signal processing circuit includes: multiple digital-signal processing units operating in parallel each including a selecting unit for selecting one of multiple systems of input picture signals, a double-speed converting unit for writing the data equivalent to one field of the picture signal selected by the selecting unit in field memory, and simultaneously reading the data equivalent to one field from the field memory twice at double speed, thereby converting the frequency of the picture signal into double speed, a reading unit for reading the picture signal converted into double speed by the double-speed converting unit and temporarily stored in line memory, and a correction processing unit for subjecting the picture signal read by the reading unit to predetermined correction processing; and a control unit for performing the selection control of the multiple systems of picture signals, and the read position control of a picture signal from the line memory.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: A method and apparatus for decoding compressed video. The method includes reading a stream of compressed video into a memory. The video includes multiple pictures, with each picture having one or more independent elements. Thereafter, assigning, via a first processor of a group of processors sharing the memory, at least one independent element per processor to be decoded by the processors in parallel; and decoding the independent elements of the video stream in parallel.

Abstract: A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vector processing. Specifically, means are provided to read all elements of one or two source vector registers in each PE simultaneously, process the read elements by a set of arithmetic-logical units (ALUs), and write back all results to one of the vector registers, all of which occurs in one PE cycle. To provide such parallel vector processing capabilities, the datapath of each PE is built as a set of identical PE processing slices, each of which includes an integer arithmetic-logical unit (ALU), a vector register bank, and a block register bank. A block/vector register bank holds all I elements of row J in a two-dimensional I×J data blocks for all block/vector registers provided by the architecture.

Abstract: A personal optical viewer enables a person to view images of how the person looks wearing an accessory and compare images of how the customer looks wearing different accessories. A seller provides an accessory to a person. A capturing device captures a photograph or a video of the person and stores the image in a memory device. The personal optical viewer displays each image to the person and the person chooses which images to keep, reject, delete, or compare. The personal optical viewer replaces rejected images with other images stored in the memory device, and when the stored images have been exhausted the personal optical viewer automatically enlarges the remaining displayed images.