Abstract: There is provided a block matching processor and method for flexibly supporting block matching motion estimation at motion vector prediction modes using matching blocks of various sizes. Each of difference unit (D-unit) arrays takes each smallest size matching block, calculates the difference between the pixels of a current frame and the pixels of a reference frame, and converts the differences to absolute values. An accumulator generates SADs (Sum of Absolute Difference) for the smallest size matching blocks and SADs for all the matching blocks of various sizes by tree-like hierarchical addition of the absolute values of the smallest size matching blocks received from the D-unit arrays.

Abstract: An enlarged image is displayed using a plurality of television sets. A television set serving as a master device and television sets serving as slave devices convert an input image into partial enlarged images and display the resultant partial enlarged images so that the partial enlarged images displayed on the respective television sets form, as a whole, a complete enlarged full image. The master device and slave devices perform mutual authentication with each other. If the authentication is successfully passed, the operation mode is set so that displaying of an enlarged image is allowed.

Abstract: A receiving section for digital television broadcasting and a receiving section for analog television broadcasting are provided. When a digital television broadcasting program is selected, it is judged whether or not an analog television broadcasting program having the same contents as those of the selected digital television broadcasting program is being broadcast. In a case where the analog television broadcasting program having the same contents as those of the selected digital television broadcasting program is being broadcast, when the digital television broadcasting program cannot be received, the analog television broadcasting program having the same contents as those of the selected digital television broadcasting program is received and outputted.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: A circuit configuration applicable to systems such as consumer electronics devices enables communication between components such as integrated circuits connected to the bus. According to an embodiment, the RUN power supplies are turned to an OFF state in response to a fault condition. An interface circuit associated with an integrated circuit coupled to the bus controls the loading on the bus caused by the interface circuit and the integrated circuit such that communication between devices on the bus can continue. Therefore, even when a fault condition results in the loss of the RUN power supplies, a command can be transmitted over the bus from a first integrated circuit in a powered state to a second integrated circuit in the powered state while a third integrated circuit connected to the bus is in an unpowered state.

Abstract: In the present invention, the same image data, captured by a TV camera, is processed by the use of an image-processing board connected to an extension bus constituted by a personal computer and a CPU board inside the personal computer so that the CPU board and the image-processing board are allowed to execute the image processes in parallel with each other.

Abstract: A picture processing apparatus is composed of a plurality of picture processing systems. Each picture processing system includes an identical picture processing IC (integrated circuit) and a plurality of memories each capable of memorizing a picture frame and including at least two memories operating at different timings. The picture processing IC includes a picture processing unit, an operation timing signal generator, a plurality of control timing signal generators for controlling different memories, and a memory control signal selection circuit for selectively outputting one of at least two memory control timing signals. As a result, the number of output pins of each picture processing IC for outputting memory control signal can be reduced, whereby the picture processing apparatus can be produced at a lower cost while retaining an identically large size of the picture processing ICs.

Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: A data flow processor includes a number of hardware units each having more than one mode. A plurality of hardware units may be connected together to implement a flow made up of a series of processes. The flows, initiated by a central processing unit, may proceed independently and substantially at their own pace. Thus, the flows may operate in parallel, independently with respect to one another. Each of the hardware units may be configured differently to operate with each of the different flows.

Abstract: A video signal processor includes a receiver unit receiving a broadcasted wave, an identify unit identifying a broadcasting system according to a signal received by the receiver unit, and a plurality of data driven processors processing a video signal received by the receiver unit according to the broadcasting system identified by the identify unit. Since the plurality of data driven processors process a video signal received by the receiver unit according to the broadcasting system identified by the identify unit, video data corresponding to the broadcasting system can be generated.

Abstract: The present invention relates to method and apparatus of recording digital data stream on a recording medium such as a high-density digital versatile disk. The present recording method searches received digital data stream containing video signals for each picture section, packetizes a data section including at least one picture section found in the searching process into a PES (Packetized Elementary Stream) packet, slices the PES packet to make the sliced data pieces to a plurality of transport packets, and writes the plurality of transport packets within a stream object unit if the stream object unit has a space enough to store the plurality of transport packets, or from head point of a next stream object unit if not. Therefore, the head of each stream object unit is aligned with start of an arbitrary picture, thereby improving random accessibility of A/V data stream recorded on a recording medium.

Abstract: A video signal processing apparatus which can process video signals with different formats simply by switching between programs for processing video signals. Different system clock signals are sent to the input and output processes by employing a programmable signal processor 4, input synchronizing signal processor 8, programmable signal processor 6 and output synchronizing pulse processor 9. A method for processing the video signal can be flexibly changed simply by switching between signal processing programs for programmable signal processors. In addition, the use of a memory 5 enables the signal, which is processed using the system clock signal in the input process, to be processed using the system clock signal in the output process. The present invention thus allows the processing of video signals with many different signal formats. The design of efficient circuitry will greatly reduce costs and production processes.

Abstract: An image processing system including a display output processor using Temporal Gamma Processing (TGP) and Reverse Super-resolution (RSR) techniques to process images. TGP assures that the time-related representation of an image is as accurate as possible, and thus, based on a previous frame value and a known transfer function of the display modulation system, adjusts its output values to provide a desired output value during display of a desired frame. RSR performs a superset of the frame rate conversion process for converting between disparate input and output frame rates. RSR, improving display quality when intended display images have apparent resolution higher than can be supported by an image modulator, sequences lower resolution images at higher frame rates to simulate higher resolution outputs.

Abstract: Plural-conversion radio receivers for receiving DTV signals, in accordance with the Advanced Television Systems Committee (ATSC) standard, or analog TV, in accordance with the National Television Sub-Committee (NTSC) standard, utilize a first intermediate-frequency band spanning 917-923 MHz and a second intermediate-frequency band spanning 35.5-41.5 MHz. A local oscillator generates local oscillations at 958.5 MHz for mixing with signal in the first intermediate-frequency band to generate signal in the second intermediate-frequency band. These local oscillations do not interfere with the aeronautical navigation band or with channel 81 television broadcasting. The second harmonic of sound carrier in the second intermediate-frequency band falls below the 88-108 MHz FM broadcast band.

Abstract: A real-time modular video processing system (VPS) which can be scaled smoothly from relatively small systems with modest amounts of hardware to very large, very powerful systems with significantly more hardware. The modular video processing system includes a processing module containing at least one general purpose microprocessor which controls hardware and software operation of the video processing system using control data and which also facilitates communications with external devices. One or more video processing modules are also provided, each containing parallel pipelined video hardware which is programmable by the control data to provide different video processing operations on an input stream of video data. Each video processing module also contains one or more connections for accepting one or more daughterboards which each perform a particular image processing task.

Abstract: Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.

Abstract: An image processor has a plurality of unit processors, each of which are assigned specific non-contiguous frame regions. All of the unit processors simultaneously start processing input partial image signals after all of the signals corresponding to the assigned frame regions have been fetched.

Abstract: A frame combining apparatus, having a plurality of decoding means for decoding frame data for each of a plurality of sub-frames through a decoding process opposite to a coding process when a plurality of coded data streams obtained by coding frame data of a frame divided into a plurality of sub-frames are input, a synchronizing means for generating external synchronizing data for defining output timings of decoded outputs from a plurality of decoding means, and a delaying means for generating more than one external synchronizing data delayed by a delay time corresponding to a plurality of sub-frames in response to the division of a frame and to give the external synchronizing data from the synchronizing means and external synchronizing data having a delay time corresponding to the divided sub-frames out of more than one delayed external synchronizing data to decoding means corresponding to the sub-frames, respectively.

Abstract: A system for processing compressed data corresponding to pictures includes a decoding mechanism, providing a picture memory with decoded picture data. The decoding mechanism requires, for decoding a current block of a previously decoded picture. A plurality of decoders are associated with respective picture memories, each storing a specific slice of corresponding blocks of a plurality of pictures, as well as at least one margin which is liable to be a predictor block serving to decode a block of the specific slice.

Abstract: A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are efficiently timesharing a global memory storage area. The received data streams are each divided into fixed portions called spans. The invention is operable for sequencing the movement of the time-sliced spans between the processors, adjusting the scheduling of particular ones of the time-sliced spans as a function of either processor availability or maintenance of real-time transmission of the received real-time time-sliced data streams.

Abstract: A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response to a programmed-controlled pointer and a three or more port data memory unit for writing-in data read out from the serial-access memory. An arithmetic logic unit responds to stored-program control to read out data from the data memory, perform a program-prescribed arithmetic operation, and write the result of the arithmetic operation back to the data memory. An output serial-access memory is controlled so that the arithmetic result will be outputted under program control in a sequential manner. Operation of the interconnected components is effected by a stored-program control unit connected to the input serial-access memory, the data memory, the arithmetic logic unit, and the output serial-access memory.

Abstract: A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and any of outputs of the processor block columns is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

Abstract: A device and method for generating output trigger signals, for firing one or more light sources, from input trigger signals generated by a vision processor. The input trigger signals are first accepted from the vision processor. Next, output triggers are determined, in response to the input trigger signals, based on a stored lighting program. Finally the output trigger signals are generated based on the determined output triggers.

Abstract: There is provided a correlation degree operation apparatus in which the search area is readily extensible, in which a high-speed process can be assured even though the search area is extended, and which can be formed in a simple arrangement. The search area memory stores the picture element data of a search area including ((m.times.M).times.L) candidate blocks. The correlation degree operation unit executes an operation of a degree of correlation between a reference picture block and each of the candidate blocks, with the use of picture element data supplied from the search area memory, this operation being executed by a pipeline process for each candidate block group composed of (M.times.L) candidate blocks. The search area memory has the function of supplying four picture element data at the same clock cycle. This enables the correlation degree operation unit to continuously execute the pipeline processes for the candidate block groups.

Abstract: A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and an output of any of the processor blocks is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

Abstract: A goggle type image display apparatus including left and right image display optical blocks, an optical block distance adjusting mechanism for adjusting the distance between the left and right optical blocks, and a housing for containing the left and right optical blocks and the optical block distance adjusting mechanism. The left and right optical blocks and the optical block distance adjusting mechanism are removably mounted as a unit on a support frame within the housing.

Abstract: To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of individual processors. For signals comprised of data of a length, serving as the unit of processing, of m or less and n or more, these parallel processors are connected and used as a single parallel processor apparatus which performs processing equivalent to that by a conventional parallel processor apparatus. For signals comprised of data of a length of n or less, these parallel processors are independently used to perform pipeline processing and thereby perform two times the amount of processing of that performed by a conventional parallel processor apparatus.

Abstract: Digital image signals in each small block of m.times.n picture elements are read out from a first image memory, which stores the digital image signals for one screen, to be stored in block memories BM1Y, BM2Y, BM1C and BM2C, and the electric zoom processing together with the interpolation operation for the digital image signals in each small block are carried out in a zoom block. A picture element in the horizontal direction in a small block partially overlaps a picture element in a small block which is next to the above-mentioned small block in the horizontal direction. As a result, the interpolation processing in the horizontal direction can be also carried out on the boundary of the small blocks. And, the order to read out the digital image signal from the first image memory and the order to write the digital image signal in the block memory are changed so that the longitudinal-lateral conversion and the right-left conversion of an image can be carried out.

Abstract: A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920.times.1080 pixel display space is divided into four vertical sections of 480.times.1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240.times.1080 pixels. Each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8.times.

Abstract: A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.

Abstract: A control system operates in a pipelined mode for executing multiple clock cycle instructions and in an open loop mode for executing single clock cycle instructions. A plurality of electrical functional units are capable of executing single clock cycle instructions and multiple clock cycle instructions that are individually addressed and applied thereto by a processor. The functional units generate current operational statuses after each clock cycle. A status indicator applies new operational statuses of the functional units to the processor. A status memory stores previous operational statuses of the functional units. A control unit controls the status indicator to apply the previous operational statuses to the processor as the new operational statuses after one of the single clock cycle instructions has been applied to the functional units.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected.

Abstract: Processing a moving image such that, after an input video signal is supplied to an image inputter, the image inputter time-divisionally converts the input video signal to a digital signal and outputs a control signal such as a vertical synchronous signal. A multiplexer reads image data converted by the image inputter into the digital signal and stores them into a plurality of temporary storers unique for frames according to the control signal from the image inputter. The plurality of temporary storers are respectively connected with a plurality of processor elements which process the memory contents of the plurality of temporary storers and re-store the processing results back in the plurality of temporary storers. A multiplexer sequentially retrieves the memory contents from the plurality of temporary storers, and has an image outputter for converting a digital signal to a video signal output them.

Abstract: In the motion prediction processor outputting the encoding type designating the inter-frame or intra-frame prediction coding and the motion vector in case of performing the inter-frame prediction coding, the coordinate values of the currently processed block are outputted and an offset is supplied to the address for reading out the reference region from the reference frame memory. The evaluation data for estimating the coding quantity in case of performing the inter-frame prediction coding is also outputted. An n number of the motion prediction processors are arranged and respectively associated with reference frame memories. The reference regions different from the same block are supplied to the n motion prediction processors and the motion prediction processor with the least evaluation data is selected from among the motion prediction processors whose reference regions are comprised within the picture. The motion vector outputted by the thus selected processor is corrected and outputted.

Abstract: Pixel data is stored and subsequently read from a random access memory of a video decompression processor in a manner that reduces the number of times different rows of the RAM must be addressed in order to retrieve portions of the pixel data therefrom. Pixel data from a video frame is stored in the RAM as a plurality of pages. Each page substantially fills a different row of the RAM and corresponds to a different section of the video frame. A motion vector is decoded to determine the location of a prediction area within the video frame. In the event that the prediction area encompasses more than one of the pages of the video frame, the pixel data is retrieved one page at a time, minimizing the number of row changes required when addressing the RAM to retrieve the data.

Abstract: To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of individual processors. For signals comprised of data of a length, serving as the unit of processing, of m or less and n or more, these parallel processors are connected and used as a single parallel processor apparatus which performs processing equivalent to that by a conventional parallel processor apparatus. For signals comprised of data of a length of n or less, these parallel processors are independently used to perform pipeline processing and thereby perform two times the amount of processing of that performed by a conventional parallel processor apparatus.

Abstract: A temporally-pipelined predictive encoder/decoder circuit for encoding or decoding an input signal containing a sequence of data frames received at a particular frame rate and frame data rate into an output signal having an equal frame rate employs a plurality of N predictive encoders/decoders. An input buffer may be used to extract the information for each data frame in the input signal and supply such information to a corresponding one of the encoders/decoders at rate of 1/N of the particular frame data rate. Each encoder/decoder generates corresponding encoded/decoded information as it is received as well as provides digitized frame information to the encoder/decoder processing the next received image frame. The encoded/decoded information is provided to corresponding frame buffers which temporarily store such information.

Abstract: The invention relates to a digital processing circuit comprising a host interface (7) which provides access from the processing circuit's bus (6) to an external data processing system (8). The processing circuit is broken down into blocks (1, 2, 3) with test registers (4, 5) interposed between an upstream block and a downstream block. The test registers (4, 5) are connected to the bus (6) and identified by an address allowing data to be sent to them or read from them.

Abstract: Apparatus and methods are described whereby a projected television image is divided into two horizontally displaced images, and an observer wears glasses to synthesize three-dimensionality from the 2-D image. Switching means are provided so that the components associated with creating the 3-D effect may be made operative or inoperative, either mechanically or electrically. One or more wedge prisms or holographic optical elements are mounted on a frame along with polarizing filters, and a lever is used to transfer these elements into and out of the beam of a projected television image. Alternatively, an electrically or acoustically activated spatial light modulator and liquid-crystal polarizers may be left in the path of the projected beam and made operative and inoperative by way of electrical signals. The invention may be used with both single-source and multi-source projected images, and may be used in conjunction with both frontal and rear projection.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into separate video signals by composite video interface and separation circuit (16). The separate video signals are converted to digital video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c).

Abstract: An apparatus for digital video and audio processing including information input and output processing devices for input, output, and processing of pictures and sounds. An information transmission device is provided for transmitting video and audio information between adjacent information input and output processing devices in one direction. The information transmission device connects the information input and output processing devices to a control device which controls the information input and output processing devices. A bus is also provided for transferring video or audio information or control information to the information input and output processing devices. An input terminal is used to enter control information into the control device.

Abstract: A system (14') for processing pixel video data having a selectable number of bits is provided. The system (14') comprises first, second and third video processors (20), (22) and (24). The first video processor (20) receives and processes pixel data of a luminance video signal. The second video processor (22) may receive and process pixel data of a chrominance video signal and may generate one of first, second and third video signal outputs. The third video processor (24) may process the chrominance video signal and may also generate at least two of the output video signals.

Abstract: A digital television system (10) System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j).

Abstract: An image signal processor for processing a received image signal. The received image signal can be at least one of an analog image signal and a digital image signal. The processor converts the analog image signal into first digital image data and converts the digital image signal to second digital image data. The processor selects at least one of the first and second digital image data as input image data. The input image data is then decode-processed based upon a selected at least one of a plurality of processing programs. The selected at least one processing program corresponds to the selected at least one of the first and second digital image data.

Abstract: A processor comprises a plurality of parallel channels having an upstream end and a downstream end, Each channel comprises a video data bus for continuously transferring video data from the upstream end to the downstream end, a plurality of modules serially connected along the video data bus and a host computer connected to the downstream end of the plurality of channels for receiving the video data. Each module comprises a crossbar switch, a pixel processing element connected to the crossbar switch, a delay resource connected across the crossbar switch and a microprocessor operably integrated within each module for controlling the operation thereof. The microprocessors of each module are serially connected together for transmitting and undertaking commands. The host computer is also connected to the microprocessor of each module for issuing commands for controlling the operation of the processor.

Abstract: A system and method are provided for encoding and decoding data in a video processor system wherein image data values represent a plurality of successive images. A current image is stored into a block of memory locations and later read from the block of memory locations, encoded and transmitted. In addition to being transmitted, the encoded data values are also decoded in order to provide companded image values. The companded image values are then stored into the same block of memory locations as the current image. The data values representing the current image are simultaneously read from the memory block while the companded values are being stored into the same memory block under the control of a number of pointers and a number of synchronization flows. Additionally, the companded data values are simultaneously read from the same memory block for the purpose of performing motion estimation.