Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract: This invention provides novel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.

Abstract: The capacitor 10 (laminated ceramic capacitor) of the invention comprises a capacitor body 11 wherein internal electrodes 12 (electrodes) and a dielectric layer 14 are alternately laminated, and external electrodes 15 are provided on the end faces thereof. The dielectric layer 14 has a site containing particles of a dielectric material which is formed of only one of these particles in its thickness direction. Regions 24 comprising at least one element selected from a group comprising Si, Li and B are scattered between the internal electrodes 12 and dielectric layer 14.

Abstract: Thin-film capacitors are formed on ceramic substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are annealed at high temperatures.

Abstract: A monolithic ceramic electronic component includes a low-permeability coil portion formed by stacking low-permeability ceramic green sheets, a first coil and a relatively large number of pores, and a high-permeability coil portion formed by stacking high-permeability ceramic green sheets, a second coil and a relatively small number of pores. The first coil and the second coil are electrically connected in series to form a spiral coil. The coil portion composed of a ferrite ceramic having a small number of pores has a high permeability and a high dielectric constant, and the coil portion composed of a ferrite ceramic having a large number of pores has a low permeability and a low dielectric constant.

Abstract: A dielectric ceramic is obtained by the steps of obtaining a reaction product composed of a barium titanate base composite oxide represented by the general formula (Ba1?h?i?mCahSriGdm)k(Ti1?y?j?nZryHfjMgn)O3, in which 0.995?k?1.015, 0?h?0.03, 0?i?0.03, 0.015?m?0.035, 0?y<0.05, 0?j<0.05, 0?(y+j)<0.05, and 0.015?n?0.035 hold; mixing less than 1.5 moles of Ma (Ba or the like), less than 1.0 mole of Mb (Mn or the like), and 0.5 to 2.0 moles of Mc (Si or the like) with respect to 100 moles of the reaction product; and firing the mixture thus obtained. This dielectric ceramic has superior humidity resistance, satisfies the F characteristic of the JIS standard and the Y5V characteristic of the EIA standard, has a relative dielectric constant of 9,000 or more, and has superior high-temperature reliability.

Abstract: A multi-layer printed wire board (PWB) structure optimized for improved drop reliability, reliable electrical connections under thermal load, and minimal thickness is provided, along with a mobile terminal, including the PWB. The PWB includes alternating conductive layers and insulative layers. The outermost three layers form an interconnect structure constructed of two conductive layers surrounding an insulative-coated conductive layer. The thicknesses of the various layers are optimized to have an increased resistance to mechanical shock resulting from, for instance, a drop onto a hard surface. In addition, the optimized PWB structure has a minimized thickness and an improved resistance to connection failures resulting from cyclical thermal loads.

Abstract: A dielectric body 12 has internal conductor layers 14 arranged in it. At the far sides of the internal conductor layers 14 separated by ceramic layers 12A, internal conductor layers 16 are arranged. A length W of a side of the dielectric body 12 running along a stacking direction Y of the ceramic layers is made longer than the lengths L and T of any other two sides running along directions (X- and Y-directions) intersecting the side running along the stacking direction (Y-direction). The internal conductor layers 14 and 16 are formed with cut parts 18a and 18b, the internal conductor layers 14 are divided into channel parts 20A and 20B across the cut part 18a, and the internal conductor layers 16 are divided into channel parts 22A and 22B across the cut part 18b. These channel parts are connected through uncut ends 19, whereby the current flows in reverse directions.

Abstract: A capacitive load cell includes upper and lower capacitor plates and an intermediate array of dielectric pads formed of silicone-impregnated open-cell urethane foam (i.e., gel pads). The silicone essentially displaces air that would otherwise be trapped in the foam, contributing to a dielectric having minimal humidity-related variability. The upper capacitor plate is defined by an array of individual charge plates, the lower capacitor plate defines a ground plane conductor common to each of the charge plates, and the dielectric pads are disposed between the ground plane conductor and each of the charge plates, leaving channels between adjacent dielectric pads. When occupant weight is applied to the seat, the dielectric pads transmitting the weight distend laterally into the channels to reduce the separation between the respective upper and lower capacitor plates, and the consequent change in capacitance is detected as a measure of the applied force and the force distribution.

Abstract: A decoupling module for decoupling high-frequency signals from A power supply line, the module including a layer (30) of dielectric material which is arranged between a first and a second metallic layer (20, 22), where the first metallic layer (20) is connected as a ground electrode of the decoupling module and the second metallic layer (22) includes at least two surfaces of different size which are consecutively electrically connected between an input connection point and an output connection point, while two respective consecutive surfaces are connected to each other by only one conducting section.

Abstract: Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.

Abstract: The capacitance of a shielded capacitive load cell is determined so as to minimize the effect of stray or parasitic capacitance between the load cell and other objects including the shield. The load cell conductors are coupled across input and output terminals of an operational amplifier that is tied to a reference voltage. A constant current is applied to the load cell, and the resulting rate of change in voltage at the amplifier output is measured as a representation of the load cell capacitance. In a vehicle seat sensor application including an electromagnetic interference shield between the load cell and the seating surface, the amplifier output is coupled to the load cell electrode furthest from the shield, the amplifier maintains the other load cell electrode at a virtual reference voltage, and the shield is tied to the reference voltage.

Abstract: An interleaving striped capacitor substrate structure for pressing-type print circuit boards is disclosed. To meet the high-frequency, high-speed, and high-density requirements in modern electronic systems, the interleaving striped capacitor substrate structure uses several dielectric materials of different dielectric coefficients to make a dielectric layer. One dielectric layer can be stacked on another to form a multi-layered capacitor substrate so that a single capacitor substrate can provide the highest capacitance required for the decoupling capacitor to suppress high-frequency noise signals, and the lower dielectric coefficient substrate required for high-speed signal transmission. This simultaneously achieves the effects of reducing high-frequency transmission time and suppressing high-frequency noise.

Abstract: Disclosed is a capacitor with a dielectric structure having an aluminum oxide layer and a lanthanum oxide layer and a fabrication method thereof. The capacitor includes: a lower electrode; a first dielectric layer with a high energy band gap formed on the lower electrode; a second dielectric layer formed on the first dielectric layer, the second dielectric layer with a high dielectric constant, wherein an energy band gap of the second dielectric layer is lower than the energy band gap of the first dielectric layer; and an upper electrode formed on the second dielectric layer.

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.

Abstract: In a capacitor device of the present invention includes a substrate, a plurality of lower electrodes formed on the substrate, a plurality of dielectric films formed on a plurality of lower electrodes respectively in a state that the dielectric films are separated mutually, and upper electrodes formed on a plurality of dielectric films respectively, a plurality of capacitors each composed of the lower electrode, the dielectric film, and the upper electrode are arranged on the substrate respectively, and each of the dielectric films in a plurality of capacitors has a different film thickness.

Abstract: A glass frit for dielectrics, a dielectric ceramic composition, a multilayer ceramic capacitor, and a method for manufacturing the same are disclosed. The glass frit has a composition represented by the formula aSiO2-bB2O3-cLi2O-dK2O-eCaO-fAl2O3-gTiO2-hZrO2, wherein the ratio of components satisfies the conditions of 20?a?35, 20?b?35, 20?c?30, 3?d?5, 2?e?12, 2?f?10, 1?g?12 and 1?h?7 in terms of mol % where a+b+c+d+e+f+g+h=100. The dielectric ceramic composition comprises 100 parts by weight of (Ca1-xRx)(Zr1-yTiy)O3, 0.5˜2.5 parts by weight of the glass frit, and 1.0˜5.0 parts by weight of a Mn compound. Additionally, the multilayer ceramic capacitor, and the method for manufacturing the same also use the glass frit having the above composition. The ratio of tetracoordinate boron to tricoordinate boron is increased in a lithium borosilicate glass, thereby enhancing structural property, and the components of Al2O3, TiO2 and ZrO2, enhance acid resistance.

Abstract: A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.

Abstract: An electrical component with a printed circuit board. The printed circuit board has an upper face and a lower face. A microprocessor is mounted to the upper face. A capacitor is mounted to the lower face. The capacitor has a first face parallel to the printed circuit board and a second face opposite to the first face. First plates and second plates are in alternating planar relationship with a dielectric therebetween and arranged in a plane perpendicular to the plane created by the circuit board. Each first plate has a first coupling tab and a power tab on opposing edges wherein the first coupling tab terminates at the first face and the power tab terminates at the second face. Each second plate of the second plates comprises a second coupling tab and a ground tab on opposing edges wherein the second coupling tab terminates at the first face and the ground tab terminates at the second face. The first coupling tab and the second coupling tab are in electrical contact with the microprocessor.

Abstract: A multilayer ceramic capacitor assembly capable of exhibiting low high-frequency inductance and a controlled equivalent series resistance (ESR) while maintaining a useful capacitance value includes respective pluralities of first and second electrode elements interleaved to form a stack. Controlled ESR is achieved either through inclusion of specific types of materials or through alteration of the shape of various component parts. A resistive material may be used in typical end terminations, via terminations, electrode elements or connective tab structures. Additionally, the dielectric may be made lossy so as to enhance resistivity without overly affecting device capacitance. Still further, an additional layer of resistive material may be added to an outer device surface to connect filled-via terminations to end terminations or radial resistive prints may be used to only partially fill the vias.

Abstract: A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.

Abstract: The present invention provides a barium titanate having a small particle size, containing small amounts of unwanted impurities, and exhibiting excellent electric characteristics, which can be employed for forming a dielectric ceramic thin film required for a small-sized capacitor which enables production of a small-sized electronic apparatus; and a process for producing the barium titanate. When a titanium oxide sol is reacted with a barium compound in an alkaline solution containing a basic compound, the basic compound is removed in the form of gas after completion of reaction, and the resultant reaction mixture is fired, a barium titanate having a large BET specific surface area and a high tetragonality content is produced.

Abstract: In a capacitor and a method for its manufacture, a first electrode layer and a second electrode layer are formed such that a ferroelectric layer is situated between the first and second electrode layer. A first bilayer or multi-layer seed structure is formed between the ferroelectric layer and either the first electrode layer or the second electrode layer.

Abstract: Disclosed is a high-performance, RF-capable MIM capacitor structure and process for the manufacture thereof, which are compatible with discrete or integrated processes. The invention is compatible with standard semiconductor processing techniques and provides increased capacitance per unit area for a wide variety of capacitor requirements. The invention exploits vertical dimensions, reduces the chip area required for capacitors, and facilitates the use of advanced materials, such as high-k dielectric materials.

Abstract: A capacitive load cell apparatus includes upper and lower capacitor plates and an intermediate dielectric in the form of a synthetic knit spacer material having upper and lower fabric layers interconnected by an array of deflectable synthetic fibers. When occupant weight is applied to the seat, the synthetic fibers deflect to locally reduce the separation between the upper and lower capacitor plates, and the consequent change in capacitance is detected as a measure of the applied weight. The load cell or just the dielectric may be encased in a polymeric sheath to prevent intrusion of foreign matter, and a fluid such as silicone may be dispersed in woven dielectric.

Abstract: A multilayer ceramic capacitor 1 having internal electrode layers 3, internal dielectric layers 2 having the thickness of less than 2 ?m, and external dielectric layers 20 wherein; the internal dielectric layers 2 and the external dielectric layers 20 include a plural number of dielectric particles 2a, 20a, and when y1 is ratio(D50a/D50b) of D50a and D50b where D50a is an average particle size of dielectric particles 2a included in the internal dielectric layers 2 and D50b is an average particle size of dielectric particles 20a included in the external dielectric layer 20 and located at least 5 ?m away from an internal electrode layer 3a, arranged outermost part of all the internal electrode layers, to the stacked direction, and x is thickness of the internal dielectric layer 2, y1 and x satisfy the following equations, y1??0.75x+2.275 and y1??0.75x+1.675.

Abstract: An integrated circuit substrate having embdedded passive components provides a reduced cost and compact package for a die and one or more passive components. An insulating layer of the substrate is embossed or laser-ablated to generate apertures for insertion of a paste forming the body of the passive component. A resistive paste is used to form resistors and a dielectric paste is used for forming capacitors. A capacitor plate may be deposited at a bottom of the aperture by using a doped substrate material and activating only the bottom wall of the aperture, enabling plating of the bottom wall without depositing conductive material on the side walls of the aperture. Vias may be formed to the bottom plate by using a disjoint structure and conductive paste technology. Connection to the passive components may be made by conductive paste-filled channels forming conductive patterns on the substrate.

Abstract: A method for making an electronic module includes forming a low temperature co-fired ceramic (LTCC) substrate with at least one capacitive structure embedded therein. Forming the LTCC substrate may include arranging first and second unsintered ceramic layers and the at least one capacitive structure therebetween. The at least one capacitive structure may include a pair of electrode layers, an inner dielectric layer between the pair of electrode layers, and at least one outer dielectric layer adjacent at least one of the electrode layers and opposite the inner dielectric layer. The at least one outer dielectric layer preferably has a dielectric constant less than a dielectric constant of the inner dielectric layer. The unsintered ceramic layers and the at least one capacitive structure may also be heated, and at least one electronic device may be mounted on the LTCC substrate and electrically connected to the at least one embedded capacitive structure.

Abstract: A multilayer ceramic capacitor including an internal electrode layer, an internal dielectric layer having a thickness of less than 2 ?m, and an external dielectric layer is provided, wherein the internal dielectric layer and external dielectric layer contain a plurality of dielectric particles, and when assuming that an average particle diameter of the entire dielectric particles in the internal dielectric layer is D50a (unit: ?m), an average particle diameter of the entire dielectric particles existing at a position being away at least by 5 ?m from the outermost internal electrode layer in the thickness direction is D50b (unit: ?m), a ratio (D50a/D50b) of the D50a and D50b is y (no unit), standard deviation of a particle size distribution of the entire dielectric particles in the internal dielectric layer is ? (no unit), and a ratio that dielectric particles (coarse particles) having an average particle diameter of 2.

Abstract: A dielectric body 12 has internal conductor layers 14 arranged in it. At the far sides of the internal conductor layers 14 separated by ceramic layers 12A, internal conductor layers 16 are arranged. A length W of a side of the dielectric body 12 running along a stacking direction Y of the ceramic layers is made longer than the lengths L and T of any other two sides running along directions (X- and Y-directions) intersecting the side running along the stacking direction (Y-direction). The internal conductor layers 14 and 16 are formed with cut parts 18a and 18b, the internal conductor layers 14 are divided into channel parts 20A and 20B across the cut part 18a, and the internal conductor layers 16 are divided into channel parts 22A and 22B across the cut part 18b. These channel parts are connected through uncut ends 19, whereby the current flows in reverse directions.

Abstract: A capacitor includes a capacitor main body having a front surface on which a semiconductor device is to be mounted and a rear surface at which the capacitor main body is to be mounted on a first main surface of a circuit substrate, a plurality of internal electrodes disposed within the capacitor main body, and a plurality of via conductors penetrating the capacitor main body between the front surface and the rear surface and electrically connected to the internal electrodes, wherein the capacitor main body has a first dielectric layer located on a side of the capacitor main body closer to the front surface and a second dielectric layer located on a side of the first dielectric layer closer to the rear surface, the second dielectric layer having a higher thermal expansion coefficient and a higher dielectric constant than the first dielectric layer.

Abstract: A monolithic ceramic component includes a coil-including region formed by stacking ceramic green sheets for defining inner layers having a porosity of about 30% to about 80%, and outer layer regions formed by stacking ceramic green sheets for defining outer layers have a porosity of about 10% or less. Outer electrodes are provided on the right end surface and the left end surface of a sintered ceramic laminate. That is, the outer electrodes are provided on the main surfaces of outermost ceramic sheets for outer layers.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which covers the capacitor and has a first hole and a second hole, the first hole being provided apart from the capacitor and extending in a vertical direction with respect to a main surface of the semiconductor substrate, the second hole reaching an electrode of the capacitor, extending in the vertical direction with respect to the main surface of the semiconductor substrate and being shallower than the first hole, a tungsten plug provided in the first hole, a first oxygen barrier film provided between the tungsten plug and a side wall of the first hole, and a conductive plug provided in the second hole and connected to the electrode of the capacitor.

Abstract: A transmission line capacitor includes at least two side-by-side capacitor portions spaced apart between a separating portion all contained in a single monolithic body. Such transmission line capacitors provide specific capacitor functionality for parallel transmission lines in a printed circuit board environment, while also maintaining a desired impedance value between the transmission paths. The transmission line capacitors offer both biasing functionality for blocking undesired DC voltages as well as AC coupling functionality for passing AC voltage signals with preserved data integrity. A first embodiment may be formed with a dielectric material having a relatively low dielectric constant, allowing high capacitor “height” with fixed spacing between distinct capacitive structures. Another embodiment may be formed with a relative high K dielectric and then slotted with an air gap between capacitive structures.

Abstract: A capacitor is formed on an interlayer insulating film formed on a semiconductor substrate. The capacitor includes a bottom electrode made of platinum, a capacitor insulating film made of SrTaBiO (SBT) containing an element absorbing hydrogen such as titanium, for example, in grain boundaries, inter-lattice positions or holes, and a top electrode made of platinum.

Abstract: A capacitor comprising: a thin film laminate including a plurality of dielectric thin films and a plurality of electrode conductor thin films laminated alternately; and first kind terminals and second kind terminals formed over a first main surface of said thin film laminate and isolated from each other in a DC current, wherein a first kind electrode conductor thin films electrically connecting with said first kind terminals and a second kind electrode conductor thin films electrically connecting with said second kind terminals are so alternately laminated in a laminate direction as are separated by said dielectric thin films, and a first dielectric thin film, an other kind electrode conductor thin film and a second dielectric thin film are laminated in this order between one same kind electrode conductor thin film and other same kind electrode conductor thin film adjoining in said laminate direction, and first through holes, second through holes and the like are defined herein.

Abstract: According to the present invention, a method of manufacturing a ferroelectric capacitor using a ferroelectric thin film, includes steps of: forming a lower conductive layer on a semiconductor substrate; coating solution of ferroelectric coking including organic solvent and organometallic complex on the lower conductive layer; performing a heating process for coated solution at temperature, to decompose said organometallic complex in solution of ferroelectric coking, or more and ferroelectric crystallization temperature or below to form said metal compound thin film; forming an upper conductive layer on said metal compound thin film; and performing a heating process for said metal compound thin film at ferroelectric crystallization temperature or more to form said ferroelectric thin film.

Abstract: A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.

Abstract: A yoke main body formed of an upper yoke and a lower yoke accommodates therein a magnetic substrate, a plurality of line conductors, a plurality of capacitor substrates, a magnetic member and a spacer member. The line conductors are connected to one another on one of the surface sides of the magnetic substrate, and each end of the line conductors put one upon another on a main surface side of the magnetic substrate is connected to the capacitor substrate. A gap portion for magnetically insulating the upper yoke and the lower yoke is defined between them.

Abstract: The mean grain size (D2) of the main crystal phase 11 in the external cover dielectric layers 3 is made larger than the mean grain size (D1) of the main crystal phase 11 in the dielectric ceramic layers 7, and the amount of the secondary phase (M2) in the external cover dielectric layer 3 is made more than the amount of the secondary phase (M1) in the dielectric ceramic layer 7, or the volume proportion of the secondary phase 16 to the main crystal phase 11 in the external cover dielectric layer 3 is made lower than the volume proportion of the secondary phase 16 to the main crystal phase 11 in the dielectric ceramic layer 7.

Abstract: A multilayer ceramic capacitor having internal electrode layers and dielectric layers with dielectric particles is disclosed. An average particle diameter of the dielectric particles, when measured parallel with the direction of the internal electrode layers, is larger than a thickness of the dielectric layer. A ratio (R/d) between the average particle diameter (R) and the thickness (d) of the dielectric layer is 1<R/d<3.

Abstract: A high voltage capacitor has a monolithic body made of layers of dielectric material and further has first and second external contacts located on the body. First and second nonoverlapping electrodes electrically connected to the respective first and second contacts are located on respective first and second layers of dielectric material within the body. A floating electrode not connected to either of the contacts is located on a different, third layer of dielectric material. The floating electrode overlaps the first and second electrodes and forms two serially connected capacitors therewith.

Abstract: Multi-layer and cascade capacitors for use in high frequency applications and other environments are disclosed. The subject capacitor may have multiple capacitor components or aspects thereof in an integrated package. Such components may include, for example, thin film BGA components, interdigitated capacitor (IDC) configurations, double-layer electrochemical capacitors, surface mount tantalum products, multilayer capacitors, single layer capacitors, and others. Exemplary embodiments of the present subject matter preferably encompass at least certain aspects of thin film BGA techniques and/or IDC-style configurations. Features for attachment and interconnection are provided that facilitate low ESL while maintaining a given capacitance value. Additional advantages include low ESR and decoupling performance over a broad band of operational frequencies.

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film containing an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film containing an electrically conductive polymer located on the pentoxide layer.

Abstract: The invention describes an electronic component, in particular a multiplayer component, with a dielectric and at least one electrode. The dielectric is a composite made of a dielectric ceramic material and an organic polymer. To manufacture the electronic component, the dielectric ceramic material is mixed with a suitable monomer, the mass id formed, and the monomer is polymerized. Ceramic bodies of stable shape are obtained which can be processed further into capacitors, antennas, or other passive components in that electrodes are provided. Sintering of the electronic components is no longer necessary.

Abstract: A capacitor element is composed of a lower electrode, a ferroelectric film, and an upper electrode that are formed on a substrate. In the capacitor element, the ferroelectric film is formed by a reaction rate-determining method, and the lower electrode has a thickness of not more than 100 nm, and variation of the thickness of not more than 10%. With this, a capacitor element in which the composition variation of the ferroelectric film is suppressed, and a method for producing the same, are provided.

Abstract: The invention provides dielectric compositions and methods of forming the same. The dielectric compositions may be used to form dielectric layers in electronic devices such as multilayer ceramic capacitors (MLCCs) and, in particular, MLCCs which include base metal electrodes. The dielectric compositions include a barium titanate-based material and several dopants. The type and concentration of each dopant is selected to provide the dielectric composition with desirable electrical properties including a stable capacitance over a temperature range, a low dissipation factor, and a high capacitance. Preferably, MLCCs including dielectric layers formed with the composition satisfy X7R and/or X5R requirements.

Abstract: A multilayer ceramic capacitor is formed by alternately stacking a plurality of dielectric layers and a multiplicity of internal electrodes, which are connected to a pair of external electrodes. Each of the dielectric layers is obtained from a dielectric ceramic compound composed of ceramic grains and a glass component connecting the ceramic grains, and the glass component contains one or more additive elements in a form of a solid solution. The additive elements are selected from the group consisting of Mn, V, Cr, Mo, Fe, Ni, Cu and Co.

Abstract: Multilayer dielectric structures particularly suitable for use in capacitors and having a plating dopant in an amount sufficient to promote plating of a conductive layer are provided, together with methods of forming such structures. Such dielectric structures show increased adhesion of subsequently applied conductive layers.

Abstract: A capacitive element for a circuit board or chip carrier is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The partially cured sheet is laminated to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.