Abstract: A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.

Abstract: A test device is disclosed. The test device includes an input/output (I/O) circuit configured to allow static electricity flowing between an input/output (I/O) pad and an internal circuit to be discharged to a power-supply line, a ground line, or a substrate line, a capacitor circuit configured to perform modeling of parasitic capacitance extracted from a package design, and a discharge circuit configured to allow capacitance stored in the capacitor circuit to be discharged to the substrate line.

Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.

Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

Abstract: A protection circuit, comprising: a transient suppression circuit, configured to suppress a transient voltage; and a short-circuit protection circuit connected between the transient suppression circuit and a ground terminal, wherein when the transient suppression circuit is shorted out and the transient voltage is a protection voltage, the short-circuit protection circuit disconnects a loop where the transient suppression circuit is located. The short-circuit protection circuit has a turned-on state and a turned-off state; the short-circuit protection circuit is in a turned-on state when the transient suppression circuit is shorted out and the transient voltage is greater than the protection voltage; and the short-circuit protection circuit is in a turned-off state when the transient suppression circuit is shorted out and the transient voltage is a protection voltage.

Abstract: Systems and methods are presented for reducing electrical interference in measurement-while-drilling (“MWD”) data. An example may include, among other features a MWD data acquisition system including an analog data reception for receiving analog MWD data, an analog-to-digital conversion circuit, at least one isolation circuit for electrically isolating the analog data reception circuit and the analog-to-digital conversion circuit from a digital data transmission circuit. In some embodiments, a power isolation circuit may electrically isolate an analog section power domain from a digital section power domain. The isolation techniques may improve the quality of the analog signal received.

Abstract: A system for monitoring medical conditions includes a conformable medical monitoring device that includes a first substrate layer, which includes an electronics module, many signal traces, and at least one electrode, such that one or more of the many signal traces electrically couple the at least one electrode to the electronics module. The conformable medical monitoring device includes a second substrate layer positioned over the electronics module, the first substrate layer, or any combination thereof to insulate the electronics module, the first substrate layer, or any combination thereof. The conformable medical monitoring device also includes a third substrate layer positioned over the second substrate layer, such that the third substrate layer reduces electromagnetic interference caused by a voltage pulse and includes an adjustable system coupled to the first substrate layer and that changes a position of the at least one electrode relative to the electronics module.

Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.

Abstract: An embodiment of the invention provides an apparatus for detecting electrostatic discharges (ESD) events, comprising: an ESD detector configured to determine at least one process window that will permit the ESD detector to detect an ESD event; at least one antenna coupled to said ESD detector; and said ESD detector calibrated for at least one discharge energy. Another embodiment of the invention provides: a method for detecting electrostatic discharges (ESD) events, comprising: determining at least one process window that will permit an ESD detector to detect an ESD event; and calibrating the ESD detector for at least one discharge energy.

Abstract: A controller for a valve assembly that is configured to meet requirements for use in hazardous areas. These configurations may regulate flow of instrument air to a pneumatic actuator to operate a valve. The controller may comprise enclosures, including a first enclosure and a second enclosure, each having a peripheral wall forming an interior space, and circuitry comprising a barrier circuit disposed in the interior space of one of the enclosures that power limits digital signals that exits that enclosure. In one example, the peripheral wall of enclosures are configured to allow instrument air into the interior space of the first enclosure but to prevent instrument air from the interior space of the second enclosure.

Abstract: An apparatus of preventing ESD and EMP coupled between a signal input and a signal output is provided with a first diode of forward bias including a positive terminal and a negative terminal connected to the signal input and ground respectively; and a first diode of reverse bias including a negative terminal and a positive terminal connected to the signal input and the ground respectively. The semiconductor is a diode including a p-type semiconductor region made of semiconductor material having a predetermined band gap and an n-type semiconductor region made of semiconductor material having a predetermined band gap. The predetermined band gap is greater than 3 eV. The diode operates in forward bias to discharge current generated by ESD and/or EMP. A method of preventing ESD and EMP is also provided.

Abstract: A sensor 1 is arranged to read data transmitted on a digital vehicle network. The sensor comprises a wire holding unit 3, and a sensing unit 5. The wire holding unit and sensing unit are connectable to one another, the sensor further comprising a locking mechanism to lock the wire holding unit and the sensing unit together, when the wire holding unit and sensing unit are connected to one another.

Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.

Abstract: The present invention provides an output circuit with electrostatic discharge (ESD) protection in a semiconductor chip of a source driver. The source driver is configured to drive a display panel. The output circuit includes an output buffer, an output pad, a switch and a first resistor. The switch is coupled between the output buffer and the output pad, wherein data voltages for driving the display panel are transmitted from the output buffer to the output pad via the switch. The switch includes a first metal oxide semiconductor (MOS) transistor, which includes a first terminal coupled to the output pad, a bulk terminal and a gate terminal. The first resistor is coupled between the bulk terminal of the first MOS transistor and a first power supply terminal.

Abstract: An electrostatic discharge protection (ESD) circuit is provided for a semiconductor element. The semiconductor element includes first and second drain/source electrodes and is surrounded by a deep well region. The ESD circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode and a power terminal and includes a first control terminal electrically connected to the deep well region and generates a first control signal. The first discharge circuit is controlled by the first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to potential states of the deep well region and the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

Abstract: A composite circuit protection device includes first and second positive temperature coefficient (PTC) components, a voltage-dependent resistor, and first, second and third conductive leads. The first PTC component includes a first PTC layer, and first and second electrode layers respectively disposed on two opposite surfaces of the first PTC layer. The second PTC component includes a second PTC layer, and third and fourth electrode layers respectively disposed on the two opposite surfaces of the second PTC layer. The voltage-dependent resistor is connected to the second and third electrode layers. The first, second and third conductive leads are bonded to the first electrode layer, the voltage-dependent resistor, and the fourth electrode layer, respectively.

Abstract: An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.

Abstract: A device includes a sensor configured to provide a temperature-sensitive voltage and an oscillator. The sensor includes: a first transistor, being a diode-connected transistor; a second transistor coupled between a source of the first transistor and ground, wherein a gate of the second transistor is controllable by an enable signal; and a current source configured to control the first transistor and comprising a third transistor, a drain of which is directly connected to a drain of the first transistor, the third transistor being a diode-connected transistor. The oscillator includes: a digital delay cell; and an adjustment device configured to, based on the temperature-sensitive voltage, adjust a delay of the digital delay cell. The digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Abstract: Disclosed are an electrostatic discharge circuit and a method for preventing malfunctions of an integrated circuit due to a reverse connection of a power source. The electrostatic discharge circuit includes at least one MOSFET for providing an electrostatic discharging current path, and a control circuit coupled to the at least one MOSFET. When an external power supply is reversely connected, the control circuit is configured to change a potential of a body of at least one MOSFET, such that the at least one MOSFET is turned off, thereby preventing the integrated circuit from malfunctioning caused by a current generated by the reverse connection of the external power source flowing through the at least one MOSFET.

Abstract: The present invention provides an on-chip surge protection circuit, including a low voltage rail, a negative transmitter differential output, a positive transmitter differential output, and a surge protection component. The surge protection component includes a first end, a second end, and a control end. The first end is connected to the transmitter differential output N. The second end is connected to the transmitter differential output P. The control end is connected to the low voltage rail.

Abstract: An over current protection system includes a first resistor, a second resistor, a third resistor, and an electrostatic discharge circuit. The first resistor includes a first terminal for receiving an input voltage, and a second terminal. The second resistor includes a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to a ground terminal. The third resistor includes a first terminal, and a second terminal coupled to the first terminal of the second resistor. The electrostatic discharge circuit is coupled to the first terminal of the third resistor. When the input voltage is an abnormal voltage, the electrostatic discharge circuit is enabled for maintaining a voltage at the second terminal of the third resistor within a normal voltage range.

Abstract: A radiofrequency transmission line configured so as to allow a radiofrequency electrical signal to be transmitted between a first end and a second end, the transmission line including a main conductor and a ground plane electrically connected to an electrical ground of the transmission line. The ground plane includes a set of portions that are connected in series between the first end and the second end and a set of second capacitors, the set of portions including a set of second portions, each second capacitor being inserted between two contiguous second portions.

Abstract: A test circuit for preventing an electrostatic discharge (ESD) device from electricity leakage and a display panel having the same are provided. The test circuit includes a switch module between the ESD device and the display panel to control an electrical connection between the ESD device and the display panel, and prevent the display panel from electricity leakage, so as to reduce power consumption.

Abstract: An electrical level shifting chip and a display device are provided. The electrical level shifting chip includes an electrical level shifting module, an overcurrent protecting module, and a controlling module. The control module is configured to detect whether the electrical level shifting chip is in an electrostatic discharge test mode and to disable the overcurrent protecting module when the electrical level shifting chip is in the electrostatic discharge test mode. Avoid the overcurrent protecting module from being disturbed and causing malfunction during an electrostatic discharge test.

Abstract: A semiconductor device arrangement and a method of operating a semiconductor device arrangement. The semiconductor device can be arranged for bidirectional operation. The semiconductor device arrangement can comprise: a field effect transistor comprising first and second input terminals; a control terminal; a first diode connected between the first terminal and the control terminal; and a second diode connected between the second terminal and the control terminal; wherein the first terminal and the second terminal are configured and arranged to be connected to respective signal lines.

Abstract: A high-frequency module includes a mounting substrate, electronic components, a sealing resin, and land conductors. The mounting substrate includes a front surface, a rear surface, and a side surface. The land conductors are provided on the rear surface. The electronic components are mounted on the front surface of the mounting substrate. A distance between the mounting surface of the land conductor near the side surface and the rear surface of the mounting substrate is larger than a distance between the mounting surface of the land conductor closer to the center than the land conductor near the side surface and the rear surface of the mounting substrate.

Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.

Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.

Abstract: Systems and methods are provided for 8-channel surge protection for a network utilizing Power Over Ethernet (PoE). Four Bob Smith terminations are arranged such that one Bob Smith termination is coupled to each of four PoE nodes. Each Bob Smith termination includes a capacitor and a resistor pair coupled in series between its respective PoE node and a respective Bob Smith termination node, wherein a first pair of the Bob Smith terminations is connected between their respective PoE nodes and a first Bob Smith node and a second pair of the Bob Smith terminations is connected between their respective PoE nodes and a second Bob Smith node. The first Bob Smith node is capacitively isolated from ground via a first terminating capacitor component and a second Bob Smith node is capacitively isolated from ground via a second terminating capacitor component separate from the first terminating capacitor component.

Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.

Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.

Abstract: A circuit for protecting against electrostatic discharges includes two avalanche circuit components having different turn-on delays with respect to a beginning of an electrostatic discharge. The two avalanche circuit components are coupled in parallel. The avalanche circuit component closer to an output node has a turn-on delay on the order of 30 ns, while the avalanche circuit component closer to an input node has a turn-on delay on the order of 1 ns.

Abstract: An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N?1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N?1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.

Abstract: An apparatus of a computing system, a computer-readable medium, a method and a system. The apparatus comprises an input/output interface and one or more processors connected to the input/output interface and adapted to perform a first reading of first fuse data stored in a fuse array storage circuitry to result in read first fuse data, and receive the read first fuse data from the fuse array storage circuitry through the input/output interface; after a random time-delay, perform a second reading of second fuse data stored in the fuse array storage circuitry to result in read second fuse data, and receive the read second fuse data from the fuse array storage circuitry through the input/output interface; and compare the read first fuse data with the read second fuse data, and if there is no match, halt a boot-up of the computing system.

Abstract: A gate driver system includes a gate driver having a first input for receiving a digital input signal, a second input for receiving a short circuit protection signal, and output for driving a power device; a current reconstruction circuit having a first input for receiving a voltage across an inductance associated with the power device, a second input for receiving a current associated with the power device, a third input for receiving the digital input signal, and an output for providing a sensed power device current; and a comparator having a first input coupled to the output of the current reconstruction circuit, a second input coupled to a reference, and an output coupled to the second input of the gate driver.

Abstract: An air gap metal tip structure is provided for (ESD) protection. The structure includes first and second metal tips disposed along at least one horizontal axis that is parallel to a upper substrate and a lower substrate. The structure includes an air chamber formed between the upper and lower substrate within which the first metal tip and the second metal tip are disposed. The air chamber includes a portion between points of the metal tips. The structure includes an under fill level disposed between the lower and upper substrates, and above one or more layers having the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the metal tips to maintain the ESD protection for subsequent arcs.

Abstract: A variable capacitance element is provided that includes a plurality of resistance elements that form a path for applying a control voltage to the electrodes of a plurality of variable capacitance portions connected in series. These resistance elements include first distribution resistance elements, second distribution resistance elements, a first shared resistance element, and a second shared resistance element. Moreover, vertical sectional areas of the first shared resistance element and the second shared resistance element with respect to conducting directions thereof are larger than the vertical sectional areas of the first distribution resistance elements and the second distribution resistance elements with respect to conducting directions thereof.

Abstract: The subject technology provides for an architecture that isolates two interfaces of a circuit with an isolating communication element while also protecting against overstress transients such as electro-static discharge (ESD) and other electrical overstress (EOS) transients across the isolating communication element that can be significantly larger than the ESD rating of the isolating communication element, and/or that may be repeated in succession. The subject technology provides isolation using a two die implementation with an isolation interface including an isolation tub in each die, or a single die containing both isolation tubs in the die. The two dice include respective substrates that are connected together and float with respect to any signal or ground. The isolation enables a large offset voltage on the order of hundreds of volts to exist between the sides. Being relatively large, each isolation tub can handle a significant amount of energy.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.

Abstract: A device for acquiring signals from a sensor, the device comprising a differential amplifier, two bias resistors for biasing of the measurement device, a common mode and differential mode filter circuit, and two lightning limiter components. The differential amplifier is of the high common mode range type, the limiter components are dimensioned to reduce a lightning voltage to a maximum voltage value of the order of about one hundred volts and the filter circuit and the bias resistors are dimensioned to withstand that maximum voltage value. A correspond method for protecting a device against lightning.

Abstract: An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.

Abstract: A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

Abstract: Provided is a current measuring device for measuring current, including a conductor adapted to pass current therethrough, a circuit board with a wire, the wire being adapted to extract a voltage signal from the conductor, a cover member adapted to house the circuit board, first fixing means provided on the cover member, and second fixing means fixed in combination with the first fixing means, in which the conductor is mounted between the first fixing means and the second fixing means.

Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.

Abstract: An electrostatic discharge measuring device includes an integrated circuit including a collector, a discharge pad and an ESD detector circuit coupled to the collector and discharge pad. The ESD detector circuit includes a device that detects occurrence and magnitude of an electrostatic discharge between the collector and the discharge pad. In one embodiment, the device is a metal-oxide-semiconductor capacitor. In another embodiment, the device is a thin film storage bitcell. In one embodiment, the electrostatic discharge measuring device is contained in a test microelectronic package. A method includes running the test microelectronic package through a manufacturing process to determine location during manufacturing at which an electrostatic discharge occurs when an externally-similar production microelectronic packages is run through the same manufacturing process.

Abstract: A coupled antenna apparatus particularly well adapted for small form factor, metal encased applications that utilize satellite wireless links, e.g. GPS. Certain examples use electromagnetic feeding that includes one or more separate feed elements that are not galvanically connected to a radiator element of the antenna. Additionally, one radiator element of the antenna can be located on an outermost surface of a bezel of an electronic device, for example a wrist-wearable device. A resonating circuit is housed within an electronic device and electrically coupled to such an outer radiator element.

Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

Abstract: An electrostatic discharge protection device is provided. A voltage selection circuit selects a voltage having a higher voltage value among a reference voltage and a voltage on a conductive path and supply the selected voltage to a RC latch self-feedback circuit, so that the RC latch self-feedback circuit ties a voltage of an input end of a RC control circuit when the electrostatic discharge does not occur, and disconnect a switch that conducts an electrostatic current.