With Specific Dielectric Material Or Layer Patents (Class 361/750)
  • Patent number: 6734370
    Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: May 11, 2004
    Assignee: Irvine Sensors Corporation
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Patent number: 6731509
    Abstract: In a method of mounting a planar electronic circuit chip onto a flexible sheet together with another planar electronic element, the electronic circuit part and the another electric element are selected so that the planar surface of the another electric element is greater than the planar surface of the electronic circuit chip, and the another electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the another electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: May 4, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Sobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 6707677
    Abstract: A chip-packaging substrate and test method therefor. The chip-packaging substrate includes at least one package area and a connection area enclosed by and connected to the package areas. A test circuit is arranged within the connection area, passing through at least two wire layers and the insulation layer therebetween. The test circuit electrically connects the first electrodes. Failure of the chip-packaging substrate is detected when the test circuit is open between any two electrodes.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 16, 2004
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Han-Kun Hsieh, Wei-Feng Lin, Yi-Chang Hsieh
  • Patent number: 6705007
    Abstract: A double-sided flexible printed circuit board is manufactured by the following steps of: (a) forming a polyimide precursor layer on a first metal layer; (b) forming a second metal layer on the polyimide precursor layer; (c) patterning the second metal layer to form a second circuit layer or (c′) patterning the first metal layer to form a first circuit layer; and (d) imidating the polyimide precursor layer to form a polyimide insulating layer. The polyimide precursor layer is obtained by dissolving a polyamic acid or other polyimide precursor in N-methyl-2-pyrrolidone or the like and applying the resultant varnish to the first metal layer. The polyimide layer is then dried. The imidation ratio of the dried polyimide precursor layer is prevented from exceeding 50%.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: March 16, 2004
    Assignee: Sony Chemicals Corp.
    Inventors: Hideyuki Kurita, Masanao Watanabe
  • Patent number: 6703702
    Abstract: IC CHIP MOUNTING STRUCTURE has IC chips having protruding electrodes, a flexible printed circuit board having conductors connected to the protruding electrodes of the IC chips, and a protective plate attached to the flexible printed circuit board. The protective plate has openings to accommodate the driver IC chips. A resin member having a high heat conductivity is arranged in the opening in contact with the surface of the IC chip. The IC chip mounting structure can be attached to a chassis of a plasma display device so that heat generated by the driver IC chip is transferred to the chassis via the heat conductive resin member.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: March 9, 2004
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Hirokazu Inoue, Toyoshi Kawada, Yuji Sano
  • Patent number: 6700789
    Abstract: There has been a problem that a mode (a high-order mode) different from a basic propagation mode occurs at a point of a through conductor and a transmission characteristic deteriorates greatly. The present invention is a high-frequency wiring board wherein L>&lgr;/4 and &pgr;(A+B)≦&lgr; are satisfied in which L is a length of a through conductor, A is a diameter of the through conductor, B is shortest distances between the through conductor and a plurality of ground through conductors, &pgr; is a circle ratio and &lgr; is an effective wavelength of a high-frequency signal transmitted by the through conductor. It is possible to inhibit a high-order mode which occurs at a point of the through conductor.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: March 2, 2004
    Assignee: Kyocera Corporation
    Inventor: Takayuki Shirasaki
  • Patent number: 6690580
    Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: February 10, 2004
    Assignees: AMD, Inc., Motorola, Inc.
    Inventors: Cindy K. Goldberg, John Iacoponi
  • Patent number: 6664942
    Abstract: A liquid crystal display has a signal transmission film and a single integrated PCB for processing a gate driving signal and data driving signal. The signal transmission film includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: December 16, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Soo Kim, Choong-Seob Oh, Jin-Hyeok Park, Jin-Ho Park, Dong-Gyu Kim, Yong-Eun Park, Nam-Soo Kang, Gyu-Su Lee, Sin-Gu Kang
  • Publication number: 20030198032
    Abstract: The invention relates to an integrated circuit assembly and a method of making same. The method according to the invention comprising providing a flex substrate having one or more dielectric tape layers, assembling one or more semiconductor chips to said flex substrate, said semiconductor chips having an active surface and a plurality of contact pads on said active surface, providing one or more conductive layers on said flex substrate, said conductive layers forming the electrical connections required for the assembly, electrically connecting the contact pads to the conductive layers.
    Type: Application
    Filed: April 23, 2002
    Publication date: October 23, 2003
    Inventors: Paul Collander, Petri Nyberg, Vesa Korhonen, Olli Pekka Koistinen, Kari Koivunen
  • Patent number: 6636421
    Abstract: A method for datum sharing between modular computer system components, includes determining a position and orientation of a motherboard, defining at least one datum feature in a primary chassis describing the position and orientation of the motherboard, and defining at least one datum feature in a secondary chassis corresponding to the at least one datum feature in the primary chassis. An apparatus for datum sharing includes at least one datum feature of the primary chassis, at least one datum feature of the motherboard, wherein a location of the at least one datum feature of the primary chassis is based upon the at least one datum feature of the motherboard, and at least one datum feature of the secondary chassis, wherein a location of the at least one datum feature of the secondary chassis is based upon the location of the at least one datum feature of the primary chassis.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: October 21, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Jimmy Clidaras, Matthew Schutte
  • Patent number: 6633487
    Abstract: A required interlayer circuit board 1 is constituted so as to provide a punched portion in which only a collapsible cable portion 2 for connecting a plurality of component mounting portions to each other is exposed. An external layer board 6 is superimposed on at least one side of the internal layer circuit board 1 through an adhesive member 4 to which an opening portion 5 is formed at a position corresponding to the cable portion 2, the external layer substrate 6 having an opening portion 7 at a similar position. Thereafter, a wiring pattern for the component mounting portions is formed on the external layer board 6, and a blank and pierce process of the respective component mounting portions except the cable portion is carried out, thereby integrally connecting a plurality of the component mounting portions to each other through the collapsible cable portion.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: October 14, 2003
    Assignee: Nippon Mektron, Ltd.
    Inventors: Akihiko Toyoshima, Kunihiko Azeyanagi
  • Patent number: 6603201
    Abstract: A package substrate having sides, which is formed of multiple non electrically conductive layers laminated together. Each of the multiple non electrically conductive layers is formed of a first lamina and a second lamina bonded together in a resin matrix. The first lamina is formed of woven fibers having a first warp. The first warp of the first lamina is disposed at a positive orientation of a first angle from the sides of the package substrate, where the first angle is neither zero degrees nor ninety degrees. The second lamina is also formed of woven fibers, having a second warp. The second warp of the second lamina is disposed at a negative orientation of the first angle from the sides of the package substrate. Electrically conductive layers are dispersed between different ones of the multiple non electrically conductive layers, with electrical connections dispersed between different ones of the electrically conductive layers.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: August 5, 2003
    Assignee: LSI Logic Corporation
    Inventors: Manickam Thavarajah, Maurice O. Othieno, Severino A. Legaspi, Jr., Pradip D. Patel
  • Patent number: 6597580
    Abstract: A shielded serpentine extension, internal signal path and receptor result in a flexible shielded interface for a circuit board that can be formed consistent with efficient circuit board fabrication processes. The shielded serpentine extension, continuous with the circuit board, has a receptor at an end that is distal from the circuit board. The receptor has a signal contact and a shield contact adapted to receive a surface mount connector. A signal path internal to the serpentine extension couples the signal contact of the receptor to the circuit board. The serpentine extension has shielding disposed about the signal path that couples the shield contact to the circuit board.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: July 22, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Leonard M. Weber, Terrence R. Noe
  • Patent number: 6583364
    Abstract: The present invention pertains to a multilayer flexible wiring board. The multilayer flexible wiring board including first and second patterned wiring layers, a resin film interposed between a surface of the first wiring layer and a surface of the second wiring layer, and a bump connected to the surface of the second wiring layer, wherein the resin film is adapted to form an opening when the bump to force into the resin film and an ultrasonic wave is applied to the bump and the bump is left in the opening to electrically connect the top of the bump to the first wiring layer.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: June 24, 2003
    Assignee: Sony Chemicals Corp.
    Inventors: Hideyuki Kurita, Masanao Watanabe, Masayuki Nakamura, Mitsuhiro Fukuda, Hiroyuki Usui
  • Patent number: 6577508
    Abstract: A technique for eliminating electrically conductive vias is disclosed. In one embodiment, the technique is realized as an improved multilayer circuit board for eliminating electrically conductive vias. The multilayer circuit board has a top layer and a buried layer separated by at least one dielectric layer, wherein the buried layer includes an electrically conductive power plane portion and an electrically conductive ground plane portion. The improvement comprises a cavity in the multilayer circuit board extending through the top layer and the at least one dielectric layer so as to expose at least a portion of the power plane portion and the ground plane portion of the buried layer within the cavity.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: June 10, 2003
    Assignee: Nortel Networks Limited
    Inventors: Herman Kwong, Larry E. Marcanti, Aneta D. Wyrzykowska
  • Publication number: 20030047353
    Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Patent number: 6528145
    Abstract: A composite electronic and/or optical substrate including polymeric and ceramic material wherein the composite substrate has a dielectric constant less than 4 and a coefficient of thermal expansion of 8 to 14 ppm/°C. at 100° C. The composite substrate may be either ceramic-filled polymeric material or polymer-filled ceramic material.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Daniel George Berger, Shaji Farooq, Lester Wynn Herron, James N. Humenik, John Ulrich Knickerbocker, Robert William Pasco, Charles H. Perry, Krishna G. Sachdev
  • Patent number: 6506979
    Abstract: A method for manufacture of a circuit board and the board formed by the novel method. The method comprises selective plating of metallic reinforcing members, solder mount pads, signal lines and interconnections sequentially. The resultant board is desirably free of glass fiber reinforcement.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: January 14, 2003
    Assignee: Shipley Company, L.L.C.
    Inventors: James G. Shelnut, Charles R. Shipley
  • Publication number: 20030007332
    Abstract: Herein is disclosed an insulating resin composition for a multilayer printed-wiring board, comprising two or more kinds of resins which are different in etching rate by plasma treatment and which are not compatible with each other, so that the surface of the resulting insulating layer can be made uneven by the plasma treatment, whereby the bonding strength of the conductor layer to the said resulting insulating layer can be ensured, and heat resistance and electrically insulating properties required can be satisfied.
    Type: Application
    Filed: March 31, 2000
    Publication date: January 9, 2003
    Inventors: Yasuaki Seki, Takashi Ito, Shuji Mochizuki, Kiyonori Furuta, Toshihiko Hatajima
  • Patent number: 6504729
    Abstract: An electrically shielded housing for an electrical device and method therefor having an insert member disposed in a cavity of a non-conductive housing body member. The insert member includes a conductive inner surface portion disposed adjacent an outer surface portion of the body member cavity. A non-conductive outer surface portion of the insert member forms a housing cavity for receiving an electrical device. The conductive inner surface portion of the insert member at least partially electrically shields the electrical device, and the non-conductive outer surface portion of the insert member insulates the electrical device from the conductive inner surface portion thereof.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: January 7, 2003
    Assignee: Illinois Tool Works Inc.
    Inventors: Peter Michael Frederick Collins, Terry Dean Thomason, Ralph A. Hausler
  • Patent number: 6496382
    Abstract: A radio frequency identification tag is made with printed antenna coil integrated on a flexible substrate, and an integrated circuit area of the substrate adjacent the antenna coil for carrying circuit elements. The radio frequency identification tag is designed to be sufficiently robust to withstand the rigors of mail efficiency processing measurement applications.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: December 17, 2002
    Assignee: Kasten Chase Applied Research Limited
    Inventors: Donald Harold Ferguson, Mircea Paun
  • Patent number: 6490169
    Abstract: An electrically conductive circuit conductor 2 is disposed on an insulating resin substrate 1, an electrically conductive surface 3 of the circuit conductor is exposed from the resin substrate continuously in a longitudinal direction, and both side portions 4 of the conductive surface are covered and fixed by collar walls 5 of the resin substrate. A bus bar or an electrically conductive resin material is used as the circuit conductor 2. The bus bar 2 is insert-molded onto the resin substrate. The electrically conductive resin material is poured and solidified in a groove portion in the resin substrate. A contact terminal on a mating circuit side or electrical component side is brought into contact with the conductive surface of the circuit conductor 2. A second circuit board is laminated on the resin substrate, and an insertion hole for allowing the conductive surface of the circuit conductor 2 to be exposed is provided in the second circuit board, and the contact terminal is inserted in the insertion hole.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: December 3, 2002
    Assignee: Yazaki Corporation
    Inventor: Hiroshi Watanabe
  • Patent number: 6483713
    Abstract: An easier and cheaper way to obtain multilayer circuit board is by using a flexible circuit board and folding it in an organized pattern. Flexible circuit has the unique property of being a three-dimensional circuit that can be shaped in multiplanar configurations, rigidized in specific areas, and molded to backer boards for specific applications. The folded circuit is fabricated from a series of foldable circuit board strips and rigid circuit board strips which are interconnected, folded, and bonded into a composite structure. The foldable strips may have prefolds arranged so that a group of upper foldable strips and lower foldable strips are folded in opposite directions. A plurality of intermediate portions are stacked on each other by the folding the foldable strips in opposite directions. The folded circuit, can be bonded after a first fold, or folded further to achieve a greater reduction in area and subsequently be bonded as a composite multilayer structure.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 19, 2002
    Assignees: St. Jude Children's Research Hospital, The University of Tennessee Research Corp.
    Inventors: Sanjiv Singh Samant, Jinesh Jitendra Jain, Joseph Laughter
  • Patent number: 6480396
    Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: November 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryoji Ninomiya
  • Patent number: 6473314
    Abstract: A low cost radio frequency interference filter assembly comprises a multiple layer structure including a middle trace layer disposed between an upper ground layer and lower ground layer. Non-conductive insulation layers are disposed between the middle trace layer and the upper and lower ground layers. The upper layer includes input contacts, signal contacts, and capacitors which are coupled to the signal contacts and an upper grounded substrate. The middle trace layer includes a grounded substrate and trace lines which are coupled to the signal contacts of the upper layer by signal vias. The lower layer includes a grounded substrate. Ground vias are formed through the insulation layers to couple the middle grounded substrate to the upper and lower grounded substrates. The filter assembly may be formed as an integral projection of a printed circuit board assembly.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 29, 2002
    Assignee: Powerwave Technologies, Inc.
    Inventors: James Keith Custer, Pauline Mei-Seung Tong
  • Publication number: 20020139569
    Abstract: A flexible circuit incorporating electrostatic discharge (ESD) limiting features and being suitable for use in the fabrication of hard disk drives for computer applications. Conductive polymer strips are implemented to enhance the static dissipative characteristics of the flexible circuit and to protect magnetorestistive (MR) heads of a hard disk drive (HDD) from damage during the manufacture of the head gimbal assembly (HGA) of the HDD.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Inventor: Robert S. Dodsworth
  • Publication number: 20020131247
    Abstract: A dielectric resin composition comprising at least one type of epoxy resin and at least one type of cyanate ester which would react with said epoxy resin, together with a metal ion catalyst system, the ratio of the epoxy functional groups of said epoxy resin to the cyanate groups of said cyanate ester being in the range of from 1:0.8 to 1:1.4. Alternatively, a dielectric resin composition according to the invention may comprise a polyimide resin with side chain epoxy groups, a cyanate ester with two or more cyanate groups in the molecule, and a metal ion catalyst system. A multilayer circuit board having a multilayer structure comprising a core substrate and a required number of dielectric layers and wiring layers stacked alternately, wherein at least one of the dielectric layers is formed from a dielectric resin composition of the invention, is also disclosed.
    Type: Application
    Filed: January 11, 2002
    Publication date: September 19, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Nawalage Florence Cooray
  • Publication number: 20020131246
    Abstract: Defect-free dielectric coatings comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The dielectric coatings are useful in a number of contexts, including the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric coatings are prepared by admixing, in a solvent, a polymeric nitrogenous porogen with a high temperature, thermosetting host polymer miscible therewith, coating a substrate surface with the admixture, heating the uncured coating to cure the host polymer and provide a vitrified, two-phase matrix, and then decomposing the porogen. The dielectric coatings so prepared have few if any defects, and depending on the amount and molecular weight of porogen used, can be prepared so as to have an exceptionally low dielectric constant on the order of 2.5 or less, preferably less than about 2.0.
    Type: Application
    Filed: March 14, 2001
    Publication date: September 19, 2002
    Inventors: Craig Jon Hawker, James Lupton Hedrick, Elbert Emin Huang, Victor Yee-Way Lee, Teddie Magbitang, David Mecerreyes, Robert Dennis Miller, Willi Volksen
  • Patent number: 6423470
    Abstract: A covercoated base substrate, comprising a base substrate and a photoimageable covercoat layer having a lead portion extending beyond at least one, wherein the lead portion has a controlled offset distance from the edge, and a printed circuit made from such base substrate having at least one conductor including a trace and a lead wherein the covercoat has a lead portion covering at least one lead. A base substrate may also have an opening formed therethrough, the opening defining an interior edge wherein the covercoat extends beyond that interior edge.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: July 23, 2002
    Assignee: 3M Innovative Properties Company
    Inventors: John B. Scheibner, Robert M. Anderton, David L. Buster, Kristine J. Williams
  • Patent number: 6423905
    Abstract: A printed wiring board having a layered composite of metal planes and dielectric layers. At least one of the dielectric layers has a modulus lower than the modulus of the remaining dielectric material layers. A plating, extending through the layered composite, has a first land on a first external surface of the layered composite, a second land on a second external surface of the layered composite, and a barrel extending between the first land and the second land. The lower modulus dielectric material layer deforms during thermal excursions of the printed wiring board in such a way as to reduce the strains imposed on both the lands and the barrel of the plated through holes.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: July 23, 2002
    Assignee: International Business Machines Corporation
    Inventors: William L. Brodsky, Kevin T. Knadle, John M. Lauffer, Douglas O. Powell, David J. Russell
  • Patent number: 6417461
    Abstract: A circuit substrate in which the conductor portions constituting the functional devices formed in the insulating board have interfacial electric conductivities &sgr; of not larger than 2.90×107 &OHgr;−1·m−1 to greatly lower the insertion losses.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: July 9, 2002
    Assignee: Kyocera Corporation
    Inventors: Seiichi Hirahara, Akira Nakayama, Akira Imoto, Shuji Nakazawa, Tatsuji Furuse
  • Patent number: 6403892
    Abstract: A flex or TAB product suitable for chip carrier applications wherein the flex reliability problems caused by copper dendrite growth and lead bending during power and thermal cycling are reduced by application of special coatings to lead areas of the flex tape.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: June 11, 2002
    Assignee: International Business Machines Corporation
    Inventors: Claudius Feger, Teresita Ordonez Graham, Kurt Rudolph Grebe, Alphonso Philip Lanzetta, John Joseph Liutkus, Linda Carolyn Matthew, Michael Jon Palmer, Nelson Russell Tanner, Ho-Ming Tong, Charles Haile Wilson, Helen Li Yeh
  • Patent number: 6396706
    Abstract: Separate heating elements are embedded in a printed circuit board near integrated circuit (IC) packages or other parts mounted on the circuit board. Each heating element supplies heat to the part residing near it in response to an input voltage pulse. The heating elements are used to selectively melt solder or adhesives attaching the parts to the circuit board so that they can be easily removed or to temporarily melt solder or cure adhesive when the parts are mounted on the circuit board. The heating elements are also used to supply heat to IC packages for regulating their operating temperatures.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: May 28, 2002
    Assignee: Credence Systems Corporation
    Inventor: Paul D. Wohlfarth
  • Patent number: 6395993
    Abstract: The present invention aims to manufacture a reliable multilayer flexible wiring board at high yield. Flexible wiring board 10 used for multilayer flexible wiring board 40 of the present invention has metal coating 14 on the surface of metal wiring film 19, and metal coating 14 is exposed within the contact region. A wall member rising above the surface of metal coating 14 is provided around the exposed metal coating 14. The wall member is formed of wall face 23 of opening 17 in resin film 15 at the top of metal wiring film 19, for example. When bump 34 having low-melting metal coating 36 is contacted with metal coating 14 in said contact region and heated above the melting point of the solder metal under pressure, low-melting metal coating 36 melts. The molten low-melting metal is stopped by wall face 23 from overflowing outside the contact region so that any bridge cannot be formed by the solder metal between metal wiring film 19.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: May 28, 2002
    Assignee: Sony Chemicals Corp.
    Inventors: Masayuki Nakamura, Mitsuhiro Fukuda
  • Patent number: 6396709
    Abstract: To increase the elasticity of an elastically deformable middle section of a printed-circuit board having at least two rigid circuit board sections provided with electric and/or electronic components and interconnected by the middle section, the middle section being provided with printed circuit traces extending from the first rigid section to the second rigid section, at least one opening is made in the elastically deformable middle section, the region of the middle section surrounding the opening forming at least two bars extending in a direction from the first rigid section to the second rigid section and laterally bordering the at least one opening, the printed circuit traces being arranged on the bars.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: May 28, 2002
    Assignee: Robert Bosch GmbH
    Inventor: Franz Schmich
  • Patent number: 6390639
    Abstract: A cover portion 20 which covers a spot-like light source 8 is provided on the printed circuit board (FPC) 9, thereby giving electrical insulation from the surrounding. Therefore, even if a metallic frame is disposed close to the spot-like light source 8, the spot-like light source 8 is prevented surely from shortcircuiting with the metallic frame. Since the cover portion 20 covers the surrounding of the spot-like light source 8, light leakage from the spot-light like source 8 can be minimized and light emitted from the spot-like light source 8 can be used efficiently.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: May 21, 2002
    Assignee: Minebea Co., Ltd.
    Inventors: Shingo Suzuki, Koichi Toyoda
  • Patent number: 6388888
    Abstract: A semiconductor device comprising a patterned wiring including a connector for external connection formed on an elongate base film, a semiconductor element or the semiconductor element and a component other than the semiconductor element mounted on and electrically connected with a portion for connection of the patterned wiring, an elongate reinforcement member provided on a surface of the base film opposite to a surface on which the patterned wiring is formed, the reinforcement member having sprocket holes at positions corresponding to the lengthwise sides of the base film, wherein the reinforcement member is further provided on said opposite base film surface in a region corresponding with a region on which the connector for external connection is formed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: May 14, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiharu Seko, Kenji Toyosawa
  • Patent number: 6380493
    Abstract: To provide a circuit board, having a circuit pattern of adequate high-frequency characteristics, for transmitting high-frequency electric signals at high speed, a circuit board, including a base layer formed of insulating material and a conductive layer formed on the base layer in the form of a specified circuit pattern, is so constructed that an air layer is made to lie between lines of wire of the circuit pattern or is so constructed that the lines of wire are covered with the cover layer but land portions of the base layer extending between the lines of wire are not covered with the cover layer. This construction of the invention enables dielectric constant between the lines of wire to be reduced and, as a result of this, the capacitance between the lines of wire can be reduced to provide improved high-frequency characteristics of the circuit pattern.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: April 30, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Shigenori Morita, Yasuhito Ohwaki, Tadao Ohkawa, Toshihiko Omote
  • Patent number: 6377408
    Abstract: A lens barrel includes a fixed lens tube of cylindrical shape and a plurality of operation parts of push type, wherein the plurality of operation parts are interconnected by a ring-shaped elastic member and are attached to the fixed lens tube. This structural arrangement of the lens barrel effectively simplifies assembly processes in the manufacture of lens barrels.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: April 23, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsuru Shinohara
  • Patent number: 6362436
    Abstract: Printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package. The distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased. The board has at least two blind via holes in one solder-balls-fixing pad.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: March 26, 2002
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Hidenori Kimbara, Nobuyuki Ikeguchi, Katsuji Komatsu
  • Patent number: 6350957
    Abstract: A circuit board which is formed with bump patterns subject to a narrow variation in height on the surface of the circuit board, and which permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 26, 2002
    Assignees: Meiko Electronics, Co., Ltd., Machine Active Contact Co., Ltd.
    Inventors: Noboru Shingai, Tatsuo Wada, Katsuro Aoshima
  • Patent number: 6344792
    Abstract: A method of manufacturing and testing an electronic circuit, the method comprising forming a plurality of conductive traces on a substrate and providing a gap in one of the conductive traces; attaching a circuit component to the substrate and coupling the circuit component to at least one of the conductive traces; supporting a battery on the substrate, and coupling the battery to at least one of the conductive traces, wherein a completed circuit would be defined, including the traces, circuit component, and battery, but for the gap; verifying electrical connections by performing an in circuit test, after the circuit component is attached and the battery is supported; and employing a jumper to electrically close the gap, and complete the circuit, after verifying electrical connections.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: February 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Rickie C. Lake, Curtis M. Medlen
  • Publication number: 20020007963
    Abstract: An improved structure of printed circuit board (PCB) under pushbutton comprises a base layer and an insulation membrane, wherein a plurality of conductive portions and corresponding contact portions are printed on the base layer and the insulation membrane respectively. A plurality of insulation portions is printed on each contact portion along its circumference; and, no glue will be applied on a corridor between every pair of the conductive potions in the base layer and the contact portions in the insulation membrane when c ombining the insulation membrane to the base layer by gluing or direct printing. By this arrangement, an air channel can be reserved for being applicable to various button groups or waterproof membrane PCBs.
    Type: Application
    Filed: September 24, 1999
    Publication date: January 24, 2002
    Inventor: CHIN-WEN CHOU
  • Patent number: 6331678
    Abstract: A device with a multi-layered micro-component electrical connector. The multi-layer micro-component electrical connector includes a dielectric layer, a micro-mesh of a first electrical conductor secured to the dielectric layer, and a second electrical conductor secured to and contacting the micro-mesh to provide electrical communication. The dielectric layer has a dielectric layer thermal expansion coefficient and the first electrical conductor has a thermal expansion coefficient different from the dielectric layer thermal expansion coefficient. Due to the presence of the micro-mesh the device is operable at temperatures above 250° C. without delamination or blistering of the first electrical conductor from the dielectric layer.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: December 18, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Tak Kui Wang, Phillip W. Barth, Michel G. Goedert
  • Patent number: 6326554
    Abstract: A surface mountable flexible interconnect and component carrier (10) for connecting to a main circuit board consists of a flex circuit (12) with solder pads (14) on one side for receiving an electronic component (15). There is an array of solderable pads (16) on the other side of the flex circuit, and each of the pads in the array has a solder bump (18) fused to it. The array of solderable solder pads (16) is electrically connected to the solder pads (14) for receiving the electronic component (15) by means of electrically conductive vias in the flexible film. A rigid carrier (20) is used to hold the flex circuit in position prior to placement on the circuit board. An opening (26) in the rigid carrier is strategically located so that the electronic component can be soldered to the solder pads.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: December 4, 2001
    Assignee: Motorola, Inc.
    Inventors: Joseph G. Gillette, Scott F. Musil
  • Patent number: 6320137
    Abstract: A printed circuit including a dielectric substrate and a conductive trace attached to a surface of the dielectric substrate. The trace includes a base layer and a coverplate layer on a portion of the base layer. The coverplate layer defines a coverplate edge on the base layer. A protective layer is formed on a portion of the coverplate layer. The protective layer extends beyond the coverplate edge onto at least a portion of the base layer of the trace. A key aspect of the present invention is that the protective layer overlaps the coverplate edge of each trace to reduce the potential for corrosion of the base layer at the coverplate edge.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: November 20, 2001
    Assignee: 3M Innovative Properties Company
    Inventors: Lora C. Bonser, Terry F. Hayden, Robert J. Schubert
  • Patent number: 6320751
    Abstract: A frame sheet comprises a core sheet, and oversheets. A recess is formed in the sheet frame. The oversheet is left in the recess in the sheet frame, and an IC carrier is mounted in the recess. The IC carrier is held, adhered to the oversheet left in the recess.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: November 20, 2001
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Mitsunori Takeda, Eiichi Igarashi, Hideyo Yoshida
  • Patent number: 6316734
    Abstract: Circuit and circuit carries include a dielectric substrate having a conductive layer mounted thereon. The conductive layer is patterned to define a plurality of spaced apart conductive elements. A static charge dissipative layer is in contact with and extending between at least two of the conductive elements. The static charge dissipative layer has a surface resistivity of between about 1×105 and about 1×1010 ohms/□. The static charge dissipative layer is made of a material selected from the group consisting of diamond-like carbon, silicon nitride, boron nitride, boron trifluoride, silicon carbide and silicon dioxide. Circuits and circuit carriers according to the present invention allow static charges to be controllably and reliably dissipated from a surface of the circuit or circuit carrier such that the potential for damage from static discharge to electrical components connected to the circuit is reduced.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: November 13, 2001
    Assignee: 3M Innovative Properties Company
    Inventor: Rui Yang
  • Patent number: 6310298
    Abstract: A substrate for a plurality of electronic assemblies includes a strip of printed circuit board (PCB) material including a surface and a plurality of segments. Each segment is adapted to receive at least one electronic component and is arranged to be singulated into a plurality of individual electronic assemblies. Each segment has a perimeter portion located generally about the periphery of the segment, with the surface being covered with a solder mask, except for the perimeter portion.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: October 30, 2001
    Assignee: Intel Corporation
    Inventors: Joseph C. Barrett, Mark P. Jamieson
  • Patent number: 6297964
    Abstract: A semiconductor device comprising an insulating film having a device hole, a plurality of bumps formed on the insulating film, a plurality of first leads having end faces thereof exposed on an outline edge of the insulating film, each of the first leads being electroplated and connected with one of the bumps, a plurality of second leads having end portions thereof protruding into the device hole, each of the second leads being electroplated and connected with one of the bumps, and a semiconductor chip connected with the end portions of the second leads in the device hole. The insulating film is outlined to have a cut in a region including each of the exposed end faces of the first leads.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: October 2, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto