With Particular Conductive Material Or Coating Patents (Class 361/751)
  • Patent number: 7485361
    Abstract: An object of the present invention is to provide a multi-layered printed wiring board which does not require roughening such as black oxide treatment and the like on inner layer circuits. For the purpose of achieving this object, there is adopted a multi-layered printed wiring board characterized by comprising a primer resin layer P comprising exclusively a resin between each inner layer circuit Ci formed without roughening and an insulating resin layer 5 of the multi-layered printed wiring board.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: February 3, 2009
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Kensuke Nakamura, Tetsuro Sato
  • Patent number: 7479013
    Abstract: A printed board is able to cool an electronic component with high efficiency without requiring a heatsink for cooling the electronic component while preventing upsizing of the electronic device. A method for manufacturing such a printed board with high efficiency is also disclosed. Since a carbon layer principally made of carbon and having excellent heat conductivity is provided inside an insulator or on a surface of the insulator in a laminated form, heat generated by the electronic component when the electronic component is energized is conducted to the carbon layer, diffused through the carbon layer, and then radiated to the outside. Therefore, the heat generated by the electronic component can be reliably radiated by heat conduction to the carbon layer and heat diffusion through the carbon layer, thereby cooling the electric component with high efficiency.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: January 20, 2009
    Assignee: U-AI Electronics Corporation
    Inventors: Masanori Takezaki, Masayuki Komaru, Haruki Nitta, Takafumi Yagi, Yoshiyuki Mizuno
  • Publication number: 20090001550
    Abstract: A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy
  • Publication number: 20080310129
    Abstract: A structure of a tag integrated circuit flexible board includes a base material, one surface thereof having an adhesive layer; and a plurality of integrated circuit flexible boards that are arranged adjacent to one another and adhered on the adhesive layer of the base material. The integrated circuit flexible board includes an insulating heat-conductive material, and a conductive circuit layer provided on a surface of the insulating heat-conductive material and formed of a plurality of sections of circuits.
    Type: Application
    Filed: August 25, 2008
    Publication date: December 18, 2008
    Inventor: Pei-Choa WANG
  • Patent number: 7455915
    Abstract: Application of a conductive material with a compliant underlayer onto selected pads of a substrate, includes forming at least one padstack, by patterning a sheet including a stack of material layers. Padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: November 25, 2008
    Inventor: Morgan T. Johnson
  • Patent number: 7452612
    Abstract: Provided is a wiring portion capable of suppressing diffusion from occurring in a wiring portion or between the wiring portion and a substrate. In the wiring substrate, a first high melting point metal portion 18 having a melting point higher than Au and Ag is provided between an Au wiring portion 15 and an Ag wiring portion 17. The higher the melting point of the first high melting point metal portion 18, the lower a coefficient thereof, that is, the harder diffusion occurs. In addition, the first high melting point metal portion 19 functions as a barrier material which adequately suppresses Ag from being diffused from the Ag wiring portion 17. By providing the first high melting point metal portion 18 between the Au wiring portion 15 and the Ag wiring portion 17, it is possible to more efficiently suppress Ag from diffusion, in comparison with a case where the Ag wiring portion and the Au wiring portion are in contact with each other.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: November 18, 2008
    Assignee: Alps Electric Co., Ltd.
    Inventor: Shinji Murata
  • Patent number: 7446261
    Abstract: A flexible circuit comprises a flexible substrate having first and second opposing surfaces. The flexible substrate can include multiple layers. A plurality of electrical traces can be mounted on either or both surfaces of the flexible substrate. A plurality of electrical components can also be mounted on either or both surfaces of the flexible substrate. A plurality of tooling cutouts is recessed in the sides of the flexible circuit. The tooling cutouts can have various shapes, such as, but not limited to, semi-circular, multiple straight edges, a single or multiple curved edges, etc. The cutouts are used to position and hold the flexible circuit in at least one other device.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: November 4, 2008
    Assignee: Finisar Corporation
    Inventors: Dev E. Kumar, Donald A. Ice, Kinya Nippa
  • Patent number: 7430799
    Abstract: A method for preforming of two or more flexible cables in an arrangement consisting of a combination of rigid printed circuit boards and flexible cable sections extending therebetween. Moreover, also provided is an apparatus for the preforming of two or more flexible cable sections of a combination of rigid printed circuit boards and therewith interposed flexible cable sections which are adapted to interconnect the rigid printed circuit boards. The apparatus consists of a tool constituted of an elongated cylindrical member having a tapered leading end which narrows into an ultra-thin flat end section of a blade-like configuration, and which is adapted to be pushed between the flexible cables and so as to preform the flexible cable sections and cause them to yield in a predetermined outwardly bowed permanently relationship between the rigid printed circuit boards at the opposite ends thereof to lengthen the fatigue life of the conductors in the flexible cable sections.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: October 7, 2008
    Assignee: International Business Machines Corporation
    Inventors: Lee Curtis Randall, Thomas Stanley Truman, Daniel James Winarski, George G. Zamora
  • Patent number: 7423220
    Abstract: A conductive paste for multilayer electronic components which is to be directly printed on a ceramic green sheet, the conductive paste contains a conductive powder, a resin and an organic solvent, wherein the organic solvent contains at least one solvent selected from an alkylene glycol diacetate and an alkylene glycol dipropionate. A multilayer electronic component is obtained by firing at high temperature an unfired laminate prepared by alternately stacking ceramic green sheets and internal electrode paste layers in which each of the internal electrode paste layers is formed by the above conductive paste. The conductive paste has appropriate viscosity characteristics and long-term stability, which allows manufacturing highly reliable multilayer electronic components having excellent electrical characteristics, without causing sheet attack.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 9, 2008
    Assignee: Shoei Chemical Inc.
    Inventors: Toshio Yoneima, Kaori Higashi
  • Patent number: 7414851
    Abstract: The present invention relates to a flexible substrate. More particularly, the present invention relates to a flexible substrate for a display apparatus. A display apparatus according to an embodiment of the present invention comprises a display panel in which an electrode is formed, a heat sink plate formed on a rear side of the display panel, a driving board formed on a rear side of the heat sink plate, and a flexible substrate for connecting the electrode and the driving board, wherein the flexible substrate is directly grounded to the heat sink plate. Accordingly, the noise of pulses supplied from the flexible substrate can be prevented and damage to the flexible substrate can be prohibited.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: August 19, 2008
    Assignee: LG Electronics Inc.
    Inventor: Se Joon You
  • Publication number: 20080186687
    Abstract: A printed circuit board includes a base formed from a plurality of woven fibers, and signal traces laid on the base. Each of the signal traces includes at least a straight line segment. The signal traces are laid on the base in such a manner that the line segments of the signal traces mapped on the base cross the fibers at angles not equal to zero degrees.
    Type: Application
    Filed: June 20, 2007
    Publication date: August 7, 2008
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YU-HSU LIN, CHAN-FEI TAI, JENG-DA WU, CHIH-HANG CHAO
  • Publication number: 20080174975
    Abstract: Disclosed is a flexible wiring substrate which does not form anomalous deposition of tin-bismuth alloy plating, through prevention of exfoliation, during the process of plating with tin-bismuth alloy, of a solder resist layer. A method for producing the flexible wiring substrate is also disclosed.
    Type: Application
    Filed: February 28, 2008
    Publication date: July 24, 2008
    Applicant: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Hiroaki KURIHARA
  • Patent number: 7397672
    Abstract: The present invention provides a flip chip mounting substrate which comprises an electronic circuit composed of a circuit line and plural mounting pads connected to both ends of the circuit line formed on one surface of a base sheet, wherein the plural mounting pads are faced each other and spaced a pad clearance gap apart, and one or more semiconductor mounting paste guide paths are formed in the mounting pads. The flip chip mounting substrate can reduce voids that might be produced in the semiconductor mounting paste, when flip-chip-mounting an IC chip on a flip chip mounting substrate.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: July 8, 2008
    Assignee: Lintec Corporation
    Inventors: Yasukazu Nakata, Katsuyoshi Matsuura, Taiga Matsushita
  • Publication number: 20080148559
    Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer and a substrate folded around the interposer. Other embodiments are described and claimed.
    Type: Application
    Filed: March 4, 2008
    Publication date: June 26, 2008
    Inventors: Robert M. NICKERSON, Ronald L. SPREITZER, John C. CONNER, Brian TAGGART
  • Patent number: 7381902
    Abstract: A wiring board comprises a patterned wiring formed of electrically conductive resin composed primarily of silver and embedded into a substrate in a manner that a surface thereof is exposed above the substrate, and a covering conductor formed primarily of carbon covering the surface of the patterned wiring. The wiring board of this structure is superior in resistance to moisture absorption and water, prevents silver migration attributable to the moisture, and reduces contact resistance in the connection between a terminal portion of the wiring board and an external apparatus.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 3, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Norihito Tsukahara, Kazuhiro Nishikawa
  • Patent number: 7378345
    Abstract: A metal electroplating process of an electrically connecting pad structure of a circuit board and structure thereof are proposed. First, a circuit board with a patterned circuit layer formed on at least one surface thereof is provided, wherein the circuit layer defines a plurality of electrically connecting pads and electroplating lines connected to the electrically connecting pads. Then, a patterned resist layer is formed on the circuit layer of the circuit board with the electroplating lines being covered by the patterned resist layer and the electrically connecting pads being exposed from the patterned resist layer. Subsequently, an electroplating process is performed so as to form a metal protection layer on the electrically connecting pads exposed from the patterned resist layer. Then, the resist layer is removed and a solder mask layer is formed on the circuit board.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: May 27, 2008
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Pao Hung Chou
  • Patent number: 7359204
    Abstract: A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, first and second covers are movably attached to a case for selectively covering or exposing the I/O pads and the test features/pads of the module of the memory card.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: April 15, 2008
    Assignee: Amkor Technology, Inc.
    Inventors: Sang Jae Jang, Chul Woo Park, Jong Woon Choi, Jae Dong Kim, Choon Heung Lee, Chang Deok Lee
  • Patent number: 7335414
    Abstract: A printed circuit board has a flexible portion where a covering layer is exposed, and a rigid portion provided by forming a resistant layer on a part of the covering layer. To produce a camera module, a lens unit and a CCD are affixed to the printed circuit board through an adhesive, wherein the CCD is located inside the lens unit. The rigid portion has a top surface that is substantially equal in shape and size to an outline of a bottom surface of the lens unit, so the top surface of the rigid portion serves as a coating area for the adhesive.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: February 26, 2008
    Assignee: FUJIFILM Corporation
    Inventor: Setsu Takeuchi
  • Patent number: 7323642
    Abstract: Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yi-Sung Hwang, Ho-Tae Jin, Hwan-young Jang
  • Patent number: 7292448
    Abstract: A circuit substrate includes a first rigid substrate having a plurality of land portions located at a predetermined interval on one surface, a second rigid substrate having a plurality of second land portions located at a predetermined interval on one surface and a flexible wiring board sandwiched by the first and second rigid substrates and which has a plurality of third land portions corresponding to the first land portions on one surface and a plurality of fourth land portions corresponding to the second land portions on the other surface. In this circuit substrate, the second and fourth land portions are displaced from each other relative to the first and third land portions and at least part of the first and third land portions and at least part of the second and fourth land portions are electrically connected to each other, respectively.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 6, 2007
    Assignee: Sony Corporation
    Inventors: Toshichika Urushibara, Koji Shiozawa, Masakazu Okabe, Yukiko Hyodo, Yusuke Masuda, Tadayuki Miyamoto
  • Patent number: 7230187
    Abstract: A multi-layer printed wire board (PWB) structure optimized for improved drop reliability, reliable electrical connections under thermal load, and minimal thickness is provided, along with a mobile terminal, including the PWB. The PWB includes alternating conductive layers and insulative layers. The outermost three layers form an interconnect structure constructed of two conductive layers surrounding an insulative-coated conductive layer. The thicknesses of the various layers are optimized to have an increased resistance to mechanical shock resulting from, for instance, a drop onto a hard surface. In addition, the optimized PWB structure has a minimized thickness and an improved resistance to connection failures resulting from cyclical thermal loads.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: June 12, 2007
    Assignee: Nokia Corporation
    Inventors: Liangfeng Xu, Tommi Reinikainen, Arni Kujala, Wei Ren, Ian Niemi, Ilkka Kartio
  • Patent number: 7224046
    Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: May 29, 2007
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani
  • Patent number: 7208218
    Abstract: A method of providing a resistance to oxidation of Nickel at high temperatures by combining Ni powder with five percent Pt resinate, and heating the same to a temperature of 500° C. to 1300° C. Electro-conductive components serving as electrodes and the like comprise a Ni/Pt powder subjected to temperatures of between 500° C. and the respective melting points of Ni and Pt.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: April 24, 2007
    Assignee: Vishay Vitramon Incorporated
    Inventor: Vito A. Coppola
  • Patent number: 7189598
    Abstract: A receiving layer is formed from a thermosetting resin precursor. An interconnecting layer is formed on the receiving layer from a dispersion liquid containing conductive particles. Heat is applied to the receiving layer and the interconnecting layer to cure the thermosetting resin precursor and to bond the conductive particles together.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: March 13, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuya Otsuki, Hirofumi Kurosawa, Hiroshi Miki
  • Patent number: 7169327
    Abstract: The dielectric-forming composition according to the invention is characterized by consisting of: composite particles for dielectrics in which part or all of the surfaces of inorganic particles with permittivity of 30 or greater are coated with a conductive metal or a compound thereof, or a conductive organic compound or a conductive inorganic material; and (B) a resin component constituted of at least one of a polymerizable compound and a polymer. In addition, another dielectric-forming composition according to the invention is characterized by containing: ultrafine particle-resin composite particles composed of (J) inorganic ultrafine particles with the average particle size of 0.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: January 30, 2007
    Assignee: JSR Corporation
    Inventors: Nobuyuki Ito, Hideaki Masuko, Satomi Hasegawa, Nakaatsu Yoshimura
  • Patent number: 7158383
    Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: January 2, 2007
    Assignee: General Electric Company
    Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
  • Patent number: 7091899
    Abstract: Hook portion is formed on sheet an electric discharge preventing sheet put between battery and electrode. Hook portion which is deformable with a prescribed force comes into contact with holder 6 retaining electric discharge preventing sheet. Therewith, a remote control transmitter is provided, in which sheet hardly comes off during storage and transportation, and battery is securely prevented from exhausting.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: August 15, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yasuhiro Imamura
  • Patent number: 7071419
    Abstract: A flexible circuit having improved tear resistance is provided. A flexible circuit, made of polyimide film, includes at least one extension which needs to be folded. To prevent tearing, an annular piece of metal, like an exposed copper pad for example, is placed at the apex of the bend angle. A second metal is then deposited atop the annular piece of metal, thereby reinforcing the annular piece of metal. The reinforced annular piece of metal helps to prevent the flexible circuit from tearing when shearing forces are applied to the extension. Experimental results have shown that the invention provides as much as a 285% increase in tear resistance when compared to prior art flexible circuits.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: July 4, 2006
    Assignee: Motorola, Inc.
    Inventors: Benjamin J. Holmes, Randall P. Chambers
  • Patent number: 7034231
    Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 25, 2006
    Inventors: Peter Kukanskis, Dennis Fritz, Frank Durso, Steven Castaldi, David Sawoska
  • Patent number: 6994918
    Abstract: A component for use in manufacturing circuit boards, such as printed circuit boards, or flex substrates is adapted for use with pick-and-place equipment to provide a first material overlay disposed over a second material base layer. Such a component may include a first electrically conductive material disposed over a second electrically conductive material, and a soluble tape backing disposed over and attached to the second electrically conductive material. The component may be attached to a circuit board by solder relow, after which the soluble tape backing is removed. Although typical embodiments involve electrically conductive materials, it is noted that an electrically insulating material can also be disposed over and attached to an underlying material which itself is disposed on a circuit board.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: February 7, 2006
    Inventor: Morgan T. Johnson
  • Patent number: 6992864
    Abstract: A thermal component is mounted on the front surface of an isolator sheet within a first specific area. A thermally-conductive material is located on the back surface of the isolator sheet on the back of the first specific area. An electrically-conductive material is located on the front surface of the isolator sheet within a second specific area. A thermally-insulating material is located on the back surface of the isolator sheet on the back of the second specific area. The flexible printed circuit board unit of this type allows heat of the thermal component to efficiently radiate from the thermally-conductive material. An increase in temperature can be suppressed in the thermal component. Heat can reliably stay in the electrically-conductive material when a solder material is applied to the surface of the electrically-conductive material. The solder material is allowed to reliably fuse.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: January 31, 2006
    Assignee: Fujitsu Limited
    Inventors: Hisashi Kaneko, Hiroyuki Iwahara, Yukihiro Komura, Mitsuhiro Izumi, Shinji Fujimoto
  • Patent number: 6921575
    Abstract: Carbon nanotube structures are provided, in which the networks with a desired area and volume, where the carbon nanotubes are electrically or magnetically connected, are formed and the method for easily manufacturing the carbon nanotube structures with less carbon nanotube structures. Carbon nanotube devices are also provided, to which the useful carbon nanotube structures mentioned above are applied. A method for manufacturing carbon nanotube structures includes the steps of applying carbon nanotubes to a low-viscosity dispersion medium to obtain a high-viscosity dispersing liquid which includes carbon nanotubes, and forming a network of the carbon nanotubes having electrical and/or magnetic connections therebetween by removing the low-viscosity dispersion medium from the high-viscosity dispersed liquid.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: July 26, 2005
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Kazunaga Horiuchi, Masaaki Shimizu, Hisae Yoshizawa
  • Patent number: 6918179
    Abstract: A method for preforming of two or more flexible cables in an arrangement consisting of a combination of rigid printed circuit boards and flexible cable sections extending therebetween. Moreover, also provided is an apparatus for the preforming of two or more flexible cable sections of a combination of rigid printed circuit boards and therewith interposed flexible cable sections which are adapted to interconnect the rigid printed circuit boards. The apparatus consists of a tool constituted of an elongated cylindrical member having a tapered leading end which narrows into an ultra-thin flat end section of a blade-like configuration, and which is adapted to be pushed between the flexible cables and so as to preform the flexible cable sections and cause them to yield in a predetermined outwardly bowed permanently relationship between the rigid printed circuit boards at the opposite ends thereof to lengthen the fatigue life of the conductors in the flexible cable sections.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: July 19, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lee Curtis Randall, Thomas Stanley Truman, Daniel James Winarski, George G. Zamora
  • Patent number: 6890629
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: May 10, 2005
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 6863962
    Abstract: A thermally conductive substrate having a structure in which inorganic filler for improving the thermal conductivity and thermosetting resin composition are included. The thermosetting resin composition has a flexibility in the not-hardened state, and becomes rigid after hardening. The thermally conductive substrate has excellent thermal radiation characteristics. The method of manufacturing the thermally conductive substrate includes: piling up (a) the thermally conductive sheets comprising 70 to 95 weight parts of an inorganic filler, and 4.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: March 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Hiroyuki Handa
  • Patent number: 6861591
    Abstract: A printed circuit board having an insulating board and a plurality of wiring patterns formed over the insulating board by screen printing and provided with first conductive pattern bent parts and wiring parts linked to the first conductive pattern bent parts. A pattern width in the first conductive pattern bent parts is greater than that of the patterns of those of the wiring parts positioned close to and on both sides of the first conductive pattern bent parts.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: March 1, 2005
    Inventor: Akihiro Kusaka
  • Patent number: 6842344
    Abstract: A printed circuit board having a dielectric layer is disclosed. At least one signal trace is disposed adjacent a first surface of the dielectric layer in a first signal area. A reference plane is disposed adjacent a second surface of the dielectric layer in a first reference area positioned opposite the first signal area. The reference plane is configured to carry a reference potential for signals on the signal trace. At least one other signal trace is disposed adjacent the second surface of the dielectric layer in a second signal area and coupled to the signal trace in said first signal area. A second reference plane is disposed adjacent the first surface of the first dielectric layer in a second reference area positioned opposite the second signal area. The second reference plane is configured to carry the reference potential for signals on the other signal trace.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: January 11, 2005
    Assignee: Unisys Corporation
    Inventors: Robert Fix, Daniel A. Jochym, Christian E. Shenberger
  • Patent number: 6835442
    Abstract: A flexible printed board contains an unroughened electrodeposited copper foil, a zinc-based metallic layer provided thereon in an amount of 0.25 to 0.40 mg/dm2, and a polyimide resin layer formed through the imidation of a polyamic acid layer provided on the zinc-based metallic layer.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: December 28, 2004
    Assignees: Sony Chemicals Corp., Circuit Foil Japan Co., Ltd.
    Inventors: Noriaki Kudo, Asaei Takabayashi, Akitoshi Suzuki, Shin Fukuda
  • Patent number: 6824857
    Abstract: Disclosed is a circuit element that includes a thermoplastic substrate and a conductive trace at least partially embedded in the thermoplastic substrate. Also disclosed is a method of forming a circuit element. The method includes the steps of providing a thermoplastic substrate having a softening temperature, printing a conductive ink onto the thermoplastic substrate to form a trace, and embedding the trace into the thermoplastic substrate by heating the thermoplastic substrate to a temperature above about the softening temperature about the trace.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: November 30, 2004
    Assignee: Nashua Corporation
    Inventors: Darren Lochun, John J. Ireland
  • Patent number: 6822873
    Abstract: An electronic device such as a semiconductor pressure sensor is provided which has a buffer disposed within a resinous casing. Terminals extend through the casing and connect electrically with an electronic element mounted on the casing through wires. The buffer is made of a material having a coefficient of thermal expansion smaller than that of the body of the casing, thereby decreasing undesirable movement of the terminals leading to fatigue of the wires which arises from a change in temperature of the casing. This minimizes a drop in mechanical strength of the wires caused by thermal cycling to which the casing is subjected.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: November 23, 2004
    Assignee: Denso Corporation
    Inventor: Kazuhiko Koga
  • Patent number: 6815620
    Abstract: A flexible circuit incorporating an electrostatic discharge limiting feature, comprising a dielectric substrate selected from polyimide or liquid crystal polymer film having at least one conductive trace coated on at least one surface of the substrate wherein the discharge limiting feature includes a thin conductive polymer coating selectively applied over a at least a portion of the non-critical region of the circuit, said feature reducing the surface resistivity of the circuit to about 104 ohms to about 108 ohms and having tribocharging of less than about 50 V.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: November 9, 2004
    Assignee: 3M Innovative Properties Company
    Inventors: Robert S. Dodsworth, John B. Scheibner, Ke Zhang, Chee Tat Ee, Juang Meng Mok, Yong Peng Lee
  • Publication number: 20040188133
    Abstract: The present invention provides a tablet computer and a docking station assembly. This docking station comprises a docking assembly for positioning with three degrees of freedom and having a data connector for mechanically supporting and interfacing with the tablet computer. A support member couples the docking assembly to an expansion base. The base includes a number of ports for interfacing with a variety of peripheral devices or power supplies. These varieties of ports mount to a printed circuit board contained within the expansion base. A flexible printed circuit (FPC) combines the signal pathways for the variety of ports, allowing the signal pathways to travel from the printed circuit board and to the data connector. The tablet computing device has a plurality of contact or touch points positioned on the right and left edges of the tablet to facilitate aligning the tablet to the docking assembly in either a landscape or portrait mode.
    Type: Application
    Filed: January 14, 2004
    Publication date: September 30, 2004
    Inventors: John Doherty, Todd W. Steigerwald, Jefferson Blake West, Philip Leveridge, David Altounian, David Cutherell
  • Patent number: 6771348
    Abstract: Disclosed are a displaying substrate and a liquid crystal display device having the same. A pad portion formed on the displaying substrate has a plurality of via holes for exposing a pad metal layer. A width of the via hole is smaller than a diameter of a conductive particle. Where the width of the via hole is larger than the diameter of the conductive particle, a depth of the via hole is smaller than the diameter of the conductive particle. Thus, a driving failure which may occur in the pad portion is prevented while maintaining a deformation ratio of the conductive particle at about 20˜60%, thereby enhancing a connecting force between the pad portion and a circuit substrate.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: August 3, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Sik Oh, Hyeong-Suk Yoo, Ju-Young Yoon, Won-Gu Cho
  • Patent number: 6761963
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: July 13, 2004
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 6759115
    Abstract: A multilayer circuit component and a method for manufacturing the same, in which the difference of the amounts of baking shrinkages between each of the glass-containing layers is small, and the enlargement rate of the diameter of the via hole formed in each of the glass-containing layers is close to those in the other layers, so that it is possible to prevent a short circuit defect due to the mutual short circuit of the conductors in the via hole from occurring, and the warp of the substrate is reduced. The multilayer circuit component is provided with at least two glass-containing layers on a substrate, differentiating the softening temperature of glass compounded in the first glass-containing layer formed on the substrate from the softening temperature of glass compounded in the second glass-containing layer formed on the first glass-containing layer.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: July 6, 2004
    Assignee: Murata Manufacturing Co. Ltd
    Inventor: Michiaki Iha
  • Patent number: 6756138
    Abstract: A device having electrical and mechanical components. The device comprises multiple layers in which: a first layer or set of layers arranged is to function as one or more electrodes or conductors; and a second layer is arranged to function as one or more press contracts or wire contacts or wire bond pads. The second layer has different physical properties than the first layer, wherein the first layer or set of layers is relatively hard or tough and the second layer is relatively soft or malleable. A corresponding method is provided.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: June 29, 2004
    Assignee: Sensonor ASA
    Inventors: Henrik Jakobsen, Svein Moller Nilsen, Soheil Habibi, Timothy Lommasson
  • Patent number: 6734370
    Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: May 11, 2004
    Assignee: Irvine Sensors Corporation
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Patent number: 6707677
    Abstract: A chip-packaging substrate and test method therefor. The chip-packaging substrate includes at least one package area and a connection area enclosed by and connected to the package areas. A test circuit is arranged within the connection area, passing through at least two wire layers and the insulation layer therebetween. The test circuit electrically connects the first electrodes. Failure of the chip-packaging substrate is detected when the test circuit is open between any two electrodes.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: March 16, 2004
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Han-Kun Hsieh, Wei-Feng Lin, Yi-Chang Hsieh
  • Patent number: 6705005
    Abstract: A method of forming a circuit board with electronic assemblies lying in different planes, includes providing a single circuit board with entire electronic assemblies pressed thereon. A channel is then formed in the circuit board of a predetermined depth to divide the circuit board into two separate, but integral portions. The circuit board is then bent at a point between the first and second portions of the circuit board such that the second portion of the circuit board can be bent between 0 and 180 degrees with respect to the first portion of the circuit board.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: March 16, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: Michael Wayne Blazier, Frank Martin Stephan
  • Patent number: 6700789
    Abstract: There has been a problem that a mode (a high-order mode) different from a basic propagation mode occurs at a point of a through conductor and a transmission characteristic deteriorates greatly. The present invention is a high-frequency wiring board wherein L>&lgr;/4 and &pgr;(A+B)≦&lgr; are satisfied in which L is a length of a through conductor, A is a diameter of the through conductor, B is shortest distances between the through conductor and a plurality of ground through conductors, &pgr; is a circle ratio and &lgr; is an effective wavelength of a high-frequency signal transmitted by the through conductor. It is possible to inhibit a high-order mode which occurs at a point of the through conductor.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: March 2, 2004
    Assignee: Kyocera Corporation
    Inventor: Takayuki Shirasaki