With Particular Conductive Material Or Coating Patents (Class 361/751)
  • Patent number: 6690580
    Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: February 10, 2004
    Assignees: AMD, Inc., Motorola, Inc.
    Inventors: Cindy K. Goldberg, John Iacoponi
  • Patent number: 6669273
    Abstract: An automobile instrument panel assembly for the cockpit of an automobile. The assembly includes, in one embodiment, a cross-car beam structure for supporting the assembly. The structure extends across a substantial portion of the cockpit and defines a plurality of generally planar mounting sites and further defines at least one recess. At least one substrate is mounted to the beam and includes at least one area of the substrate populated by electronic components on both sides of the substrate. The area is aligned over the at least one recess, and an instrument panel cover is removably positioned over the substrate and the structure.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: December 30, 2003
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Andrew Z. Glovatsky, Thomas B. Krautheim, Daniel R. Vander Sluis
  • Publication number: 20030234443
    Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
    Type: Application
    Filed: June 9, 2003
    Publication date: December 25, 2003
    Applicant: Staktek Group, L.P.
    Inventors: Julian Partridge, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly
  • Patent number: 6633487
    Abstract: A required interlayer circuit board 1 is constituted so as to provide a punched portion in which only a collapsible cable portion 2 for connecting a plurality of component mounting portions to each other is exposed. An external layer board 6 is superimposed on at least one side of the internal layer circuit board 1 through an adhesive member 4 to which an opening portion 5 is formed at a position corresponding to the cable portion 2, the external layer substrate 6 having an opening portion 7 at a similar position. Thereafter, a wiring pattern for the component mounting portions is formed on the external layer board 6, and a blank and pierce process of the respective component mounting portions except the cable portion is carried out, thereby integrally connecting a plurality of the component mounting portions to each other through the collapsible cable portion.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: October 14, 2003
    Assignee: Nippon Mektron, Ltd.
    Inventors: Akihiko Toyoshima, Kunihiko Azeyanagi
  • Publication number: 20030181038
    Abstract: A method and apparatus for producing printed circuits utilizing direct printing methods to apply a pattern mask to a substrate. The pattern mask may be an etch resist mask for forming conductive pathways by an etching process, or the pattern mask may be a plating mask with conductive pathways being formed by a plating operation. The process of the present invention is applicable to forming both single-sided and double sided printed circuit boards.
    Type: Application
    Filed: March 19, 2002
    Publication date: September 25, 2003
    Inventor: N. Edward Berg
  • Patent number: 6625032
    Abstract: An aqueous dispersion of the invention has conductive microparticles and organic particles dispersed in an aqueous medium and can form a conductive layer of a volume resistivity of for example 10−4 &OHgr;·cm or less by electrodeposition. A circuit board of the invention is equipped in an insulating layer and a conducting layer, which includes conducting through parts that pass through the insulating layer, and is favorably manufactured by the invention s method that includes an electrodeposition using an aqueous dispersion of the invention as a electrodeposition solution and using the conductive foil as one of the electrodes after closing the openings at one end of the through holes formed on the insulating layer by means of a conductive foil.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: September 23, 2003
    Assignees: JSR Corporation, JSR Microtech Inc.
    Inventors: Nobuyuki Ito, Kenichi Koyama
  • Patent number: 6611065
    Abstract: The present invention is a connection material which enables a flexible circuit board to be connected to a bare IC chip without causing a shoulder touch effect. The connection material contains an insulating adhesive and a flaky or fibrous insulating filler dispersed therein is used for connecting a film-like flexible circuit board and a bare IC chip. The aspect ratio of the flaky or fibrous insulating filler is no less than 20.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: August 26, 2003
    Assignee: Sony Chemicals Corporation
    Inventors: Motohide Takeichi, Junji Shinozaki
  • Patent number: 6603663
    Abstract: The invention relates to an electronic unit having a mounting board (4) and electronic components (1-3) mounted on it, with the mounting board (4) having metal webs (41) which are embedded in an electrically insulating material (40), the metal webs (41) having a first side (411), which is in the form of a contact surface for making contact with the electronic components (1-3) and having a second side (412) facing away from this. According to the invention, cutout(s) are arranged in the electrically insulating material (40), via which the second side (412) of each metal web (41) is accessible for a voltage or current measurement apparatus.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: August 5, 2003
    Assignee: Patent-Treuhand-Gesellscahft fuer Elektrische Gluehlampen mbH
    Inventor: Matthias Burkhardt
  • Patent number: 6594152
    Abstract: A first printed circuit board has a contact area, and a second printed circuit board has a contact area. An electrically conductive band is to couple the contact area of the first printed circuit board to the contact area of the second printed circuit board. The conductive band may be selected from the group consisting essentially of a band formed from solder, a band coupled by a weld, a band coupled by a wire bond, a band comprising conductive adhesive, a band comprising conductive film, a band comprising conductive tape, and a band comprising conductive rope. The conductive band may couple the first printed circuit board and the second printed circuit board in a substantially coplanar position.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventor: David Dent
  • Publication number: 20030123232
    Abstract: A handheld type electronic device of this invention includes two housings respectively provided with electronic system components, a rotary device, and an electrical connector electrically connecting the electronic system components in the two housings. The invention is characterized in that the rotary device has a pivoting portion disposed on one side of one of the housings to rotatably connect with the other one of the housings, and a receiving portion. The electrical connector is disposed in the receiving portion and is confined in the housing provided with the rotary device such that rotation of the pivoting portion can bring the two housings to open or close while the electrical connector remains immovable.
    Type: Application
    Filed: October 2, 2002
    Publication date: July 3, 2003
    Inventors: San-Shan Huang, Hung-Chuen Yin
  • Publication number: 20030047353
    Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Patent number: 6504729
    Abstract: An electrically shielded housing for an electrical device and method therefor having an insert member disposed in a cavity of a non-conductive housing body member. The insert member includes a conductive inner surface portion disposed adjacent an outer surface portion of the body member cavity. A non-conductive outer surface portion of the insert member forms a housing cavity for receiving an electrical device. The conductive inner surface portion of the insert member at least partially electrically shields the electrical device, and the non-conductive outer surface portion of the insert member insulates the electrical device from the conductive inner surface portion thereof.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: January 7, 2003
    Assignee: Illinois Tool Works Inc.
    Inventors: Peter Michael Frederick Collins, Terry Dean Thomason, Ralph A. Hausler
  • Patent number: 6499215
    Abstract: A method for processing circuit boards containing area array surface treated bonding sites, such as noble metal terminal pads of a Land Grid Array (LGA) assembly. The circuit board includes a plurality of apertures patterned about the bonding site to form a footprint. A protective cover shaped to conform to the footprint includes posts registered to removably fit into the apertures. The protective cover remains overlaid on the circuit board during fabrication processes such as solder screen printing, rework, and washing, and then removed. Thus, contamination from the fabrication processes is avoided, as well as eliminating possible sources of contamination from use of adhesive tape for protection.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: December 31, 2002
    Assignee: International Business Machines Corporation
    Inventors: Mark Kenneth Hoffmeyer, Daniel Scott Johnson
  • Patent number: 6483713
    Abstract: An easier and cheaper way to obtain multilayer circuit board is by using a flexible circuit board and folding it in an organized pattern. Flexible circuit has the unique property of being a three-dimensional circuit that can be shaped in multiplanar configurations, rigidized in specific areas, and molded to backer boards for specific applications. The folded circuit is fabricated from a series of foldable circuit board strips and rigid circuit board strips which are interconnected, folded, and bonded into a composite structure. The foldable strips may have prefolds arranged so that a group of upper foldable strips and lower foldable strips are folded in opposite directions. A plurality of intermediate portions are stacked on each other by the folding the foldable strips in opposite directions. The folded circuit, can be bonded after a first fold, or folded further to achieve a greater reduction in area and subsequently be bonded as a composite multilayer structure.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 19, 2002
    Assignees: St. Jude Children's Research Hospital, The University of Tennessee Research Corp.
    Inventors: Sanjiv Singh Samant, Jinesh Jitendra Jain, Joseph Laughter
  • Patent number: 6477060
    Abstract: A printed circuit board utilizes asymmetric striplines to accommodate a large number of transmission lines on a six-layer board. The asymmetric striplines are formed from two signal layers that are sandwiched between two reference planes such that the traces in each signal layer form asymmetric striplines with the two reference planes. Two additional signal layers are arranged on the outside of the reference planes so as to form microstrips with the reference planes.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: November 5, 2002
    Assignee: Intel Corporation
    Inventors: Erik W. Peter, Jeffrey M. Shuey, Ronald Martin
  • Patent number: 6473310
    Abstract: The invention includes a multichip integrated circuit package having at least two chips electrically isolated from one another. Within the multichip integrated circuit package is a slug that is directly coupled to at least two chips, without any intervening insulating layers. The slug is physically separated at an appropriate place between the two chips, so that electrical interference between the two chips is effectively eliminated. Making the integrated circuit package begins with directly attaching the two chips to a heat dissipating slug. The heat dissipating slug can have a pre-cut groove running between the chips. Once the chips are attached to the slug, the slug is molded into the multichip integrated circuit package. Then, the slug is physically separated into two pieces from the underside, the separation running along the pre-cut groove. Usually the slug would be separated by being cut by a saw.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: October 29, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Paolo Casati, Carlo Cognetti
  • Publication number: 20020131248
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Application
    Filed: November 8, 2001
    Publication date: September 19, 2002
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 6433284
    Abstract: A partially cut multi-planar flexible printed circuit comprises a substrate, a set of signal conducting elements for differential mode and common mode, a power supply and/or ground. The multi-planar flexible printed circuit is formed by partially grouped cutting a flexible printed circuit at a proper position so that the cross-sectional area of the multi-planar flexible printed circuit at the cut portion can fit in with a small round or square splice hole in addition to a flat rectangular slit for connecting, for example, a liquid crystal display with a notebook computer. Moreover, intervals between edges of a substrate and a plurality of transmission lines are preferably greater than three times of thickness of the substrate.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: August 13, 2002
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Gwun-Jin Lin, Chi-Kuang Hwang, Ching-Cheng Tien
  • Patent number: 6395993
    Abstract: The present invention aims to manufacture a reliable multilayer flexible wiring board at high yield. Flexible wiring board 10 used for multilayer flexible wiring board 40 of the present invention has metal coating 14 on the surface of metal wiring film 19, and metal coating 14 is exposed within the contact region. A wall member rising above the surface of metal coating 14 is provided around the exposed metal coating 14. The wall member is formed of wall face 23 of opening 17 in resin film 15 at the top of metal wiring film 19, for example. When bump 34 having low-melting metal coating 36 is contacted with metal coating 14 in said contact region and heated above the melting point of the solder metal under pressure, low-melting metal coating 36 melts. The molten low-melting metal is stopped by wall face 23 from overflowing outside the contact region so that any bridge cannot be formed by the solder metal between metal wiring film 19.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: May 28, 2002
    Assignee: Sony Chemicals Corp.
    Inventors: Masayuki Nakamura, Mitsuhiro Fukuda
  • Patent number: 6395992
    Abstract: A three-dimensional wiring board comprises a metal base having a roughed surface, a heat-bonding type of polyimide film without using adhesive, bonded to the roughed surface and serving as an electric insulating layer, and a copper foil for a conductive layer, bonded to the other surface of the polyimide film. A method for manufacturing the wiring board comprises a roughing treatment process for plating or oxidizing the surface of a metal base, thereby forming a roughed surface, a contact bonding process for attaching a polyimide film to the roughed surface and a copper foil by thermocompression bonding, thereby forming a laminate material, a patterning process for etching the copper foil into a desired conductive pattern, and a bending process for bending the laminate material into a desired three-dimensional shape by press working.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: May 28, 2002
    Assignees: NHK Spring Co., Ltd., Ube Industries, Ltd.
    Inventors: Osamu Nakayama, Toshinori Hosoma, Takuhiro Ishii
  • Patent number: 6396706
    Abstract: Separate heating elements are embedded in a printed circuit board near integrated circuit (IC) packages or other parts mounted on the circuit board. Each heating element supplies heat to the part residing near it in response to an input voltage pulse. The heating elements are used to selectively melt solder or adhesives attaching the parts to the circuit board so that they can be easily removed or to temporarily melt solder or cure adhesive when the parts are mounted on the circuit board. The heating elements are also used to supply heat to IC packages for regulating their operating temperatures.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: May 28, 2002
    Assignee: Credence Systems Corporation
    Inventor: Paul D. Wohlfarth
  • Patent number: 6388201
    Abstract: To provide a wired circuit board capable of surely preventing occurrence of a short circuit between a metal terminal layer and a metal supporting layer with a simple construction, to provide improvement in connection reliability and in voltage proof property, a wired circuit board comprises a base layer formed on a supporting board, a conductive layer formed on the base layer, a surface of the conductive layer being exposed by opening the supporting board and the base layer, and a metal plated layer formed on the conductive layer exposed in the openings of the supporting board and the base layer, wherein a specified space is defined between a periphery of the metal plated layer and a periphery of the opening of the supporting board.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: May 14, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Takeshi Yamato, Kenichiro Ito
  • Patent number: 6380493
    Abstract: To provide a circuit board, having a circuit pattern of adequate high-frequency characteristics, for transmitting high-frequency electric signals at high speed, a circuit board, including a base layer formed of insulating material and a conductive layer formed on the base layer in the form of a specified circuit pattern, is so constructed that an air layer is made to lie between lines of wire of the circuit pattern or is so constructed that the lines of wire are covered with the cover layer but land portions of the base layer extending between the lines of wire are not covered with the cover layer. This construction of the invention enables dielectric constant between the lines of wire to be reduced and, as a result of this, the capacitance between the lines of wire can be reduced to provide improved high-frequency characteristics of the circuit pattern.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: April 30, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Shigenori Morita, Yasuhito Ohwaki, Tadao Ohkawa, Toshihiko Omote
  • Patent number: 6376779
    Abstract: A printed circuit board having a plurality of spaced apart scrap border support tabs along the perimeter. The board surfaces including the edges are coated with a conductive shielding material, except that each tab presents an uncoated, unshielded surface at the point of severance created by detachment of a scrap border subsequent to the coating application. The printed circuit board includes a plurality of spaced apart elongated apertures adjacent the perimeter, with each aperture being inwardly coincident to a respective one of each support tabs, each aperture defining an inner surface adjacent to the corresponding support tab with a portion of the inner surface being substantially parallel to adjacent perimeter portions of the circuit board, the inner surface of each aperture also being coated with the conductive shielding material with the latter being attached to the conductive shielding material of the board surface.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: April 23, 2002
    Assignee: Nortel Networks Limited
    Inventors: Simon E. Shearman, Geoffrey G. Skanes, Kyle G. Edginton, Denis Kasprowicz
  • Patent number: 6362997
    Abstract: A memory system is disclosed. The memory system comprises a circuit board and at least two memory devices mounted on the circuit board. Each of the at least two memory devices includes a plurality of pins for receiving and providing signals. At least a first portion of the pins of one of the at least two memory devices are coupled to at least a second portion of the pins of the other at least two memory devices such that a pair of the first portion coupled to a pin of the second portion forms a coupled load. The coupled load then appears as one load. Accordingly, in a system in accordance with the present invention, at least two memory devices are provided on a circuit board. Each of the at least two memory devices includes a plurality of pins.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: March 26, 2002
    Assignee: nVIDIA
    Inventors: Larry Fiedler, Simon Thomas, Barry Wagner
  • Patent number: 6353188
    Abstract: A circuit assembly having a plurality of tracks formed from a conductive material secured to a flexible substrate by an adhesive. The adhesive is selected to withstand high temperatures and strains caused by folding the flexible substrate.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: March 5, 2002
    Assignee: Lear Corporation
    Inventor: Salvador Gomez Fernandez
  • Patent number: 6350957
    Abstract: A circuit board which is formed with bump patterns subject to a narrow variation in height on the surface of the circuit board, and which permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 26, 2002
    Assignees: Meiko Electronics, Co., Ltd., Machine Active Contact Co., Ltd.
    Inventors: Noboru Shingai, Tatsuo Wada, Katsuro Aoshima
  • Patent number: 6344792
    Abstract: A method of manufacturing and testing an electronic circuit, the method comprising forming a plurality of conductive traces on a substrate and providing a gap in one of the conductive traces; attaching a circuit component to the substrate and coupling the circuit component to at least one of the conductive traces; supporting a battery on the substrate, and coupling the battery to at least one of the conductive traces, wherein a completed circuit would be defined, including the traces, circuit component, and battery, but for the gap; verifying electrical connections by performing an in circuit test, after the circuit component is attached and the battery is supported; and employing a jumper to electrically close the gap, and complete the circuit, after verifying electrical connections.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: February 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Rickie C. Lake, Curtis M. Medlen
  • Publication number: 20020007963
    Abstract: An improved structure of printed circuit board (PCB) under pushbutton comprises a base layer and an insulation membrane, wherein a plurality of conductive portions and corresponding contact portions are printed on the base layer and the insulation membrane respectively. A plurality of insulation portions is printed on each contact portion along its circumference; and, no glue will be applied on a corridor between every pair of the conductive potions in the base layer and the contact portions in the insulation membrane when c ombining the insulation membrane to the base layer by gluing or direct printing. By this arrangement, an air channel can be reserved for being applicable to various button groups or waterproof membrane PCBs.
    Type: Application
    Filed: September 24, 1999
    Publication date: January 24, 2002
    Inventor: CHIN-WEN CHOU
  • Patent number: 6335077
    Abstract: As an electrically conductive paste for via-holes, an organic vehicle and an electrically conductive metal powder coated with a resin which is insoluble in the organic vehicle are prepared. Filling via-holes with the electrically conductive paste for via-holes produces a monolithic ceramic. Filling characteristics of the electrically conductive paste into via-holes are improved, and cracks and elevations of the conductive metal and cracks of the ceramic barely form during the baking step. Further, the resulting monolithic ceramic substrate can maintain excellent soldering wettability and plating characteristics.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: January 1, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroji Tani, Kazuhito Ohshita
  • Patent number: 6331678
    Abstract: A device with a multi-layered micro-component electrical connector. The multi-layer micro-component electrical connector includes a dielectric layer, a micro-mesh of a first electrical conductor secured to the dielectric layer, and a second electrical conductor secured to and contacting the micro-mesh to provide electrical communication. The dielectric layer has a dielectric layer thermal expansion coefficient and the first electrical conductor has a thermal expansion coefficient different from the dielectric layer thermal expansion coefficient. Due to the presence of the micro-mesh the device is operable at temperatures above 250° C. without delamination or blistering of the first electrical conductor from the dielectric layer.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: December 18, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Tak Kui Wang, Phillip W. Barth, Michel G. Goedert
  • Patent number: 6326554
    Abstract: A surface mountable flexible interconnect and component carrier (10) for connecting to a main circuit board consists of a flex circuit (12) with solder pads (14) on one side for receiving an electronic component (15). There is an array of solderable pads (16) on the other side of the flex circuit, and each of the pads in the array has a solder bump (18) fused to it. The array of solderable solder pads (16) is electrically connected to the solder pads (14) for receiving the electronic component (15) by means of electrically conductive vias in the flexible film. A rigid carrier (20) is used to hold the flex circuit in position prior to placement on the circuit board. An opening (26) in the rigid carrier is strategically located so that the electronic component can be soldered to the solder pads.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: December 4, 2001
    Assignee: Motorola, Inc.
    Inventors: Joseph G. Gillette, Scott F. Musil
  • Patent number: 6326559
    Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 &mgr;m in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: December 4, 2001
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Hirokazu Yoshioka, Norio Yoshida, Kenichiro Tanaka
  • Patent number: 6323096
    Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: November 27, 2001
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Kevin Matthew Durocher, Herbert Stanley Cole
  • Patent number: 6320137
    Abstract: A printed circuit including a dielectric substrate and a conductive trace attached to a surface of the dielectric substrate. The trace includes a base layer and a coverplate layer on a portion of the base layer. The coverplate layer defines a coverplate edge on the base layer. A protective layer is formed on a portion of the coverplate layer. The protective layer extends beyond the coverplate edge onto at least a portion of the base layer of the trace. A key aspect of the present invention is that the protective layer overlaps the coverplate edge of each trace to reduce the potential for corrosion of the base layer at the coverplate edge.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: November 20, 2001
    Assignee: 3M Innovative Properties Company
    Inventors: Lora C. Bonser, Terry F. Hayden, Robert J. Schubert
  • Patent number: 6320751
    Abstract: A frame sheet comprises a core sheet, and oversheets. A recess is formed in the sheet frame. The oversheet is left in the recess in the sheet frame, and an IC carrier is mounted in the recess. The IC carrier is held, adhered to the oversheet left in the recess.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: November 20, 2001
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Mitsunori Takeda, Eiichi Igarashi, Hideyo Yoshida
  • Patent number: 6320136
    Abstract: A printed circuit board, on which an electronic component with leads is mounted, includes a first conductive layer; an insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a buffer region. The second conductive layer is provided with pads to be connected to the leads of the electronic component. The buffer region has a thermal expansion coefficient lower than the first conductive layer and is arranged between the first conductive layer and the insulating layer to ease thermal expansion of the first conductive layer.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: November 20, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akira Sakamoto
  • Patent number: 6316734
    Abstract: Circuit and circuit carries include a dielectric substrate having a conductive layer mounted thereon. The conductive layer is patterned to define a plurality of spaced apart conductive elements. A static charge dissipative layer is in contact with and extending between at least two of the conductive elements. The static charge dissipative layer has a surface resistivity of between about 1×105 and about 1×1010 ohms/□. The static charge dissipative layer is made of a material selected from the group consisting of diamond-like carbon, silicon nitride, boron nitride, boron trifluoride, silicon carbide and silicon dioxide. Circuits and circuit carriers according to the present invention allow static charges to be controllably and reliably dissipated from a surface of the circuit or circuit carrier such that the potential for damage from static discharge to electrical components connected to the circuit is reduced.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: November 13, 2001
    Assignee: 3M Innovative Properties Company
    Inventor: Rui Yang
  • Patent number: 6310298
    Abstract: A substrate for a plurality of electronic assemblies includes a strip of printed circuit board (PCB) material including a surface and a plurality of segments. Each segment is adapted to receive at least one electronic component and is arranged to be singulated into a plurality of individual electronic assemblies. Each segment has a perimeter portion located generally about the periphery of the segment, with the surface being covered with a solder mask, except for the perimeter portion.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: October 30, 2001
    Assignee: Intel Corporation
    Inventors: Joseph C. Barrett, Mark P. Jamieson
  • Patent number: 6297964
    Abstract: A semiconductor device comprising an insulating film having a device hole, a plurality of bumps formed on the insulating film, a plurality of first leads having end faces thereof exposed on an outline edge of the insulating film, each of the first leads being electroplated and connected with one of the bumps, a plurality of second leads having end portions thereof protruding into the device hole, each of the second leads being electroplated and connected with one of the bumps, and a semiconductor chip connected with the end portions of the second leads in the device hole. The insulating film is outlined to have a cut in a region including each of the exposed end faces of the first leads.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: October 2, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6295206
    Abstract: A memory card is disclosed which has a card body (2) having a concavity (9) formed at the forward end thereof in the inserting direction and in which terminals (5) are disposed and projections (10) are formed between the terminals (5) to prevent the terminals (5) from being touched or accessed from outside. A receptacle for the memory card is also disclosed. The memory card has a simple structure designed to positively protect the terminals and easily let out dust or the like from inside, thereby permitting to assure a positive connection with the receptacle.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 25, 2001
    Assignee: Sony Corporation
    Inventors: Yoshio Kondo, Toshiharu Kobayashi, Takumi Okaue, Akira Sassa
  • Patent number: 6217990
    Abstract: A multilayer circuit board for holding a flip chip thereon includes laminated first to fourth substrates. A first pattern integrated portion having a locally high pattern density is provided on the second substrate. Further, on the fourth substrate which is disposed on an opposite side of the second substrate with respect to a center in a laminated direction of the circuit board, a second pattern integrated portion having a locally high pattern density is disposed to correspond to the first pattern integrated portion. Accordingly, a local warp can be prevented from being produced on the mounting surface of the multilayer circuit board when the circuit board is manufactured by baking.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: April 17, 2001
    Assignees: Denso Corporation, Kyocera Corporation
    Inventors: Yasutomi Asai, Takashi Nagasaka, Shinji Ota, Takashi Yamazaki, Shinya Terao, Syoichi Nakagawa
  • Patent number: 6157541
    Abstract: Two semiconductor memory chips are placed onto a flexible wiring and are shaped by simple folding of the flexible wiring about a central elastic line, into a space-efficient stack arrangement whose outer contacts are formed only at one marginal side. To form memory cards, a plurality of such stack arrangements can be placed onto a simply constructed printed board.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: December 5, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hans-Juergen Hacke
  • Patent number: 6157548
    Abstract: An electrically shielded housing for an electrical device and method therefor having an insert member disposed in a cavity of a non-conductive housing body member. The insert member includes a conductive inner surface portion disposed adjacent an outer surface portion of the body member cavity. A non-conductive outer surface portion of the insert member forms a housing cavity for receiving an electrical device. The conductive inner surface portion of the insert member at least partially electrically shields the electrical device, and the non-conductive outer surface portion of the insert member insulates the electrical device from the conductive inner surface portion thereof.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: December 5, 2000
    Assignee: Illinois Tool Works Inc.
    Inventors: Peter Michael Frederick Collins, Terry Dean Thomason, Ralph A. Hausler
  • Patent number: 6144558
    Abstract: A present invention is to provide a thin parts installation structure and their manufacturing method. There is provided a circuit on a wiring substrate, an adhesive is painted to a selected part installation position on the wiring substrate, a conductive adhesive is painted in a position where the terminal area of electronic parts contact the wiring pattern circuits. The electronic part is put in the selected position of wiring the substrate such that the terminals of the electronic parts contact the conductive adhesive prior to curing the adhesives, and followed by both the non-conductive adhesive and conductive adhesive are stiffened.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: November 7, 2000
    Assignee: Minebea Co., Ltd.
    Inventors: Naohiro Shiota, Rikuro Obara
  • Patent number: 6125042
    Abstract: The present invention is directed to an integrated circuit package having improved EMI characteristics. In accordance with one aspect of the invention, a ball grid array integrated circuit package is provided for attachment to a circuit board. The circuit package includes a substrate having a semiconductor die defining an electronic circuit formed thereon. A matrix of spherically-shaped package leads is disposed adjacent the substrate and opposite the semiconductor die. Conductive elements, such as bond wires, electrically connect circuit points on the semiconductor die to the package leads. Further, at least one conductive element electrically interconnects each of the leads that define a perimeter of the matrix of package leads, for electrical connection to ground. In the preferred embodiment, adjacent leads of the perimeter matrix are separated by a spacing that is no greater than 1/20 of the wavelength of the highest frequency electrical signal carried on any of the signal leads.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: September 26, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Fred W. Verdi, Richard Haynes
  • Patent number: 6118665
    Abstract: A flexible printed circuit having wiring patterns printed on a flexible resin film, comprising a narrow flexible area having first wiring patterns and constituting a flexible wiring part and a broad connection area adapted to be adhered to a main board and having second wiring patterns connected to the first wiring patterns and adapted to be electrically connected to wiring patterns on the main board. The second wiring patterns serve to electrically connect the first wiring patterns of the flexible wiring part to the wiring patterns on the main board. Also included is a conductive adhesion surface formed on the broad connection area along a side of the main board, having a width larger than a width of the first wiring patterns, and extending from an inside of a region to an outside thereof. The region is defined in the broad connection area by extending a boundary of the flexible area into the broad connection area.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: September 12, 2000
    Assignee: Fujitsu Limited
    Inventors: Katsuhiko Kishida, Katsunori Tanaka, Toshiya Onodera, Hirofumi Miyamoto
  • Patent number: 6108211
    Abstract: What is disclosed is an electrical contact system (10) for four pressure sensors (19) to be electrically contacted from different contact sides (13, 14). For this purpose a component side (22) of a flexible circuit board (11) has spaced-apart contact areas (24, 25), which come into contact with opposite contact areas (48, 49) provided on the pressure sensors (19) by folding the circuit board (11) over in a bendable are (52) between two contact areas (24, 25) to provide for a quick and reliable contacting process.
    Type: Grant
    Filed: May 5, 1999
    Date of Patent: August 22, 2000
    Inventor: Carmen Diessner
  • Patent number: 6108214
    Abstract: Plural units each composed of a metallic frame and a dielectric substrate mounted on the frame are stacked on one another, thereby forming a unitary case. A superconducting circuit such as a resonator is formed on an upper surface of the substrate, and a ground plane, made of a metallic material, preferably, a superconducting material, is formed on a lower surface of the substrate. The ground plane is exposed to a center opening of the frame, so that the ground plane of one substrate faces the superconducting circuit of another substrate which is stacked underneath the one substrate with a space therebetween. Thus, a plurality of the superconducting circuits are mounted in a compact unitary case.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: August 22, 2000
    Assignee: Advanced Mobile Telecommunication Technology, Inc.
    Inventor: Masashi Fuse
  • Patent number: 6104280
    Abstract: A method of manufacturing and testing an electronic circuit, the method comprising forming a plurality of conductive traces on a substrate and providing a gap in one of the conductive traces; attaching a circuit component to the substrate and coupling the circuit component to at least one of the conductive traces; supporting a battery on the substrate, and coupling the battery to at least one of the conductive traces, wherein a completed circuit would be defined, including the traces, circuit component, and battery, but for the gap; verifying electrical connections by performing an in circuit test, after the circuit component is attached and the battery is supported; and employing a jumper to electrically close the gap, and complete the circuit, after verifying electrical connections.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: August 15, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Rickie C. Lake, Curtis M. Medlen