With Specific Dielectric Material Or Layer Patents (Class 361/762)
  • Patent number: 11791270
    Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kamal K Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, Ravi K. Bonam, Hiroyuki Mori, Yang Liu, Paul S. Andry, Isabel De Sousa
  • Patent number: 11361891
    Abstract: One object is to provide a magnetic coupling coil component having an improved coupling coefficient. A coil component according to one embodiment of the present invention includes: an insulator body; and first and second coil conductors embedded in the insulator body and wound around a coil axis. A first coil surface of the first coil conductor is opposed to a second coil surface of the second coil conductor. The insulator body includes: an intermediate portion disposed between the first coil surface and the second coil surface; a core portion disposed inside the first and second coil conductors; and an outer peripheral portion disposed outside the first and second coil conductors. A magnetic permeability of the intermediate portion in a direction perpendicular to the coil axis is smaller than those of the core portion and the outer peripheral portion in a direction parallel to the coil axis.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 14, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Natsuko Sato, Satoshi Tokunaga, Satoshi Kobayashi
  • Patent number: 11336251
    Abstract: Disclosed are devices and methods for fabricating devices. A device can include a passive portion having at least one metal insulator metal (MIM) capacitor and at least one 2-dimensional (2D) inductor. The device further includes a substrate and the passive portion is formed on the substrate. A magnetic core is embedded in the substrate. A 3-dimensional (3D) inductor is also included having windings formed at least in part in the substrate and at least a portion of the windings being formed around the magnetic core.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: May 17, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Jonghae Kim, Ranadeep Dutta
  • Patent number: 11328980
    Abstract: A power device embedded PCB includes a printed circuit board having a first major surface separated by a thickness and opposite a second major surface and an embedded power device. The embedded power device may include a power semiconductor device, an electrically and thermally conductive substrate bonded to the power semiconductor device along a first surface of the electrically and thermally conductive substrate and bonded to an electrical insulation layer on a second surface of the electrically and thermally conductive substrate opposite the first surface and a thermally conductive substrate bonded to the electrical insulation layer on a surface opposite the bonded electrically and thermally conductive substrate. The power semiconductor device, the electrically and thermally conductive substrate, the electrical insulation layer, and the thermally conductive substrate are disposed within the printed circuit board.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 10, 2022
    Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Feng Zhou, Shohei Nagai
  • Patent number: 11239180
    Abstract: A structure and a formation method of a package structure are provided. The method includes disposing a first semiconductor die over a carrier substrate and forming a first protective layer to surround the first semiconductor die. The method also includes forming a dielectric layer over the first protective layer and the first semiconductor die. The method further includes patterning the dielectric layer to form an opening partially exposing the first semiconductor die and the first protective layer. In addition, the method includes bonding a second semiconductor die to the first semiconductor die after the opening is formed. The method includes forming a second protective layer to surround the second semiconductor die.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • Patent number: 10896871
    Abstract: A circuit board includes an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Masaharu Furuyama, Daisuke Mizutani
  • Patent number: 10763217
    Abstract: A semiconductor package and an antenna module including the same includes a frame having first and second through-holes, a semiconductor chip disposed in the first through-hole of the frame and having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a wiring chip disposed in the second through-hole of the frame and including a body portion and a plurality of through vias penetrating the body portion, an encapsulant encapsulating at least portions of the semiconductor chip and the wiring chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and the through via of the wiring chip.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Koon Lee, Jin Su Kim
  • Patent number: 10651117
    Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Jianyong Xie, Sujit Sharan
  • Patent number: 10607980
    Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Changhan Hobie Yun, Daeik Daniel Kim, Chengjie Zuo, David Francis Berdy, Mario Francisco Velez, Jonghae Kim
  • Patent number: 10546680
    Abstract: A coil electronic component includes coil parts formed on both surfaces of a support part and a magnetic body enclosing the support part and the coil parts. The magnetic body includes a dipping coating part formed around the coil part, a core part formed inside the coil part, an outer peripheral part formed outside the coil part, and first and second cover parts formed above and below the coil part. The dipping coating part contains metal powder having shape anisotropy.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Soo Park, Ji Hyun Eom, Jae Yeol Choi
  • Patent number: 10475756
    Abstract: A composite antenna substrate and semiconductor package module includes: a fan-out semiconductor package including a semiconductor chip, an encapsulant encapsulating at least portions of the semiconductor chip, and a connection member including a redistribution layer electrically connected to connection pads; and an antenna substrate including an antenna member including antenna patterns, ground patterns, and feed lines, and a wiring member disposed below the antenna member and including wiring layers including feeding patterns electrically connected to the feed lines.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Ho Baek, Doo Il Kim, Young Sik Hur, Jung Hyun Cho, Won Wook So
  • Patent number: 10350324
    Abstract: A microfluidic cartridge and a microfluidic delivery device having a housing and a microfluidic cartridge releasably connectable with the housing are provided. The microfluidic cartridge includes a reservoir for containing a fluid composition, a first face, and a second face joined with the first face. The electrical circuit has a first end portion and a second end portion. The first end portion of the electrical circuit is disposed on the first face and the second end portion of the electrical circuit is disposed on the second face. The first end portion includes electrical contacts and one or more circuit minor openings that are configured to mate with minor guideposts on the housing of a microfluidic delivery device. The microfluidic cartridge may include one or more major openings that are configured to mate with major guideposts on the housing. The microfluidic cartridge includes a microfluidic die disposed on the second face.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 16, 2019
    Assignee: The Procter & Gamble Company
    Inventors: Dana Paul Gruenbacher, William Michael Cannon, James Daniel Anderson, Jr.
  • Patent number: 10237978
    Abstract: A fabricating method according to the present disclosure is a component built-in multilayer substrate fabricating method for incorporating a component (12) in a resin multilayer substrate (11) formed by laminating and pressing thermoplastic resin sheets (111a to 111d) so as to crimp them to each other. With the fabricating method according to the present disclosure, a metal pattern (13) is provided on a component mounting surface of the thermoplastic resin sheet (111a). Further, the component (12) is inserted in the area sandwiched by the metal pattern (13). Out of widths relating to the area sandwiched by the metal pattern (13), the width in the component mounting surface side is assumed to be a width W2, and the width in the component-insertion side is assumed to be a width W3, the width W2 being equal to or larger than a width W1 of the component but less than the width W3.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: March 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kuniaki Yosui
  • Patent number: 10205120
    Abstract: An encapsulating method, a display panel and a display apparatus, the encapsulating method including: forming a frit layer in an encapsulating area of a first substrate; forming a glass network modifier oxide layer on the surface of the frit layer; a first-sintering for the frit layer and the glass network modifier oxide layer; and aligning and attaching the first substrate and a second substrate, and forming an encapsulating structure through irradiating the encapsulating area by a laser. The encapsulating method can improve the liquidity of the surface of the frit layer and make the surface of the frit planarization after sintering at high temperature, so that the production of the holes of the surface of the frit layer can be reduced in the process of being encapsulated by a laser, and then the effect of encapsulating is improved.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhiliang Jiang, Fengli Ji, Renrong Gai, Minghua Xuan
  • Patent number: 9799608
    Abstract: A semiconductor device includes a monocrystalline substrate of a material which does not have a liquid phase at atmospheric pressure, and an identification mark disposed on or in the substrate comprising an amorphous region of the material or a region of the material deviated from stoichiometry.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 24, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuma Suzuki, Hirofumi Fujisawa, Tsutomu Shirakawa, Kenya Sano
  • Patent number: 9730322
    Abstract: A component-embedded substrate includes a cavity including through-holes penetrating through resin sheets in a stacked body of resin sheets having flexibility. An electronic chip component including external electrodes is disposed in the cavity. The resin sheet on which the electronic chip component is located is provided with through-holes into which conductive pastes are filled. The resin sheet includes cut-away portions communicating with a through-hole and located at a distance from each other across the through-hole. When this stacked body is hot-pressed, the conductive pastes overflow from the through-holes. However, the overflowing conductive pastes enter the cut-away portions.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 8, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuki Wakabayashi, Shigeru Tago, Daisuke Tsuruga, Masaki Kawata
  • Patent number: 9530744
    Abstract: A semiconductor device includes a wiring substrate including a first electrode in which a cross-sectional shape is an inverted trapezoidal shape, a semiconductor chip including a second electrode in which a cross-sectional shape is an inverted trapezoidal shape, a metal bonding material bonding a tip end of the first electrode and a tip end of the second electrode which face each other, and an underfill resin filled between the wiring substrate and the semiconductor chip, the underfill resin covering a side face of each of the first electrode and the second electrode and a side face of the metal bonding material.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 27, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kiyoshi Oi, Satoshi Otake
  • Patent number: 9468090
    Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 11, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Goutham Sabavat, Javid Mohamed, Subramanian Ramanathan, Stephen A. Scearce
  • Patent number: 9406428
    Abstract: An inductor includes a multilayer body, which is composed of a non-magnetic material and a magnetic material, and a coil. An inner circumferential surface of the coil is covered by non-magnetic material layers. The sum of the width of a coil conductor forming part of the coil and the width of a non-magnetic material layer covering an inner circumferential side of the coil conductor that are located in a center portion of the coil in a z-axis direction is larger than the sum of the width of a coil conductor forming part of the coil and the width of a non-magnetic material layer covering the coil conductor that are located in an end portion of the coil on the positive side in the z-axis direction.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: August 2, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yasushi Takeda
  • Patent number: 9270003
    Abstract: The present invention is directed to a stripline assembly that includes a first pre-fired ceramic substrate including a ground plane disposed on a first surface of the first pre-fired ceramic substrate. A second pre-fired ceramic substrate includes a ground plane disposed on a first surface thereof and a circuit disposed on a second surface of the second pre-fired ceramic substrate opposite the first surface. The circuit is disposed between the first pre-fired ceramic substrate and the second pre-fired ceramic substrate. A conductive bonding layer is disposed around the periphery of the circuit and between the first pre-fired ceramic substrate and the second pre-fired ceramic substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 23, 2016
    Assignee: Anaren, Inc.
    Inventors: Benton O'Neil, Adam Cook, Benjamin Shawley
  • Patent number: 9265149
    Abstract: A printed wiring board comprises ground layers stacked via insulator(s); a first through hole; second through holes ; and signal wirings each extending from the first through hole through the clearance between predetermined ones of the ground layers, disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring layer in which the signal wiring is disposed has an outline that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that outline of second clearance does not contact with the second through holes.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: February 16, 2016
    Assignee: NEC CORPORATION
    Inventor: Kazuhiro Kashiwakura
  • Patent number: 9086836
    Abstract: A housing for a handheld computing device can include a metallic outer shell having a substantially flat base and a sidewall connected to a periphery of the base, the sidewall having a card slot, the outer shell having an inner surface and an outer surface, and a corrugated stiffener connected to the inner surface of the base and positioned adjacent to the card slot, the stiffener including a series of substantially parallel ridges and troughs and configured to provide rigidity to the housing.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: July 21, 2015
    Assignee: Z124
    Inventors: Charles Becze, Rich Michonski
  • Patent number: 9086549
    Abstract: The locking insertion mechanism (15) is equipped with thrust components, bumper components, the control lever (1) and with reversibly horizontally sliding mechanism of the locking slider (6) with a safety component for securing the control lever (1) in its secure closed position during the defined insertion of the plug-in component (10) into the guide frame (11) and the previously-defined axial connection of optical and/or electronic connectors (8) in connector casings (9) in their axes. The method for performing the plug-in connecting of the optical and/or electronic connectors (8) into the connector casings (9) is performed in three phases.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: July 21, 2015
    Assignee: SQS Vláknová Optika a.s.
    Inventors: Michael Písa{hacek over (r)}ík, Ilja Kop{dot over (a)}{hacek over (c)}ek, Lud{hacek over (e)}k {hacek over (C)}erník
  • Publication number: 20150138741
    Abstract: There are provided a chip embedded board and a method of manufacturing the same. The chip embedded board includes: a core substrate; a first build-up layer formed on one surface of the core substrate and having a cavity formed therein; a chip disposed in the cavity; and an insulating layer filled in the cavity in which the chip is disposed, wherein one surface of the chip is positioned in a circuit layer positioned at the outermost layer of the first build-up layer.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seon Hee Moon, Young Do Kweon, Jeong Ho Lee
  • Patent number: 9036362
    Abstract: An electronic component incorporated substrate includes a first substrate and a second substrate that are electrically connected to each other by a spacer unit. An electronic component is mounted on the first substrate and arranged between the first substrate and the second substrate. An encapsulating resin fills a space between the first substrate and the second substrate to encapsulate the electronic component. The spacer unit includes a stacked structure of a metal post and a solder ball stacked in a stacking direction of the first substrate and the second substrate. The spacer unit further includes an insulation layer that is formed on the second substrate and covers a side wall of the metal post.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 19, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Koichi Tanaka, Nobuyuki Kurashima, Hajime Iizuka, Satoshi Shiraki
  • Patent number: 9030837
    Abstract: Provided are systems and methods for a control assembly including: a first film that is in-molded that includes decorative graphics, a front surface and a rear surface; and a second film molded to the rear surface of the first film having a printed circuit that includes sensors, control circuits and interconnects and a front and rear surface; and an internal connector.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: May 12, 2015
    Inventor: Scott Moncrieff
  • Publication number: 20150116964
    Abstract: A component-embedded substrate includes a substrate portion, an embedded electronic component, and a resin portion. The substrate portion has inner electrodes on an inner principal surface. The embedded electronic component has terminal electrodes and is mounted to the substrate portion via solder fillets adhering to the respective terminal electrodes and the respective inner electrodes. The resin portion is stacked on the substrate portion, with the embedded electronic component embedded therein. The resin portion includes a no-filler-added layer and a filler-added layer. The no-filler-added layer extends from the inner principal surface to a height which allows at least the solder fillets to be covered. The filler-added layer contains an inorganic filler and extends from an interface with the no-filler-added layer to a height which allows at least the embedded electronic component to be covered.
    Type: Application
    Filed: January 2, 2015
    Publication date: April 30, 2015
    Inventor: Satoru Noda
  • Patent number: 9019715
    Abstract: A touch panel includes a substrate, a transparent sensor electrode pattern, a patterned compensation electrode, a passivation layer, a transparent shielding electrode and at least one connection structure. The substrate has a surface and includes a sensor region and a peripheral region. The transparent sensor electrode pattern is disposed on the surface of the substrate and in the sensor region. The patterned compensation electrode is disposed on the surface of the substrate and in the peripheral region, and the patterned compensation electrode and the transparent sensor electrode pattern are electrically isolated. The passivation layer is disposed on the surface of the substrate, covers the transparent sensor electrode pattern, and at least partially exposes the patterned compensation electrode. The transparent shielding electrode is disposed on the passivation layer.
    Type: Grant
    Filed: February 24, 2013
    Date of Patent: April 28, 2015
    Assignee: AU Optronics Corp.
    Inventors: Chia-Chun Yeh, Po-Yuan Liu, Wen-Chi Chuang, Pei-Jung Wu, Cheng-Ta Ho
  • Publication number: 20150109748
    Abstract: An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.
    Type: Application
    Filed: November 29, 2011
    Publication date: April 23, 2015
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Zhongyao Yu, Xia Zhang
  • Patent number: 9012786
    Abstract: A circuit board including a substrate having first and second dielectric layers of first and second dielectrics, the second dielectric containing 8 mass % or more of a glass net former component. At least one portion of an inner layer electrode has approximately two principal surfaces parallel to principal surfaces of the circuit board and a thickness of not less than 50 micrometers in a normal direction of the principal surfaces. The inner layer electrode and second dielectric layer contact with each other, and a ratio t/T of sum total thickness t of the second dielectric layer in contact with the inner layer electrode in a normal direction of the principal surface to sum total thickness T of the first dielectric layer in a normal direction of the principal surface is 0.1 or more.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 21, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Shinsuke Yano, Takami Hirai, Tsutomu Nanataki, Hirofumi Yamaguchi
  • Patent number: 9007779
    Abstract: According to one embodiment, an electronic apparatus includes a case, a printed circuit board contained in the case and having a through-hole, and a fixing member including a shaft portion inserted in the through-hole and a head portion located at one end of the shaft portion. The electronic apparatus also includes copper foil provided on the printed circuit board, and a cover film including an opening portion configured to expose part of the copper foil. The opening portion is located at a position which is to be covered with the head portion, and the cover film covers the copper foil at positions other than the position where the opening portion is located. The electronic apparatus further includes a conductive material provided on the copper foil inside the opening portion and configured to electrically connect the head portion and the copper foil to each other.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Yamamoto, Takahisa Funayama
  • Patent number: 9007782
    Abstract: In a first conductive layer and a third conductive layer that are respectively closest to a core layer having a storage portion that penetrates therethrough, four first penetrating holes and four first penetrating holes are formed so as to overlap part of an opening edge of the storage portion that is projected onto the first conductive layer and the third conductive layer, respectively.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 14, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Tatsuro Sawatari, Yuichi Sugiyama, Hiroshi Nakamura, Masaki Naganuma, Tetsuo Saji
  • Publication number: 20150098203
    Abstract: In a first conductive layer and a third conductive layer that are respectively closest to a core layer having a storage portion that penetrates therethrough, four first penetrating holes and four first penetrating holes are formed so as to overlap part of an opening edge of the storage portion that is projected onto the first conductive layer and the third conductive layer, respectively.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 9, 2015
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Tatsuro SAWATARI, Yuichi SUGIYAMA, Hiroshi NAKAMURA, Masaki NAGANUMA, Tetsuo SAJI
  • Publication number: 20150092369
    Abstract: A component-embedded substrate includes a multilayer body formed by stacking up a plurality of resin layers in a predetermined direction, a component embedded in the multilayer body, the component having a plurality of terminal electrodes, a plurality of joining conductors provided in the multilayer body and joined to the plurality of terminal electrodes, a plurality of wiring conductors provided in the multilayer body and electrically coupled to the plurality of joining conductors and at least one auxiliary member enclosed within an outer boundary of the component provided in the multilayer body. The auxiliary member may be electrically insulated from each of the plurality of wiring conductors and arranged to balance pressures acting on the plurality of terminal electrodes when pressure is applied on the multilayer body.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 2, 2015
    Inventor: Naoki Gouchi
  • Publication number: 20150092368
    Abstract: An electronic module includes a substrate, a built-in electronic component and a surface mount electronic component. A suckable region is provided on a front surface of the substrate. When viewed in a see-through manner in a direction perpendicular or substantially perpendicular to the front surface of the substrate, the suckable region is inside of a region in which one built-in electronic component is built in and a center of gravity of the electronic module is located inside of the suckable region. A protective layer is not provided on the front surface of the substrate on which the surface mount electronic component is mounted.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Inventor: Shigeru TAGO
  • Patent number: 8995141
    Abstract: An electronic device includes a first component electrically coupled to a second component. The first component and the second component are coupled by the base of a spring loaded connector.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Nidhi Rathi, Edward A. Lilgegren
  • Patent number: 8995142
    Abstract: Provided is a power module invented for easy manufacturing and fatigue reduction at a soldered portion, and a method for manufacturing the same. The power module according to the present invention comprises a substrate where electronic parts are mounted by soldering, and a mold case housing the substrate and including bus bars for electrical connection with an external apparatus. The mold case comprises partition plates forming an electronic part mount area where electronic parts are mounted on the substrate, and a bonding area for bonding to the bus bars, a first resin cast to the electronic part mount area, and a second resin cast to the bonding area.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: March 31, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Masato Saito, Hiroyuki Abe
  • Patent number: 8983399
    Abstract: Provided is an in-millimeter-wave dielectric transmission device. The in-millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of in-millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Hirofumi Kawamura, Yasuhiro Okada
  • Patent number: 8971054
    Abstract: A component assembly that can be easily built in a main substrate with high accuracy is formed such that a glass transition temperature of a built-in-component layer of an assembly substrate in which multiple capacitors are embedded is higher than a glass transition temperature of a built-in-component layer of a built-in-component substrate. Thus, thermal deformation of the component assembly is prevented when the built-in-component substrate in which the component assembly is built is heated during reflow, for example. The component assembly can thus be highly accurately built in the built-in-component substrate. Moreover, when the component assembly in which the multiple capacitors are embedded is built in the built-in-component substrate, electrode pads of the component assembly in which the multiple capacitors are embedded can be electrically connected to wiring layers of the built-in-component substrate by soldering despite the variation in height among the capacitors.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masanori Fujidai, Kazuo Hattori, Isamu Fujimoto
  • Patent number: 8971053
    Abstract: A wiring board includes a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on a surface of the first substrate and including interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including conductive circuits for being connected to semiconductor elements, a filler filling the opening portion such that the interposer is held in the opening portion of the built-up layer, and mounting pads formed on the first substrate and positioned to mount the semiconductor elements. The mounting pads are positioned to form a matrix on the first substrate.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 3, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani
  • Patent number: 8963016
    Abstract: Disclosed is a printed wiring board offering improved reliability through increased mechanical strength at the bottom of cavity areas for mounting components. A printed wiring board 10 is characterized in that an insulation layer 16 is formed on either the top or bottom side of a metal core 11, while an opening 12 formed in the metal core 11 is used as a cavity area 15a for mounting a component, wherein a reinforcement pattern 30 is formed on the surface of an insulation layer facing the bottom of the cavity area 15a in the insulation layer 16. The reinforcement pattern 30 is made of the same material as the wiring patterns 28c, 29c formed on the insulation layer 16, and also formed simultaneously with these wiring patterns 28c, 29c.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: February 24, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Hideki Yokota, Masashi Miyazaki
  • Patent number: 8964409
    Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component (1) with contact terminals (2) and conducting lines (4) in a first wiring layer (3). There is also a dielectric (5) between the component (1) and the first wiring layer (3) such that the component (1) is embedded in the dielectric (5). Contact elements (6) provide electrical connection between at least some of the contact terminals (2) and at least some of the conducting lines (4). The electronic module also comprises a second wiring layer (7) inside the dielectric (5). The second wiring layer (7) comprises a conducting pattern (8) that is at least partly located between the component (1) and the first wiring layer (3) and provides EMI protection between the component (1) and the conducting lines (4).
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 24, 2015
    Assignee: GE Embedded Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 8953331
    Abstract: A card key has a molded body and an upper and a lower housings. The molded body has a circuit board, to which electronic parts for communicating with an in-vehicle equipment are mounted and which is covered with resin. The molded body is formed in a plate shape. The upper and the lower housings are fixed to each other so that the molded body is arranged between them. An external appearance of the card key is defined by the upper and the lower housings.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: February 10, 2015
    Assignee: Denso Corporation
    Inventors: Keiichi Sugimoto, Mitsuru Nakagawa
  • Patent number: 8942002
    Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to a thin interposer disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can insulate the components from one another and also couple signals between the components on the first and second layers. In one embodiment, the components in the first and second layers are passive components.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: January 27, 2015
    Inventors: Shawn X. Arnold, Douglas P. Kidd, Sean A. Mayo, Scott P. Mullins, Dennis R. Pyper, Jeffrey M. Thoma, Kenyu Tojima
  • Publication number: 20150022984
    Abstract: An embedded printed circuit board and a method of manufacturing the same. The embedded printed circuit board includes: an insulating layer on which a cavity is formed; a chip mounted on the cavity; and a circuit layer formed on the insulating layer, wherein the insulating layer is made of photosensitive compositions including photosensitive monomer and photoinitiator. As a result, the cavity can be formed by selectively using only the insulating layer, thereby making it possible to secure a degree of freedom in the design of the embedded printed circuit board.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 22, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyungmi JUNG, Jaechoon Cho, Choonkeun Lee, Taesung Jeong, Seungeun Lee, Jinsun Park, Yeena Shin
  • Publication number: 20150022983
    Abstract: A method includes depositing a thin film on a first surface of a first substrate and moving a second surface of a second substrate into contact with the thin film such that the thin film is located between the first and second surfaces. The method further includes generating electromagnetic (EM) radiation of a first wavelength, the first wavelength selected such that the thin film absorbs EM radiation at the first wavelength. Additionally, the method includes directing the EM radiation through one of the first and second substrates and onto a region of the thin film until the first and second substrates are fused in the region.
    Type: Application
    Filed: July 31, 2014
    Publication date: January 22, 2015
    Inventors: David A. Ruben, Michael S. Sandlin
  • Patent number: 8937255
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 20, 2015
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Publication number: 20150016078
    Abstract: The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: Dan YANG, Song HE, Yuxing REN, Xunqing SHI
  • Patent number: 8935010
    Abstract: This disclosure describes techniques for managing a power supply for hot-swappable components of a high-power networking device. According to these techniques, a high-power networking device includes a power distribution module (PDM). The PDM is receive a high-voltage, high-power supply input, generate supply plurality of high-power, reduced voltage supplies, and distribute the plurality of high-power reduced voltage supplies to a plurality of hot-swappable components of the high-power networking system via an intermediate distribution plane.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: January 13, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Katsuhiro Okamura, Nathan Berg
  • Patent number: 8929090
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventors: Yoshiki Nakashima, Shintaro Yamamichi, Katsumi Kikuchi, Kentaro Mori, Hideya Murai