Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Abstract: Provided is an electromagnetic wave shielding film capable of easily exhibiting excellent conductivity between a ground member and a shielding layer when the ground member is disposed on the electromagnetic wave shielding film. In the electromagnetic wave shielding film 1, the conductive adhesive layer 11, the shielding layer 12, and the insulating layer 13 are laminated in this order, and a ratio [conductive adhesive layer/insulating layer] of Martens hardness of the conductive adhesive layer 11 in accordance with ISO14577-1 to Martens hardness of the insulating layer 13 in accordance with ISO14577-1 is 0.3 or more.

Abstract: First and second conductors extend on and along a first surface of a substrate. The first conductor includes first and second parts extending in first and second directions and a third part connected to the first and second parts. The second conductor includes fourth and fifth parts extending in the first and second directions and a sixth part connected to the fourth and fifth parts. A first insulator partly covers the first surface, covers the first to fifth parts, and is partly opened in a first region extending along the sixth part above the sixth part in a third direction.

Abstract: An electronic device with storage functionality is provided. The electronic device includes a first housing member, a first circuit board, a second housing member and a second circuit board. The first circuit board is connected to the first housing member. The second circuit board is coupled to the first circuit board and is parallel to the first circuit board. The first housing member includes two hooks, and the hooks are wedged against the first edge of the second circuit board.

Abstract: Broadly, embodiments of the inventive concepts disclosed herein are directed to a PCB data board that allows for either a single configuration or to be deployed in conjunction with another configuration such as being able to control a radio and sending PLI (Positional Location Information) data. The PCB data board and associated code can accommodate multiple different configurations. The PCB data board may facilitate multiple radio connectivity, enhanced configuration utilities, and additional functions.

Abstract: Disclosed are monolithically integrated three-dimensional (3D) DRAM array structures that include one-transistor, one-capacitor (1T1C) cells embedded at multiple device tiers of a layered substrate assembly. In some embodiments, vertical electrically conductive data-line and ground pillars extending through the substrate assembly provide the transistor source and ground voltages, and horizontal electrically conductive access lines at multiple device levels provide the transistor gate voltages. Process flows for fabricating the 3D DRAM arrays are also described.

Abstract: Packaged modules for use in wireless devices are disclosed. A substrate supports integrated circuit die including at least a portion of a baseband system and a front end system, an oscillator assembly, and an antenna. The oscillator assembly includes an enclosure to enclose the oscillator and conductive pillars formed at least partially within a side of the enclosure to conduct signals between the top and bottom surfaces of the oscillator assembly. Components can be vertically integrated to save space and reduce trace length. Vertical integration provides an overhang volume that can include discrete components. Radio frequency shielding and ground planes within the substrate shield the front end system and antenna from radio frequency interference. Stacked filter assemblies include passive surface mount devices to filter radio frequency signals.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM. For example, embodiments may include a substrate with a first layer and a second layer parallel to the first layer with a first trace coupled with the first layer in a routing configuration and a second trace coupled with the second layer in the routing configuration, where the routing configuration of the first trace and the second trace substantially overlap each other with respect to an axis perpendicular to the first layer and the second layer, and where the first trace and the second trace are electrically coupled by a first and a second electrical coupling perpendicular to the first layer and the second layer.

Abstract: A wearable device according to various embodiments may include a display configured to allow external light toward a first surface to go through a second surface opposite to the first surface, and having a display area on the second surface, a memory for storing instructions, at least one camera, and at least one processor configured to, when executing the instructions, display content on the display area of the display, detect an external entity using the at least one camera, recognize the external entity as a controller for controlling the content having one designated shape of a plurality of designated shapes, identify a posture change of the external entity recognized as the controller, a gesture input for the external entity recognized as the controller, or a combination thereof using the at least one camera, and control the content, based on the identification.

Abstract: A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Abstract: A component mounting machine, including a component transfer device, having a component mounting tool configured to collect and mount a component, a mounting head configured to hold the component mounting tool, and a head driving mechanism configured to horizontally drive the mounting head, which performs a mounting work of mounting the component collected from a component supply device on a predetermined coordinate position of a board carried in and positioned by a board conveyance device, and a control device configured to control the mounting work, and configured to implement a thermal correction process for reducing an influence on mounting accuracy of the component, of which influence being caused by thermal deformation due to a temperature change in at least one of the head driving mechanism and the mounting head.

Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

Abstract: An electronic device including a shielding member for performing an electromagnetic interference (EMI) shielding function is provided. The electronic device includes a printed circuit board including a first area in which first electronic components having a first frequency as a driving frequency are mounted, and a second area in which second electronic components having a second frequency as a driving frequency are mounted, a shielding film disposed to cover the first area and the second area of the printed circuit board and attached to a first ground portion of the printed circuit board, and at least one conductive member formed to extend in a direction perpendicular to an extending direction of the printed circuit board. The at least one conductive member includes a first end that contacts the shielding film, and a second end that contacts a second ground portion of the printed circuit board, the second end being disposed between the first area and the second area of the printed circuit board.

Abstract: According to one embodiment, a display device includes a first submodule having a display panel, a second submodule having a cover member located on the display panel, and a first decoupling layer located between the first submodule and the second submodule, and each of the first submodule and the second submodule has a single neutral plane.

Abstract: An example electronic device includes a controller and a connector coupled to the controller. The connector includes a first set of pins and a second set of pins. The controller concurrently is to communicate with a first module of a modular computing system via the first set of pins and to communicate with a second module of the modular computing system, coupled to the first module, via the second set of pins.

Abstract: A high frequency module includes a power amplifier and a substrate on which the power amplifier is mounted. The power amplifier includes a first external terminal and a second external terminal formed on a mounting surface. The substrate includes a first land electrode and a second land electrode formed on one principal surface. The first external terminal is connected to the first land electrode, and the second external terminal is connected to the second land electrode. A distance from the mounting surface to a connection surface of the first external terminal is shorter than a distance from the mounting surface to a connection surface of the second external terminal, and a distance from a connection surface of the first land electrode to the one principal surface is longer than a distance from a connection surface of the second land electrode to the one principal surface.

Abstract: Disclosed are substrates having an electronic component, including a frame having a through hole, the electronic component disposed in the through hole, a first wiring portion formed on a surface of the frame and the electronic component, a first layer formed on the first wiring portion, and a second wiring portion formed on the first layer, and the second wiring portion including an antenna layer.

Abstract: An electronic component built-in wiring board includes a substrate having a cavity, an electronic component accommodated in the cavity of the substrate and having pads on a surface of the component, a coating insulating layer formed on the substrate such that the insulating layer is covering the component and has via holes, via conductors formed in the via holes such that the via conductors are penetrating through the insulating layer, and a resin coating formed between the component and the insulating layer and having through holes such that the through holes are partially exposing the pads in the via holes and that the coating has adhesion to the component that is stronger than adhesion of the insulating layer to the component. The via conductors are formed in the via holes and the through holes such that the via conductors are connected to the pads on the surface of the component.

Abstract: Systems, apparatuses, and methods related to a printed circuit board (PCB) with a plurality of layers are described. An edge connector may be formed on an end of the PCB substrate and may include contact pins on an outer layer of the plurality of layers. The edge connector may also include an intra-pair coupling block disposed on one or more interior layers such that at least a portion of the intra-pair coupling block is colinear with at least one contact pin on the outer layer. The electronic device may also include at least one integrated circuit on the PCB and electrically connected to the contact pins. The intra-pair coupling component may induce coupling of signals carried by the contact pins.

Abstract: A connector includes a flat-plate housing made of insulating resin and including a first positioning hole and a second positioning hole, a plurality of contacts held on the housing, and a first hold-down and a second hold-down made of metal and disposed to correspond to a first positioning hole and a second positioning hole, respectively. The housing includes a CPU board opposed surface to be opposed to a CPU board. The first hold-down includes a reinforcing plate part to cover the CPU board opposed surface around the corresponding first positioning hole. The second hold-down includes a reinforcing plate part to cover the CPU board opposed surface around the corresponding second positioning hole.

Abstract: A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure.

Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.

Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.

Abstract: A semiconductor arrangement includes at least one switching device, electrically coupled between a first terminal and a second terminal, at least one diode, coupled in parallel to the at least one switching device between the first terminal and the second terminal, at least one bonding pad, and at least one electrically connecting element. Each of the at least one electrically connecting element is arranged to electrically couple one of the at least one switching device to one of the at least one diode. Each electrically connecting element includes a first end, a second end, and a middle section, and for at least one of the electrically connecting element, the first end is mechanically coupled to the respective switching device, the second end is mechanically coupled to the respective diode, and the middle section is mechanically coupled to at least one of the at least one bonding pad.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

Abstract: Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.

Abstract: Provided is a circuit module including a power supply chip module, a load chip module, and a system board. A power supply output terminal group of the power supply chip module is arranged side by side in a row along a side of the power supply chip module board, the power supply input terminal group of a load chip module includes a specific terminal group arranged in a specific row that is a row along a side of the load chip module board, and a wiring width along an arrangement direction of the power supply output terminal group of a wiring pattern in which the power supply output terminal group is connected to the system board is equal to or more than a wiring width W31 along an arrangement direction of the specific terminal group of the wiring pattern in which the specific terminal group is connected to the system board.

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

Abstract: An electronic device comprises: a first plate configured to face one surface of the electronic device; a second plate configured to face in a direction opposite to the first plate; a side bezel structure connected to the first plate and the second plate and configured to surround the side of the electronic device; and a printed circuit board mounted in the electronic device and configured to be connected to the side bezel structure, wherein the printed circuit board comprises: a ground area; a first conductive pad, disposed in one area of the printed circuit board, and configured to couple the side bezel structure and the printed circuit board; and a second conductive pad electrically connected to the ground area and disposed between the first conductive pad and the ground area, wherein the first conductive pad and the second conductive pad may be disposed at an interval through which a current, having a voltage equal to or greater than a threshold voltage between the first conductive pad and a second electro

Abstract: A wireless communication device is provided and includes a communication module, a dust and moisture resistant adhesive, and a nano-metallic layer. The communication module includes a circuit board, a communication chip and a plurality of passive components mounted on a carrying surface of the circuit board, and an insulating sheet that is disposed on the passive components and that has a thickness smaller than or equal to 150 ?m. The dust and moisture resistant adhesive covers any electrically conductive portions of the communication module on the carrying surface. The nano-metallic layer covers the dust and moisture resistant adhesive, the communication chip, the passive components, and the insulating sheet, and is electrically coupled to a grounding portion of the circuit board. The wireless communication device does not include any grounding metal housing mounted on the circuit board.

Abstract: A printed circuit board comprises a first mounting surface, a second mounting surface, and a piezoelectric transformer. The piezoelectric transformer has a piezoelectric substance, external electrodes, and a frame substrate. The second mounting surface has a projection region. There is a first region from a first location, where an end portion further from the output electrode out of end portions of the input electrode is projected onto the second mounting surface in the projection region, to a second location, where an end portion closer to the output electrode out of the end portions of the input electrode is projected onto the second mounting surface, the first region being a mounting allowed region where an electronic component is mounted.

Abstract: A high frequency module in which warpage does not easily occur is provided by adjusting linear expansion coefficient, glass transition temperature, and elastic modulus of a sealing resin layer. The high frequency module includes a wiring board, a first component mounted on a lower surface of the wiring board, a plurality of connection terminals, a first sealing resin layer that coats the first component and the connection terminal, a plurality of second components mounted on an upper surface of the wiring board, a second sealing resin layer coating the second components, and a shield film. The first sealing resin layer is formed thinner than the second sealing resin layer, and the first sealing resin layer has the linear expansion coefficient of the resin smaller than the linear expansion coefficient of the resin of the second sealing resin layer.

Abstract: A transparent display device has a first substrate, a second substrate, and a display medium disposed between the first substrate and the second substrate. A pixel unit of the transparent display includes a transparent region and a display region. In the display region, a first reflective material is disposed between the first substrate and the display medium, and a second reflective material is disposed between the second substrate and the display medium.

Abstract: A solderable circuit board module system includes at least a first solderable circuit board module and a second solderable circuit board module, wherein the first solderable circuit board module has a first module circuit board having a top side and an underside provided for placement on a motherboard, wherein on the underside of the first module circuit board, solder connection contacts are arranged in a first frame-shaped contact region around a central middle section, which is free of connection contacts. The second solderable circuit board module has additional solder connection contacts, which form an outer frame around the first frame-shaped contact region, as a second group.

Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

Abstract: A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

Abstract: A detection system for non-standard connection interface through an adapter card. In the detection system, snaps of a first assembly are inserted through fastening slots of an adapter card, to make the first assembly and the adapter card fasten and engage with each other; the snaps of the first assembly are further inserted through engaging slots of a second assembly, to make the first assembly, the adapter card and the second assembly engage and fasten with each other; a motherboard is electrically connected to the adapter card, and the adapter card is electrically connected to a standard test adapter card, and the standard test adapter card is electrically connected to a standard BSI development test fixture, thereby achieving the technical effect of restraining protection for the adapter card and improvement of stability in detection for the non-standard connection interface.

Abstract: There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.

Abstract: An inertial sensor includes: a sensor unit; a base substrate having the sensor unit arranged at one surface thereof and having a first lateral surface and a second lateral surface; a package accommodating the sensor unit and the base substrate and having an inner bottom surface, a first inner wall surface, and a second inner wall surface; a first adhesive bonding together an other surface of the base substrate and an inner bottom surface of the package; a second adhesive bonding together the first inner wall surface of the package and the first lateral surface; and a third adhesive bonding together the second inner wall surface of the package and the second lateral surface.

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices.

Abstract: Provided is a storage system including a decoupling device having a plurality of unit capacitors. The storage system includes a storage device, a control device, and a decoupling device disposed on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an inner voltage. The decoupling device is connected to the control device and decouples the inner voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal. Some of the unit capacitors are selectively connected with each other to constitute the decoupling capacitors having various capacitances.

Abstract: A micro-electrical-mechanical system (MEMS) assembly includes a micro-electrical-mechanical system (MEMS) actuator configured to be coupled, on a lower surface, to a printed circuit board, an image sensor assembly coupled to an upper surface of the micro-electrical-mechanical system (MEMS) actuator, and a holder assembly coupled to and positioned with respect to the micro-electrical-mechanical system (MEMS) actuator.

Abstract: The present application relates to structures for supporting mechanical, electrical and/or electromechanical components, devices and/or systems and to methods of fabricating such structures. The application describes a primary die comprising an aperture extending through the die. The aperture is suitable for receiving a secondary die. A secondary die may be provided within the aperture of the primary die.

Abstract: A component carrier includes a stack comprising at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component embedded in the stack, and at least one stress relief opening formed in each of the at least one electrically conductive layer structure arranged in the stack on one side of the component so that a portion of the stack extending from an exterior main surface of the component carrier up to a main surface of the component on said side and including the at least one stress relief opening is free of electrically conductive material.