Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: A number of different sealed interfaces for power modules are described. In one example, a sealed interface includes a printed circuit board including a contact pad for power conduction to a bus bar of the printed circuit board, a semiconductor module including at least one power transistor, a terminal pin electrically coupled to the power module, and a housing for the power module. The housing includes an open terminal aperture that extends through the housing. The printed circuit board is seated upon the open terminal aperture, to close and seal the open terminal aperture, with the contact pad positioned within the open terminal aperture. The terminal pin contacts the contact pad of the printed circuit board within the open terminal aperture, and the open terminal aperture comprises a transitional feature to abate electric field intensity around an interface between the open terminal aperture and the printed circuit board.

Abstract: A printed wiring board includes a first insulating layer, a conductor layer, and a second insulating layer. The conductor layer includes first and second circuits such that space is formed between the circuits, the first circuit has first and second side walls, the second circuit has third and fourth side walls such that the second wall faces the third wall, the first circuit has first, second and third portions, the second circuit has fourth, fifth and sixth portions such that the first and fourth portions, the second and fifth portions and the third and sixth portions face each other, the first circuit is formed such that the second wall of the second portion is recessed from the second wall of the first and third portions, and the first insulating layer has recess between the second and fifth portions such that the second insulating layer is filling the space and recess.

Abstract: A technique for dissipating heat from a plurality of components is proposed. An electric component (1) includes a substrate (400), a first component (412), a second component (401), and a heat sink (31). The substrate (400) has a first surface (400b) and a second surface (400a) opposite to the first surface (400b). The first component (412) is disposed on a side of the first surface (400b). The second component (401) includes a body (401a) disposed on a side of the second surface (400a), and a lead (401b) that extends from the body (401a) through the second surface (400a) to the first surface (400b). The heat sink (31) is disposed on the side of the first surface (400b), and is used in common for dissipation of heat from the body (401a) through the lead (401b) and dissipation of heat from the first component (412).

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.

Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: An electronic device includes a base layer including a flat region and a bendable region extending from the flat region, a display module disposed on the base layer and overlapping the flat region, a window disposed on the display module and having a display region and a non-display region adjacent to the display region, and an antenna layer overlapping the non-display region of the window and disposed on one side of the display module, wherein the antenna layer includes an antenna module and an insulating layer surrounding the antenna module.

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for wireless power transmission. In accordance with this disclosure, a wireless power transmission apparatus (such as a charging pad) may support positional freedom such that a wireless power receiving apparatus may be charged regardless of positioning or orientation of the wireless power receiving apparatus. Various implementations include the use of multiple primary coils in a wireless power transmission apparatus. The multiple primary coils may be configured in a pattern, size, shape, or arrangement that enhances positional freedom. In some implementations, the placement of the multiple primary coils may optimize the size and distribution of electromagnetic fields that are available to charge a wireless power receiving apparatus.

Abstract: A commonly designed processor heat exchanger decouples the mounting hardware used to mount the heat exchanger to a processor from the heat exchanger itself. This allows a single heat exchanger design to be mounted to various different types of processors using processor customized mounting brackets that engage with flanges extending out from a body of the heat exchanger.

Abstract: Provided are a flexible circuit mother board and a detection method. The flexible circuit mother board includes flexible circuit daughter boards, at least one detection terminal group and external pad groups corresponding to the flexible circuit daughter boards in one-to-one correspondence. Each flexible circuit daughter board has a bonding pad area adjacent to a corresponding one of the plurality of external pad groups. Each detection terminal group detects at least one flexible circuit daughter board, and each of the at least one detection terminal group comprises a plurality of detection terminals. Each flexible circuit daughter board includes a plurality of capacitors including a first electrode plate and a second electrode plate. Each of the first electrode plate and the second electrode plate is electrically connected to one detection terminal.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

Abstract: A multi-chip module (MCM) includes a first integrated circuit (IC) chip to receive first data. The first IC chip includes a first transfer interface to transmit the first data off the first IC chip. A second IC chip includes an input interface to receive the first data from the first IC chip. The second IC chip includes switching circuitry to selectively forward the first data to one of a first output interface or a second output interface. The first output interface is communicatively coupled to a third IC chip, while the second output interface is configured to output the first data from the MCM.

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Abstract: A high-frequency module (1) includes a substrate (10), a first electronic component (30) and a second electronic component (40) mounted on a main surface (10a) of the substrate (10). The substrate (10) has a protruding portion (20) projecting from the main surface (10a), the first electronic component (30) is mounted in a region of the main surface (10a) different from a region in which the protruding portion (20) is provided, and the second electronic component (40) is mounted on the protruding portion (20).

Abstract: Provided is a semiconductor device capable of improving the divisibility of a wafer by concentrating crack stress by disposing notch patterns on a scribe line of a wafer, by locally removing a metal thin film in a scribe line and propagating a dividing energy in a vertical direction of a die surface. A semiconductor device includes: die regions spaced apart from each other in a wafer, scribe line regions disposed between neighboring ones of the die regions and covered with a metal material layer, and one or more open areas disposed in each of the scribe line regions and formed by locally removing the metal material layer, wherein each of the open areas includes one or more notch patterns indicating a direction in which the scribe line region is extended.

Abstract: A semiconductor light-emitting device, includes: a semiconductor light-emitting element; a support including a base and a conductive part and configured to support the semiconductor light-emitting element; and a cover configured to overlap the semiconductor light-emitting element as viewed in a first direction, and to transmit light from the semiconductor light-emitting element, wherein the cover includes a base layer having a front surface and a rear surface which transmit the light from the semiconductor light-emitting element and face opposite sides to each other in the first direction, wherein the rear surface faces the semiconductor light-emitting element, wherein the base layer includes a plurality of undulation parts bonded to the support by a bonding material, and wherein the undulation parts are more uneven than the rear surface.

Abstract: An optical module includes a circuit board having a through hole for the lead terminal, a signal wiring connected to the lead terminal, a ground layer providing a reference potential, an opening through which the ground layer is exposed, and a bonding material connecting the ground layer to the metallic base. The lead terminal extends in a first direction, and the circuit board and the signal wiring extend in a second direction. When the circuit board is viewed from the first direction, the opening overlaps with the signal wiring, or when the opening does not overlap with the signal wiring, a first distance between the signal wiring and a closest point of the opening to the signal wiring is smaller than a second distance between the closest point and an edge of the circuit board.

Abstract: A transient or biodegradable battery is provided having a filament structure that limits the speed of reaction allowing for a longer duration of battery power with a controlled current limit. In one embodiment, the filament may be constructed of zinc microparticles or nanoparticles having a thin outer insulation whereby a chemical reaction at the center core results in the progressive disintegration of the insulation revealing more core material. In one embodiment, microparticles or nanoparticles are coated with outer layers of chitosan and Al2O3 nanofilms, respectively, with designable discharge current and battery lifespan by controlling the exposed cross-sectional area of the zinc microparticle center core and the length of the filament, respectively. This novel structure of biodegradable battery provides improved control of battery life and power output, providing a promising solution to power transient medical implants.

Abstract: An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

Abstract: A ground plane is disposed in a dielectric substrate or on the top surface of the dielectric substrate. A high-frequency semiconductor device is mounted on the bottom surface of the dielectric substrate. A shield structure that is provided in a space closer to the bottom surface than the ground plane is surrounds the high-frequency semiconductor device from below and sideways of the high-frequency semiconductor device and is connected to the ground plane. An opening is formed in the shield structure. A radiation-structure portion causes a high-frequency signal output by the high-frequency semiconductor device to be radiated through the opening.

Abstract: In an embodiment, an antenna may be formed by applying an insulator to a package body and forming at least a portion of the antenna as a conductor on the insulator.

Abstract: A display device includes a supporting substrate including a polymeric material, base substrate disposed on an upper surface of the supporting substrate, a pixel array disposed in a display area of the base substrate, a transfer wiring disposed in a bending area of the base substrate and electrically connected to the pixel array, and an organic filling portion disposed under the transfer wiring in the bending area. The base substrate includes an organic film including a polymeric material, and an inorganic barrier film overlapping the organic film and extending outwardly from an edge of the organic film. The organic filling portion contacts the organic film of the base substrate.

Abstract: A connection structure embedded substrate includes: a printed circuit board including a plurality of first insulating layers and a plurality of first wiring layers, respectively disposed on or between the plurality of first insulating layers; and a connection structure disposed in the printed circuit board and including a plurality of internal insulating layers and a plurality of internal wiring layers, respectively disposed on or between the plurality of internal insulating layers. Among the plurality of internal wiring layers, an internal wiring layer disposed in one surface of the connection structure is in contact with one surface of a first insulating layer, among the plurality of first insulating layers.

Abstract: A printed circuit board includes a substrate including an external connection pad; and a metal post extending to the outside of the substrate in a thickness direction of the substrate from the external connection pad. The metal post may include a first post portion, elongated while having a substantially constant width, a second post portion extending to the outside of the substrate in the thickness direction of the substrate while having a narrow width, and a third post portion extending to the outside of the substrate in the thickness direction of the substrate from the second post portion while having substantially the same width as the first post portion. The third post portion may forma lower end portion of the metal post.

Abstract: This application features a method of forming a nanoporous layer. The method includes steps of dispensing on a substrate a colloid composition comprising a liquid and a number of nanoparticle clusters, and subjecting the dispensed colloid composition to drying to form the nanoporous layer over the substrate. The nanoporous layer includes nanoparticles deposited to form a three dimensional network of irregularly shaped bodies. The nanoporous layer also includes a three dimensional network of irregularly shaped spaces that are not occupied by the three dimensional network of irregularly shaped bodies.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

Abstract: The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

Abstract: A ceramic electronic device includes: a multilayer chip in which dielectric layers are stacked, the multilayer chip having two end faces, an upper face, a lower face and two side faces; a plurality of internal electrode layers that are provided inside of the multilayer chip; and a pair of external electrodes that are provided on the two end faces and are connected to the plurality of internal electrode layers, wherein each of the pair of external electrodes has a smaller thickness in a region not connected to the plurality of internal electrode layers, has an inwardly inflected point as viewed toward the plurality of internal electrode layers, and has a larger thickness in a region connected to the plurality of internal electrode layers, as measured in a direction perpendicular to the corresponding end face.

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region.

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

Abstract: An embodiment of the present invention provides a display device including: a substrate including a display area in which an image is displayed and a non-display area disposed outside the display area; a pad portion disposed in the non-display area on the substrate and including a plurality of pads spaced apart by a predetermined distance; and a flexible printed circuit board bonded to the pad portion, wherein the flexible printed circuit board may include a plurality of leads, each of the plurality of pads may be bonded to each of the plurality of leads, each of the plurality of pads may include a contact pad electrode that contacts each of the plurality of leads, and the contact pad electrode may include a dummy electrode surrounding an edge of a lower surface of each of the plurality of leads.

Abstract: A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

Abstract: A connection structure embedded substrate includes a printed circuit board including a plurality of first insulating layers, and a plurality of first wiring layers disposed on or between the plurality of first insulating layers; and a connection structure embedded in the printed circuit board, and including a plurality of second insulating layers and a plurality of second wiring layers disposed on or between the plurality of second insulating layers. A lowermost second insulating layer of the plurality of second insulating layers includes an organic insulating material, and is in contact with an upper surface of one of the plurality of first insulating layers.

Abstract: An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

Abstract: This disclosure provides a package substrate including: a first dielectric layer formed of a first molding compound; a first conductive wire and a first conductive channel disposed in the first dielectric layer; a second dielectric layer formed of a second molding compound; a second conductive wire and a second conductive channel disposed in the second dielectric layer; a third dielectric layer formed of a third molding compound; a third conductive wire and a third conductive channel disposed in the third dielectric layer; a fourth dielectric layer formed of a fourth molding compound; a fourth conductive wire, a fourth conductive channel and a circuit device disposed in the fourth dielectric layer; wherein, a first empty region, a second empty region, a third empty region and a fourth empty region are formed in the first, second, third and fourth dielectric layers, respectively, and the empty regions are vertically overlapped.

Abstract: A package structure, including a conductive element, multiple dies, a dielectric body, a circuit layer and a patterned insulating layer, is provided. The multiple dies are disposed on the conductive element. A portion of the conductive element surrounds the multiple dies. The dielectric body covers the multiple dies. The circuit layer is disposed on the dielectric body. The circuit layer is electrically connected to the multiple dies. The patterned insulating layer covers the circuit layer. A portion of the patterned insulating layer is disposed between the dies that are adjacent. A manufacturing method of a package structure is also provided.

Abstract: A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.

Abstract: A display apparatus, includes: a flexible circuit board including a first board pad and a second board pad, which are spaced apart from each other in a first direction and extend in a second direction intersecting the first direction; a main circuit board coupled to the flexible circuit board; and a display panel coupled to the flexible circuit board, the display panel including a first display pad overlapped with the first board pad and a second display pad overlapped with the second board pad, wherein the first board pad includes a first, second, and third portions, and the second board pad includes a first, second, and third portions.

Abstract: A mounting apparatus includes: a bonding stage; a base; a mounting head for performing a temporary press-attachment process in which semiconductor chips are suction-held and temporarily press-attached to a mounted object and a final press-attachment process in which the temporarily press-attached semiconductor chips are finally press-attached; a film arrangement mechanism arranged on the bonding stage or the base; and a controller which controls driving of the mounting head and the film arrangement mechanism. The film arrangement mechanism includes: a film feed-out mechanism which has a pair of feed rollers with a cover film extended there-between and successively feeds out a new cover film; and a film movement mechanism which moves the cover film in a horizontal direction with respect to a substrate.

Abstract: An optoelectronic component is disclosed. In an embodiment an optoelectronic component includes a housing body, an optical element and a rabbet comprising a shoulder and a cheek, wherein the rabbet is located on an upper side of the housing body, wherein the optical element is located in the rabbet such that a brim of the optical element rests on the shoulder of the rabbet, wherein the upper side of the housing body comprises a rectangular shape, and wherein the shoulder of the rabbet is located only at corners of the rabbet.

Abstract: The invention provides a PCB for gallium nitride device, on which has been formed: a gallium nitride welding position to which first and second gallium nitride elements having different packages are interchangeably welded; a first/second driving circuit welding position to which a first/second driving circuit of the first/second gallium nitride element is welded; wherein the gallium nitride welding position includes: a first and second gate pad respectively welded to gate electrode of the first and second gallium nitride element and respectively connected to gate signal terminal of the first and second driving circuit; a first and a second ground pad; a first contact contactless connected to the first ground pad and directly connected to ground terminal of the first driving circuit; and a second contact contactless connected to the second ground pad and directly connected to ground terminal of the second driving circuit.

Abstract: A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.

Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.