Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

Abstract: A printed board includes a printed board body having a first side, a second side opposing the first side, and a through-hole; a printed conductor disposed on the first side of the printed board body; and a bus bar disposed on the second side of the printed board body, the bus bar including a terminal that extends through the through-hole. The terminal includes a plurality of branched terminal portions at a position corresponding to an interior of the through-hole, and at least one of the branched terminal portions is bent and attached to the printed conductor.

Abstract: A land pattern, a method of manufacturing a printed circuit board (PCB) and a PCB incorporating a land pattern. In one embodiment, the land pattern includes: (1) a quadrilateral component outline area having diagonally opposed first and second corners and diagonally opposed third and fourth corners, defined according to a body configuration of a particular component type and located on a surface of a substrate and (2) first and second exposed conductive pads located within said area respectively proximate said first and second corners, coupled to respective first and second circuit conductors of said substrate, configured according to a terminal configuration of said type and separated from said third and fourth corners such that a component of said particular component type may be placed on the land pattern in multiple orientations without causing a short circuit.

Abstract: To provide a connecting structure which can effectively suppress the generation of a crack and an exfoliation of a terminal.

Abstract: A signal connecting component is suitable to be disposed on a circuit board. The signal connecting component includes an insulation element, at least a first bridge line, at least a second bridge line, a plurality of first pins and a plurality of second pins. The first bridge line and the second bridge line are disposed on different layers of the insulation element. The first pins and the second pins are respectively electrically connected to both ends of the first bridge line and both ends of the second bridge line.

Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract: The present invention makes repair easy and reduces effects on the electrical connection conditions of an electronic component to an internal wiring after repair and on the mechanical strength of the repair part in a case of breakage or separation of an electrode for implementation of the electronic component. In a multilayer wiring board, a plurality of wiring sheets each having an internal wiring and a plurality of electrical insulating sheets are arranged alternately in the thickness directions of these sheets, and a plurality of electrodes for implementing an electronic component electrically connected to the internal wirings are formed on the surface of an uppermost sheet. The multilayer wiring board further comprises a plurality of spare electrodes corresponding to the electrodes and electrically connected to the internal wirings connected to the corresponding electrodes directly under the corresponding electrodes on a sheet located directly under the uppermost sheet.

Abstract: A ceramic substrate part comprising on its upper surface pluralities of external electrodes comprising wire-bonding electrodes, each of which comprises a primer layer based on Ag or Cu, a Ni-based lower layer, an intermediate layer based on a Pd—P alloy containing 0.4-5% by mass of P, and a Au-based upper layer formed in this order on a ceramic substrate, the upper layer containing Pd after heated by soldering, and having a Au concentration of 80 atomic % or more based on the total concentration (100 atomic %) of Au and Pd.

Abstract: A surface mountable device includes a ceramic substrate including a first principal surface, a second principal surface, and a side surface connecting the first principal surface to the second principal surface, a terminal electrode disposed on the first principal surface, and a first conductor for appearance inspection extending continuously from the terminal electrode to the side surface and having a width smaller than the width of the terminal electrode.

Abstract: An integrated circuit package system includes: providing a flexible circuit substrate having a fold; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a recessed encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover.

Abstract: A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The regions of rough surface contours include two-dimensional arrays of spots (401) comprising a central area (402) below the original surface (400) and a piled ring (403) above the original surface. The piled ring (403) consists of the leadframe material in amorphous configuration.

Abstract: A method of fabricating a rechargeable battery having an electrode assembly, a PCB and a battery case, wherein the electrode assembly is connected to the PCB, the method including preparing a PCB having a first surface with an external contact terminal formed thereon and having a second surface with a conductive feature formed thereon, wherein the conductive feature is electrically connected to the external contact terminal through a conductive trace, and plating the external contact terminal by electrically connecting a plating electrode to the conductive feature.

Abstract: An integrated circuit package system includes: providing a flexible circuit substrate; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a mounded encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode

Abstract: The present disclosure generally pertains to wireless communication modules that can be used for enabling wireless communication in various applications. A wireless communication module in accordance with one embodiment may be interfaced with other devices, such as nodes of a wireless sensor network (WSN). The module has rows of male integrated circuit (IC) pins that may be interfaced with female pin receptacles of another device. The module receives wireless signals and provides the data of such wireless signals to the other device. The module also receives data from the other devices and packetizes such data for wireless communication.

Abstract: A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern.

Abstract: A motor vehicle control device includes a housing lid and a base plate that are connected with each other in an oil-tight manner via a frame. An interconnect device with at least one electronic component and/or at least one electrical contact area is arranged on the base plate. Respectively in the area of an electronic component and/or an electrical contact area, the base plate includes a foil conductor strip, of which an end section facing the interconnect device in turn includes an electrical contact area. The frame completely surrounds the interconnect device and includes one opening respectively in the area of an electrical contact area of the foil strip. Via connection lines, the electronics on the interconnect device are electrically connected with the contact area in the opening, and thus with the electronic components outside the control device.

Abstract: A passive device having a portion in the package substrate and a portion in the system board such that the portions of the device are electromagnetically coupled. A transformer including inductors in the package substrate and system board electromagnetically coupled across a space between the substrate and board that is surrounded by solder balls coupling the substrate and board. A capacitor including plates in the substrate and board electromagnetically coupled across a space between the substrate and board that is surrounded by solder balls coupling the substrate and board. A core material can at least partially fill the space between the substrate and board. The solder balls surrounding the space can be coupled to ground. Metal shielding can be put in the substrate and/or board surrounding the device. The metal shielding can be coupled to the solder balls. The metal shielding can be coupled to ground.

Abstract: The present invention provides a SiP module for wireless local area network comprising a base. A control unit is formed on a first surface of the base and a RF front end components is formed on a second surface of the base and coupled to the control unit through the base. A plurality of group of bumps is arranged on the first surface and coupled to the control unit, and separated with one another to reduce the interference.

Abstract: The present invention provides an addressable or static electronic apparatus, such as a light emitting display. An exemplary apparatus comprises a substrate having a plurality of cavities; a plurality of first conductors coupled to the substrate and at least partially within the cavities, with the plurality of first conductors having a first and substantially parallel orientation; a plurality of light emitting diodes or other electronic components coupled to the plurality of first conductors and having a second orientation substantially normal to the first orientation; and a plurality of substantially optically transmissive second conductors coupled to the plurality of light emitting diodes and having a third orientation substantially normal to the second orientation and substantially perpendicular to the first orientation.

Abstract: An apparatus is disclosed that may include a printed circuit board (PCB) and an electronics package may be disposed about the first surface of the PCB. The PCB may include a metal layer and a core, and, in some aspects, may include multiple cores interposed between multiple metal layers, and in some embodiments a backplane may be disposed along the core. The metal layer may be disposed on a core first surface. The metal layer may comprise metal or other conductive material suitable to define traces, which may be circuit paths for electronic components affixed to the PCB. In some aspects, the core may be electrically non-conducting, and may be thermally insulating, and, accordingly, inhibit the transfer of heat from the electronics package through the PCB. However, pins may be configured to pass through the PCB including the core from the core first surface to the core second surface to conduct heat generated by the electronics package away for dispersion.

Abstract: The present disclosure is directed at an apparatus for changing printed circuit board pad structure to increase solder volume and strength. The invention provides increased end row pad and lead size and utilizes a plurality of lead-to-pad and pad-to-lead conforming geometric structures to form a joint providing additional solder surface adhesion area.

Abstract: A method of forming contacts for an interconnection element, includes (a) joining a conductive element to an interconnection element having multiple wiring layers, (b) patterning the conductive element to form conductive pins, and (c) electrically interconnecting the conductive pins with conductive features of the interconnection element. A multiple wiring layer interconnection element having an exposed pin interface, includes an interconnection element having multiple wiring layers separated by at least one dielectric layer, the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element, a plurality of conductive pins protruding in a direction away from the first face, and metal features electrically interconnecting the conductive features with the conductive pins.

Abstract: A semiconductor integrated circuit device described herein includes a semiconductor chip and a package on which the semiconductor chip is disposed. The semiconductor chip includes first electrode pads, and the package includes second electrode pads connected to the first electrode pads. The second electrode pads include signal pads and power supply pads, and are arranged in rows along the semiconductor chip. All the power supply pads of the second electrode pads are for supplying power to the semiconductor chip and are disposed in a row positioned farther from the semiconductor chip than another row. Each power supply line that leads out from a second power supply pad has a width not less than a width of the second power supply pad.

Abstract: A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.

Abstract: A wiring board of the present invention includes a dummy wiring in a semiconductor-chip mount area on which a semiconductor chip is to be mounted. The dummy wiring is arranged in a manner such that all wiring-lines included in the dummy wiring each have a free end within the semiconductor-chip mount area. This prevents a defect due to vaporization and expansion of moisture inside a semiconductor apparatus, with a simple structure and without raising costs.

Abstract: A method for producing a capping wafer for a sensor having at least one cap includes: production of a contacting via extending through the wafer, and, temporally subsequent thereto, filling of the contacting via with an electrically conductive material.

Abstract: A power amplifier and a signal transmitting system using the power amplifier are disclosed. The power amplifier includes a circuit board, a power amplifier, and a structural component. The circuit board is fixed on the structural component. The power amplifier is fixed on the circuit board or the structural component. A grounding reference layer is set on the structural component. A pair of pins is set on the power amplifier. A pair of housing portions is set between the circuit board and the structural component. Overhead matching areas are set face to face with the housing portions on the circuit board respectively. Power amplification matching portions are set face to face with the reference layer on the matching areas respectively. The pins are electrically connected to the power amplification matching portions respectively.

Abstract: A ceramic substrate part comprising on its upper surface pluralities of external electrodes comprising wire-bonding electrodes, each of which comprises a primer layer based on Ag or Cu, a Ni-based lower layer, an intermediate layer based on a Pd—P alloy containing 0.4-5% by mass of P, and a Au-based upper layer formed in this order on a ceramic substrate, the upper layer containing Pd after heated by soldering, and having a Au concentration of 80 atomic % or more based on the total concentration (100 atomic %) of Au and Pd.

Abstract: Provided is a circuit board which suppresses abnormal formation of plated layer inside a via, caused by core materials of glass fibers or the like projected from a side wall of the via and which helps to improve the connection reliability of the via. An insulating layer, which is formed of thermoset resin and embedded with glass fibers, is provided between a first wiring layer and a second wiring layer. The glass fibers projected into a via hole side from a side wall of the via hole in different positions are embedded into a via conductor in such a state that the glass fibers are jointed with each other.

Abstract: Provided is a circuit board including: a circuit board body with at least one surface having a plurality of electrically connecting pads; an insulating protection layer formed on the circuit board body and formed with an opening corresponding in position to one of the electrically connecting pads, being larger than the electrically connecting pad, and not being in contact with the periphery of the electrically connecting pad; and a soldering material formed on, and confined to, the electrically connecting pad; thus allowing an electrically conductive element limited in the opening formed in the insulating protection layer to be fabricated from the soldering material by a reflow process with a view to forming a fine-pitch electrically connecting structure.

Abstract: A portable electronic device (20) includes a circuit board (21) and at least one conducting pole (22). The conducting pole is mounted on the circuit board and includes a breakable portion (2224), the breakable portion is configured to be the part that breaks when the conducting pole is crumpled.

Abstract: A chip package including a die pad, a plurality of leads, a chip, an adhesive, and a molding compound is provided. The die pad has a top surface and a bottom surface opposite to the top surface, wherein the die pad has a blocking portion disposed on the top surface, and the leads are disposed around the die pad. The chip is disposed on the top surface of the die pad surrounded by the blocking portion and is electrically connected to the leads. A top surface of the blocking portion is higher than the top surface of the die pad surrounded by the blocking portion. The adhesive is disposed between the chip and the die pad. The molding compound encapsulates the chip, a portion of the leads, and the die pad.

Abstract: There are provided a printed circuit board having a structure for relieving a stress concentration on an outer most lead of leads, due to a difference in thermal expansion coefficients between the semiconductor device and the printed circuit board when the semiconductor device is mounted on the printed circuit board. The printed circuit board includes an inner lead portion to be connected to the semiconductor device. The inner lead portion includes a plurality of leads, arranged in parallel with a same pitch in a predetermined area, and additional leads located near both ends of the predetermined area in which the plurality of leads are arranged in parallel, respectively, wherein each of the plurality of leads has a pitch smaller than 30 ?m and a width of the additional lead is wider than 20 ?m. There are also provided a semiconductor chip package equipped with the printed circuit board according to the present invention.

Abstract: A multichip module comprises a multilayer substrate circuit having conductive patterns on its surface(s) to which microelectronic device(s) are attached. The conductive patterns include a series of electrical contacts adjacent to one edge of the substrate. The substrate is bonded to two rigid frames, one on each opposite surface. Each substrate has a series of castellations on one edge that are aligned and electrically connected to the respective contacts on the substrate, preferably by soldering. The castellations can serve as a self-aligning mechanism when the module is brought into contact with a low-profile pin array, and the module may be held in place on a motherboard by guide rails in a socket that engages the edges perpendicular to the castellated edge of the module. The module may further be provided with protective heat spreading covers.

Abstract: Provided is an electronic components assembly capable of effectively dealing with unwanted charge accumulated in a capacitor even when general-purpose components are used. An assembly 10 includes an electrolytic capacitor 1, a coil lead 4, and a circuit mounting board 5. The electrolytic capacitor 1 includes a main body 1a, an anode lead 2, and a cathode lead 3. The coil lead 4 is wrapped around the main body 1a. The circuit mounting board 5 has the electrolytic capacitor 1 and the coil lead 4 mounted thereon. The coil lead 4 is connected to a ground of the circuit mounting board 5.

Abstract: An electronic substrate includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed.

Abstract: A wiring board to be used with being mounted on a packaging board includes a chip component surface-mounted on a surface facing the packaging board. The chip component includes terminal electrodes at both end portions of the component body thereof. Each of the terminal electrodes is provided in a form in which a plated film (Sn) formed on the surface of the terminal electrode is separated into two portions, one portion being on the wiring board side, and another portion being on the packaging board side. In one aspect, each of the terminal electrodes of the chip component is separated into a portion on the wiring board side and a portion on the packaging board side, and the plated film (Sn) is formed on a surface of each of the separated portions of each of the terminal electrodes.

Abstract: An anisotropic conductive film, containing a resin film; and conductive particles aligned into a monolayer within the resin film adjacent to or on one plane of the resin film with respect to a thickness direction of the resin film, wherein a distance between the one plane of the resin film and a center of the conductive particle is 9 ?m or less based on 10-point average.

Abstract: A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.

Abstract: A printed wiring board which can certainly prevent damage of conductive pattern caused by the terminal. The printed wiring board has a board, a conductive pattern, a through-hole and a non-conductive area. A lead wire of resistance mounted on the printed wiring board is inserted into the through-hole 4. The lead wire projects from a surface of the board, and is bent close to the surface. The non-conductive area is formed into a fan-shaped shape enlarging toward a tip of the lead wire from a center of the through-hole. Because the bent lead wire is arranged on the non-conductive area, the non-conductive area can prevent damage of the conductive pattern which is caused by touching the lead wire to the conductive pattern.

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: An assembly structure is provided. The assembly structure includes a first substrate, a second substrate and a medium layer disposed between the first and second substrates. The medium layer includes a side edge, and the second substrate includes at least one lead wire. When the second substrate is disposed on the medium layer, the lead wire of the second substrate is relatively oblique to the side edge of the medium layer.

Abstract: A surface mounting lug terminal formed of a metallic plate having terminal leads and positioning projections can readily be positioned on a printed board with high precision by fitting the positioning projections into positioning cutouts formed in the printed board. The terminal leads of the surface mounting lug terminal can easily be soldered to land patterns on the printed board to secure the surface mounting lug terminal onto the printed board irrespective of the number of terminal leads. The surface mounting lug terminal can be reduced in size, thus to contribute miniaturization of electronic circuits.

Abstract: The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips.

Abstract: An electric drive (1) with a circuit board (2), having conductor tracks (3) and contact openings (4) with plated through-holes (5) and equipped with electronic components (6), the circuit board (2) being coated with a protective layer (7) of insulating material, and press-fit contacts (8) are inserted into the contact openings (4) and in electrical contact areas (9) within the contact openings (4) electrical contact exists between a press-fit contact (8) and the plated through-hole (5) of the contact opening (4). The task of the invention is to reliably protect circuit boards of electric drives exposed to moisture and other chemical environmental effects and contact them economically.

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.