Shaped Lead On Components Patents (Class 361/773)
  • Publication number: 20030095393
    Abstract: A wireless bonded semiconductor device comprises a semiconductor chip packaged on a metal lead frame, in which the semiconductor chip contains at least one contact electrically connected to a lead frame and a connecting-pin terminal leading out from its bottom face, and at least one contact and a plurality of individual connecting-pin terminals leading out from its top face, there is no metal bonding wire exists between the surface contact and individual connecting-pin terminals, instead a matrix of the connecting-pin terminal with pre-determined extension length that directly folded and bonded onto the surface contact of the semiconductor chip is employed.
    Type: Application
    Filed: September 18, 2002
    Publication date: May 22, 2003
    Applicant: Chino-Excel Technologies Corp.
    Inventors: Kou-Way Tu, Feng-Tso Chien, You-Ren Li, Jen-Huei Dung
  • Publication number: 20030067755
    Abstract: An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material disposed on a surface of the electronic component and has a conductive land on its crest. The rubber-elastic elevation also has on its sloping side or in its volume a conduction path between the land and the electronic circuit.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 10, 2003
    Inventors: Alfred Haimerl, Harry Hedler, Jens Pohl
  • Publication number: 20030043559
    Abstract: The three-dimensional disposition structure of an electric board component, comprising an electric board and several elements. The several elements includes several plane elements, which have at least one short connection leg, and several elevated elements, which have at least one long connection leg. Wherein, the plane element is welded onto the electric board and its bottom is close to the electric board, and the elevated element is welded onto the electric board and its bottom is above the plane element.
    Type: Application
    Filed: June 15, 2001
    Publication date: March 6, 2003
    Applicant: PATEN Technology Coporation
    Inventor: Canny Wang
  • Patent number: 6518650
    Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: February 11, 2003
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Larry D. Kinsman, Jerry M. Brooks
  • Patent number: 6518517
    Abstract: Electrical nets are prepared by bonding an electrically conductive element in a deleted plated via. The electrically conductive element has a headed portion that contacts the bottom of the laminate and the other end of the electrically conductive element electrically connects to a BGA pad or surface trace line.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Baechtle, Stephen R. Howland
  • Patent number: 6507496
    Abstract: A dual-sided circuit board module designed for an operating position that is not perpendicular to a system motherboard will be coupled to the motherboard by leads having at least two different lengths. Because leads of differing lengths have differing associated inductance, the operating characteristics of the leads and therefore the devices coupled to the leads will differ. In order to improve the operating characteristics of the module, integrated circuit packages are selected based on the inductive (and possibly other) qualities of the leads to which the respective packages are coupled. In one embodiment, leads having a larger inductance are coupled to integrated circuit (IC) packages having a smaller inductance and vice versa, which allows the inductive characteristics of the various components of the module to have more closely matching inductive characteristics than would otherwise be possible.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: January 14, 2003
    Assignee: Intel Corporation
    Inventors: Paul S. Levy, David Frame
  • Patent number: 6507109
    Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: January 14, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Larry D. Kinsman
  • Patent number: 6492737
    Abstract: An electronic device comprising: a semiconductor chip having plural electrode pads on one main surface thereof; a wiring board having plural connection parts; and plural salient electrodes disposed respectively between the electrode pads of the semiconductor chip and the connection parts of the wiring board to provide electrical connections between the two, the salient electrodes being arranged in an array not providing balance of the semiconductor chip with respect to one main surface of the wiring board, the plural connection parts of the wiring board being arranged at a deeper position than one main surface of the wiring board in a depth direction from the one main surface.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: December 10, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Norio Kishikawa, Yoshiyuki Kado, Kazuyuki Taguchi, Takahiro Naito, Toshihiko Sato
  • Patent number: 6483178
    Abstract: A semiconductor device package structure is proposed, which allows the encapsulation body to be highly secured in position to the leads, making the encapsulation body hardly delaminated from the leads. The proposed semiconductor device package structure comprises a die pad; a semiconductor chip mounted on the die pad; a plurality of leads arranged around the die pad, each lead being formed with a bolting hole; a plurality of bonding wires for electrically coupling the semiconductor chip to the leads; and an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads. The bolting hole is characterized in the forming of a constricted middle part or an inclined orientation with respect to the lead surface, which allows the encapsulation body to be highly secured in position to the leads, thereby making the encapsulation body hardly delaminated from the leads.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: November 19, 2002
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Jui-Yu Chuang
  • Patent number: 6483041
    Abstract: The invention is directed to techniques for forming a soldered connection using a pin having a channel. The channel enables the pin to form a secure connection with a via (e.g., by facilitating gas percolation out of the via hole during soldering to improve solder flow, by holding solder prior to pin insertion and soldering, or by facilitating accurate pin bending to hold solder or a pin insert prior to pin insertion and soldering) to improve connection system reliability and increase manufacturing yields. In one arrangement, the pin has a surface which includes (i) a first surface area, (ii) a second surface area that is substantially parallel to the first surface area, and (iii) a channel surface area which defines a channel that extends from the first surface area toward the second surface area. To form a soldered connection, the pin is inserted into a cavity defined by a via of a connecting member (e.g., a circuit board), in a direction that is parallel to a central axis of the via.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: November 19, 2002
    Assignee: EMC Corporation
    Inventor: Stuart D. Downes
  • Publication number: 20020131255
    Abstract: In accordance with the invention, a low impedance surface-mount connector comprises a length of cylindrical rod having an I-shaped cross section. The device permits interconnection by pick-and-place techniques, and the interconnection has advantageous qualities of low resistance, low inductance, mechanical compliance and ease of manufacture. A first circuit device having one or more circuit components is interconnected with a second circuit device by surface mounting such connectors on the first circuit device, providing corresponding solder pads on the second circuit device, and mounting the connectors of the first circuit device onto the pads of the second.
    Type: Application
    Filed: May 2, 2002
    Publication date: September 19, 2002
    Inventor: Apurba Roy
  • Patent number: 6449838
    Abstract: This invention mounts a semiconductor device having a plurality of electrodes to a substrate. A bump electrode having a pointed tail is formed on the electrode. The concave mounting pad is formed on the substrate. A sealing resin covers the substrate. And the tail of the bump electrode is buried into the sealing resin by putting the semiconductor device close to the substrate. Further, the semiconductor device is pressed to the substrate. And the sealing resin is hardened by heating.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: September 17, 2002
    Assignee: NEC Corporation
    Inventor: Tomoo Murakami
  • Patent number: 6452802
    Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: September 17, 2002
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
  • Patent number: 6452808
    Abstract: A power electronics module has a metal substrate, a printed circuit card carried on one of the faces of the substrate, and components, at least some of which are power components, mounted on the card. The card also carries electrical interconnection tracks between the components themselves and with external power supply. Conductive bridges of a shape enabling each of them to extend over a power component mutually interconnect short segments of interconnection tracks, that carry power current.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: September 17, 2002
    Assignee: Sagem SA
    Inventor: Jean Hoche
  • Patent number: 6445593
    Abstract: A chip type electronic component and a method of manufacturing the same reduces the steps necessary for applying an electrically conductive paste to define a first external electrode, a second external electrode and a third external electrode on the outer surface of an electronic component main body. External electrodes are provided around the side surfaces of the main body of the electronic component. The first external electrode is positioned on the first end surface of the main body, the second external electrode is positioned on the second end surface, the third external electrode is positioned between the first and second external electrodes. The first and second external electrodes are arranged to extend to edge portions of the first and second end surfaces, but exposing at least the approximate central portions of these end surfaces. In this way, the external electrodes are formed by applying the electrically conductive paste on the side surfaces of the main body.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: September 3, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Shingo Okuyama
  • Publication number: 20020117330
    Abstract: Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed.
    Type: Application
    Filed: December 28, 2001
    Publication date: August 29, 2002
    Applicant: FormFactor, Inc.
    Inventors: Benjamin Niles Eldridge, Gary William Grube, Igor Yan Khandros, Gaetan L. Mathieu
  • Patent number: 6430058
    Abstract: An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventors: Bob Sankman, Hamid Azimi
  • Patent number: 6429516
    Abstract: A bare chip mounting structure includes a bare chip having inlet or outlet terminals, an interposer having openings at positions corresponding to said inlet or outlet terminals of the bare chip and a circuit board having conductive pads wherein the bare chip is mounted on the circuit board by means of the interposer in such a manner that the inlet or outlet terminals are electrically connected to the conductive pads of the circuit board through the openings of the interposer.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: August 6, 2002
    Assignee: Fujitsu, Limited
    Inventor: Kazuhisa Tsunoi
  • Patent number: 6426880
    Abstract: Surface mount device packages with increased mounting strength and a method therefor. In one embodiment, an, electronic device is made up of a device package and one or more electrically conductive terminals. For surface mounting, the device terminals are each provided with a mounting surface which is bonded using a conductive adhesive to a corresponding contact pad on a circuit board. The terminals are further provided with at least one groove across the mounting surface. When conductive adhesive is used to mount the device on a circuit board, this groove serves to form the conductive adhesive into a ridge or “dam” over the contact pad. This provides increased mounting strength which may eliminate the need for additional adhesive material to provide side reinforcement of the device, and thereby allow an increase in the packing density of devices on the circuit board.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: July 30, 2002
    Assignee: Intermedics, Inc.
    Inventor: Philip H. Chen
  • Patent number: 6403892
    Abstract: A flex or TAB product suitable for chip carrier applications wherein the flex reliability problems caused by copper dendrite growth and lead bending during power and thermal cycling are reduced by application of special coatings to lead areas of the flex tape.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: June 11, 2002
    Assignee: International Business Machines Corporation
    Inventors: Claudius Feger, Teresita Ordonez Graham, Kurt Rudolph Grebe, Alphonso Philip Lanzetta, John Joseph Liutkus, Linda Carolyn Matthew, Michael Jon Palmer, Nelson Russell Tanner, Ho-Ming Tong, Charles Haile Wilson, Helen Li Yeh
  • Patent number: 6395991
    Abstract: Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Robert Charles Dockerty, Ronald Maurice Fraga, Ciro Neal Ramirez, Sudipta Kumar Ray, Gordon Jay Robbins
  • Patent number: 6396699
    Abstract: An apparatus for mounting a heat sink to a chip package such as a BGA type chip package or the like is disclosed. In an exemplary embodiment, ground bumps are formed on the die substrate of the chip package and on the heat mating surface of the heat sink to be attached to the package. The ground bumps formed on the die protrude into the body of dimples formed in the body of the chip encapsulation package to make thermal/electrical ground contact with the ground bumps formed on the heat mating surface of the heat sink for electrically grounding the heat sink.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: May 28, 2002
    Assignee: LSI Logic Corporation
    Inventors: Barry Caldwell, Craig C. McCombs
  • Patent number: 6388321
    Abstract: In order to obtain a semiconductor device of which bonding reliability between a semiconductor element 7 and a printed wiring board 1 is improved and a manufacturing method thereof, in a semiconductor device mounted a semiconductor element 7 on a printed wiring board 1, while a circumference of a metal bump 3 formed on a conductor pad electrode disposed on the printed wiring board in wiring pattern and an electrode 6 disposed along an external periphery of a semiconductor element 7 facing the metal bump 3 is provided with, along a placement position of the metal bump 3 or the electrode 6, frame- or wall-shaped anisotropic conductive film 4, a gap between the semiconductor element 7 and the printed wiring board 1, the insides of the anisotropic conductive film 4 formed in frame or wall shape, is filled by sealing material such as epoxy resin or the like.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: May 14, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Hirai, Yoshitaka Fukuoka
  • Patent number: 6379997
    Abstract: A semiconductor device includes a semiconductor element, a holding substrate holding the semiconductor element, a frame body provided on the holding substrate so as to surround the semiconductor element and having a hole which communicates to a space formed between the holding substrate and the frame body and the frame body and the holding substrate form a housing, a plurality of leads having inner lead portions connected to the semiconductor element and outer lead portions extending outside the frame body, and a resin filling the space and encapsulating the semiconductor element and the inner lead portions. All of the outer lead portions extend outside the housing from one side of the housing.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: April 30, 2002
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Toshimi Kawahara, Sinya Nakaseko, Mitsunada Osawa, Mayumi Osumi, Hiroyuki Ishiquro, Yoshitugu Katoh, Junichi Kasai, Shinichirou Taniguchi, Yuji Sakurai
  • Patent number: 6376782
    Abstract: In a resinous circuit board having a circuitized substrate having conductive layers therewithin, a plurality of pin pads formed on a rear surface of the substrate, and a plurality of pins, each pin having a tip end portion and a head portion and soldered to the pin pad in such a manner as to contact at the head portion to the pin pad. The head portion of the pin consists of a flange section which is larger in diameter than the tip end portion, and a part-spherical abutment section bulging from the flange section in the direction opposite to the tip end portion and brought into contact with the pin pad. The part-spherical abutment section is made of eutectic silver solder which is lower in melting point than solder such as Sn—Ag solder which is used for soldering the pin to the pin pad. Since the silver solder and soft solder are present between the flange section and the pin pad, they can release the stress applied to the pin, thus making it possible to increase the joining strength considerably.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: April 23, 2002
    Assignee: NGK-Spark Plug Co., Ltd.
    Inventors: Kazuo Kimura, Hajime Saiki, Mitsuo Shiraishi, Yosuke Kondo
  • Publication number: 20020039283
    Abstract: A circuit board module comprises a battery case 101 storing a battery of which external terminals 4 have a laminated members 8 made of different metal material for each other, a circuit board 102 for carrying out charge and discharge of the above-mentioned battery and a joint member 103 for connecting the battery case 101 and the circuit board 102 electrically and/or mechanically, wherein the joint body 103 is constructed by clad material that a first metal layer 111 and a second metal layer 112 made of different metal materials each other are laminated.
    Type: Application
    Filed: July 2, 2001
    Publication date: April 4, 2002
    Inventors: Satoshi Nakamura, Kohshi Nishimura
  • Patent number: 6365840
    Abstract: The present invention provides an electrical connecting member and an electrical connecting method for achieving electrical connection securely through conductive particles regardless of a slight unevenness of an object matter. An electrical connecting device (10) for electrically connecting an electrical connecting portion (5) of a first object to an electrical connecting portion (3) of a second object comprises an adhesive layer (6) disposed on the first object (4) and constituted of a plurality of conductive particles (7) and a binder (8) containing the plurality of the conductive particles (7) and a paste (9) having a fluidity and disposed on the film-like adhesive layer (6).
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: April 2, 2002
    Assignees: Sony Corporation, Sony Chemicals Corporation
    Inventors: Noriyuki Honda, Yasuhiro Suga
  • Patent number: 6348659
    Abstract: Resilient electrical interconnects are provided which have a non-uniform cross section which achieves an increased range of deflection and a predetermined relationship between compression force and deflection of the interconnect, and between resistance and deflection of the interconnect. A smaller cross sectional area decreases the spring rate, or compression force, of the interconnect during compression. Increased range of deflection and reduced spring rate enables improved compensation for surface irregularities and facilitates mounting of integrated circuit or other devices having large arrays of interconnects. The non-uniform cross section is provided by a single or compound slope, or alternatively a nonlinear curve, from the end of smaller cross-section to the end of larger cross-section.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: February 19, 2002
    Assignee: Thomas & Betts International, Inc.
    Inventors: David Crotzer, David DeDonato, Jonathan Goodwin, Stephen Delprete
  • Patent number: 6343019
    Abstract: An apparatus and method wherein an outer die is mounted on an inner die to form a stack which is mounted on a first surface of a substrate, such as a circuit board, the stack may be mounted filly or partially recessed in a recess which is formed in a first surface of the substrate which is dimensioned for receiving at least a portion of a die therein, and where an aperture may be formed in the recess extending through the substrate to a second side thereof for wire bonding the inner die to the substrate.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: January 29, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Chad A. Cobbley
  • Patent number: 6335492
    Abstract: A tape carrier package (TCP) with improved connecting terminals is disclosed. The TCP includes a base film of non-conductive material which carries a plurality of conductive leads on one surface thereof. A plurality of connecting terminals are deposited on the surface such as to be electrically interconnected to the ends of the conductive leads. Each of the connecting terminals has an acute-angled top portion and includes an inner member of a first material and an outer member of a second material plated on the inner member. The acute-angled top portion of the second material is easily deformable when the connecting terminal is pressed against a corresponding terminal provided on a board to be interconnected to the TCP. Thus, an adequate interconnection area is obtained between the TCP and the circuit provided on the board.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: January 1, 2002
    Assignee: NEC Corporation
    Inventors: Shinji Terasaka, Satoshi Hatazawa
  • Patent number: 6333104
    Abstract: Disclosed herein is an interconnection for electrical connection of two electrical devices. The interconnection comprises a conductive polymer disposed in contact with one or two solderable caps. Together, the solderable cap(s) and the conductive polymer form an interconnection that can be used to connect two electrical devices through the contact pads on the electrical devices. For example, a packaged integrated circuit chip can be connected to a “card” using an array of the interconnections. Since the interconnection has solderable surfaces, the interconnect can be used in place of solder balls in a conventional manufacturing line.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Charles H. Perry, Mark G. Courtney, Lewis s. Goldmann, Gregory B. Martin
  • Patent number: 6329609
    Abstract: An electronic component structure assembly comprising a thin film structure bonded to a multilayer ceramic substrate (MLC) using solder connections and wherein a non-conductive, compliant spacer preferably with a layer of thermoplastic adhesive on each surface thereof is interposed between the underlying MLC carrier and overlying thin film structure. The spacer includes a pattern of through-holes which corresponds to opposing contact pads of the thin film structure and MLC. The contact pads of at least one of the thin film structure or MLC have posts (e.g., metallic) thereon and the posts extend partly into the spacer through-holes whereby the height of the posts are greater than the thickness of the adhesive. The posts of the MLC have solder bumps thereon. After reflow under pressure the thin film structure is electrically and mechanically connected to the MLC and the join method has been found to provide a reliable and cost-effective process. The joined components also have enhanced operating life.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: December 11, 2001
    Assignee: International Business Machines Corporation
    Inventors: Suryanarayana Kaja, Chandrika Prasad, RongQing Yu
  • Patent number: 6330164
    Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: December 11, 2001
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, David V. Pedersen, Benjamin N. Eldridge, Richard S. Roy, Gaetan Mathieu
  • Patent number: 6326680
    Abstract: In manufacturing an encapsulated optocomponent, the optocomponent is embedded in a plastics material. The optocomponent has guide grooves on one of its surfaces in which guide pins are to extend so that the encapsulated optocomponent will obtain an optical interface of standard type. For the encapsulating operation guide pins are placed in a mold cavity in a mold half and the optocomponent is placed in the cavity in the mold, so that the guide pins are engaged in the guide grooves and ar accurately inserted therein. To achieve this effect, a resilient or elastic force such as from plunger is applied to the other side of the optocomponent, so that it is pressed with some force against the guide pins. The cavity in the mold is then closed by placing a second mold half on top after which the encapsulating material can be introduced in the closed cavity in the mold.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: December 4, 2001
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Odd Steijer, Hans-Christer Moll, Paul Eriksen, Jan-Åke Engstrand
  • Patent number: 6327158
    Abstract: An improved integrated circuit device that includes both bond pads and trim pads is disclosed. Electrically conductive, non-wettable and non-corrosive protective caps are formed over each of the trim pads. With this arrangement, the protective caps act as barriers between the trim pads and solder used to form solder bumps when the IC package is mounted onto a substrate. In one embodiment, the protective caps are formed from a material that is easily sputtered, such as titanium. In a method aspect of the invention, the protective caps are applied during wafer level processing before either the solder bumping or trimming operations.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: December 4, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Nikhil Vishwanath Kelkar, Pai-Hsiang Kao
  • Patent number: 6324067
    Abstract: A printed wiring board (PWB) and assembly are described which are suitable for high density mounting of an electronic component and which can provide a thin and light assembly. A recess is formed in one part of a PWB and components are received in this recess. The components are lower than the surface of the PWB. A conductive pad is provided to the bottom of the recess and a connecting terminal and the conductive pad are electrically connected by using a solder ball or a conductive adhesive material. The recess is formed by partially removing one or more layers of plural conductive layers and insulating layers which make up the multilayer PWB.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: November 27, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tousaku Nishiyama
  • Patent number: 6316737
    Abstract: In general, in one aspect, the invention features a connection between a through-hole in a circuit board and a contact region on a component. The contact region has a surface bearing a depression. A continuous solder column has one end of that forms a solder joint with an inner wall of the through-hole and the other end of that forms a solder joint with the contact region.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: November 13, 2001
    Assignee: VLT Corporation
    Inventors: Michael D. Evans, James D. Goss, Jeffrey A. Curhan, Patrizio Vinciarelli
  • Patent number: 6316735
    Abstract: A semiconductor chip mounting board which improves reliability of electrical connection between a semiconductor chip mounted thereupon and a wiring pattern on a printed circuit board on which the semiconductor chip mounting board is mounted at low cost and in an easy manner. The semiconductor chip mounting board mounts a semiconductor chip on one surface of the board and forms a connecting pad electrically connecting with a wiring pattern of a printed circuit board on the other surface of the board. The semiconductor chip mounting board further forms on the other surface of the board a connection reinforcing pad, which is thicker than the connecting pad electrically connecting with the wiring pattern on the printed circuit board.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: November 13, 2001
    Assignee: Ricoh Company, Ltd.
    Inventor: Masahiro Higashiguchi
  • Patent number: 6310285
    Abstract: An EMI countermeasure component is provided relative to an active element, which does not deteriorate a circuit function of the active element, but has a sufficient shielding effect against permeation of electromagnetic waves radiated to the exterior, and further suppresses a malfunction or the like due to mutual interferences between peripheral components or an electromagnetic induction to a signal line. The EMI countermeasure component is made of a composite magnetic body including soft magnetic powder having oxide films on the surfaces thereof and an organic binding agent, and extinguishes undesired high frequency electromagnetic radiation as heat due to its complex permeability.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: October 30, 2001
    Assignee: Tokin Corporation
    Inventors: Mitsuharu Sato, Koji Kamei, Shigeyoshi Yoshida
  • Patent number: 6310781
    Abstract: A connection pin layout for connecting one or more integrated magnetics modules (IMMs) to a printed circuit board (PCB) for reduced electromagnetic interference (EMI) includes grouping and locating the connection pins based on the signals passed through the connection pins and a method of routing traces to the connection pins. The connection pins carrying power between the PCB and the IMMs are located together and on the periphery of the connection pin layout. The traces to the power pins are routed to avoid passing under the data and ground connection pins or crossing the traces to the data and ground connection pins. When multiple IMMS are connected to a PCB, the connection pin layout coordinates the location of connection pins among IMMs and integrates the grouping of the connection pins for multiple IMMs.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: October 30, 2001
    Assignee: Cisco Technology, Inc.
    Inventor: Roger A. Karam
  • Patent number: 6303874
    Abstract: A liquid crystal display module (1) constructed such that a base end portion (20A) of a pin terminal (20) is joined to an input terminal (18) of a liquid crystal panel (10). A front end portion (20B) of the pin terminal (20) is disposed inwardly of the outer peripheral edge of the liquid crystal panel (10). This allows the portion where the pin terminal (20) is soldered to the circuit board (2) to be located at the back of the liquid crystal panel (10). The amount of space used for mounting the liquid crystal display module (1) onto the circuit board (2) can be minimized, that is it can be reduced by an amount based on the size of the liquid crystal panel 10, thereby allowing very efficient use of space.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: October 16, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Eiji Muramatsu
  • Patent number: 6297547
    Abstract: A semiconductor device includes multiple dies, in which a first die and a second die are mounted on a leadframe. The bond pads on the first and second dies are wirebonded to the leadframe. The first die, second die, and leadframe are encapsulated in a package.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: October 2, 2001
    Assignee: Micron Technology Inc.
    Inventor: Salman Akram
  • Patent number: 6288907
    Abstract: A high density integrated circuit module having complex electrical interconnection is described, which includes a plurality of stacked level-one integrated circuit devices, wherein each level-one device includes an integrated circuit die and a plurality of electrical leads extending from the die; and a plurality of non-linear rails adapted to electrically and thermally interconnect selected leads of selected stacked level-one devices within the module, wherein at least some of the plurality of non-linear rail include a lead interconnect portion which is adapted to at most partially surround and receive a selected lead from one of the stacked level-one devices. Other embodiments include TSOP modules having leads reduced in width to allow additional selected non-linear rails to interconnect with select leads in the module. Strain relief for the rail/circuit board substrate connection in harsh environment applications is also provided.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: September 11, 2001
    Assignee: Staktek Group, L.P.
    Inventor: Carmen D. Burns
  • Patent number: 6274823
    Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond. The component carries the contact structures on both sides, the spacing of the structures on the first side being different than that of the second side.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: August 14, 2001
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 6271479
    Abstract: A device for electrical and mechanical connection of an electric high-power component which transmits high-frequency electrical signals to conductors on a circuit board. The component includes horizontally projecting connections which to the are glued to the conductors on the circuit board with an electrically conducting adhesive, of which the adhesion to the foundation is greater than a predetermined value. The component is subject to repeated temperature changes which leads to stresses on the connection between the connections and the conductors. The length of the connections is chosen depending on a predetermined threshold value for the highest acceptable attenuation which the high-frequency electrical signal is subject to when passing through the electrical high-power component via the connections. The contact surface of the connections towards the glued joint can be designed so that it includes a number of cavities, whereby the adhesive achieves a better grip to the connections.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: August 7, 2001
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Christer Olsson
  • Patent number: 6259036
    Abstract: A method for fabricating bumped semiconductor components and electronic assemblies, such as multi chip modules, is provided. The method includes forming semi cured, electrically conductive, elastomeric bumps on electrodes of a semiconductor component (e.g., die, chip scale package), or on electrodes of a mating component (e.g., PCB, MCM substrate). The bumps include an adhesive matrix material and dendritic metal particles. The adhesive matrix material is in a semi cured condition having adhesive qualities for bonding, but with a structural rigidity for supporting the dendritic particles to enable penetration of oxide layers on the electrodes. The semi cured adhesive bumps permit the bumps to be cured without the necessity of externally generated compressive forces.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: July 10, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 6259163
    Abstract: A metal pattern 4 is formed at a rear surface of a substrate 3 at a front surface of which a molded semiconductor chip is mounted, the metal pattern 4 is covered with an insulating film 5 except at its connecting area 4a and a solder ball 6 is bonded to the connecting area 4a. The area of the metal pattern 4 other than the connecting area 4a inclines toward the substrate 3 and gradually becomes thinner toward the outside. Stress, which is applied to the solder ball 6, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks X is reduced and the solder ball which is used to achieve connection with an external substrate is effectively prevented from becoming electrically disconnected.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: July 10, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yoshimi Egawa, Noritaka Anzai
  • Patent number: 6259022
    Abstract: A micromodule is used as a surface-mounted package on a substrate of interconnections. In one embodiment of the invention, barriers to the expansion of solder are formed between contact zones of the micromodule and corresponding contact pads of the substrate. A mechanical stopping device is planned to keep the thickness of the interface of solder. In another embodiment of the invention, contact zones are extended by tongues. A cambering operation enables the formation of the surface-mounting pins.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: July 10, 2001
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Francis Steffen
  • Patent number: 6256200
    Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: July 3, 2001
    Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
  • Patent number: RE37413
    Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: October 16, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gi Bon Cha