Abstract: An assembly of connected circuit boards includes at least one each of a matrix board, an input board and an output board. There are two types of input board, one for hydrophone cable input and one for single-ended (SE) cable input. The matrix board provides for switching any pair of input differential signals to any channel on the output board.

Abstract: A wiring board of the present invention includes a dummy wiring in a semiconductor-chip mount area on which a semiconductor chip is to be mounted. The dummy wiring is arranged in a manner such that all wiring-lines included in the dummy wiring each have a free end within the semiconductor-chip mount area. This prevents a defect due to vaporization and expansion of moisture inside a semiconductor apparatus, with a simple structure and without raising costs.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: A structure has a printed board carried by a metal chassis. A printed board carrying chassis analyzing system, a printed board carrying chassis analyzing method, a printed board carrying chassis structure, and a printed board carrying chassis analyzing program are provided to achieve a screw-fastened arrangement for predicting unnecessary radiation frequencies and for reducing unnecessary radiation. An equivalent circuit model including a printed board power and ground plane pair, a pair of confronting surfaces of a printed board and a chassis, and screw-fastened grounding posts is generated and analyzed to predict unnecessary radiation frequencies and unnecessary radiation reductions and to select a screw-fastened arrangement for reducing unnecessary radiation.

Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.

Abstract: A contact bank, which can be terminated, or is terminated, at least one terminal module serving for signal communication and being adapted to allow telecommunications lines to be connected therewith, or at least one supplementary module, of a telecommunications distribution point, which is connected to a terminal module, whereby the contact bank further is mountable or mounted in the telecommunications distribution point, includes: (a) a plurality of tapping contacts directly and permanently electrically connected to the contacts of the module in the terminated condition of said contact bank; (b) a smaller number of outlet contacts than of tapping contacts; (c) a plurality of remote-controllable switches for selectively electrically connecting said outlet contacts to said tapping contacts; and (d) a control device for controlling the plurality of switches.

Abstract: An integrated circuit packaging system comprising: forming a substrate including; patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.

Abstract: The invention relates to an electric insulating body (2) provided with a conductor pattern (1) and an electronic device (10) comprising such a body (2) and at least one electronic element (30). According to the invention, the body (2) has first and second faces (2A, 2B) in between of which an angle of less than 180 degrees is defined, wherein the conductor pattern (1) of the body (2) extends over both faces (2A, 2B), which body (2) carries both the conductor pattern (1) and the electronic element (30). The conductor pattern (1) comprises strip-shaped regions (1A) and regions (1B) with a larger width than the strip-shaped regions (1A), which regions (1B) are suitable for electrically contacting the electronic element (30). The electronic element (30) is, for example, a camera. The device (10) with such a camera is particularly suitable for use in a mobile communication apparatus.

Abstract: A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. A pair of differential signal vias in a circuit board are surrounded by an opening that is formed within a ground plane disposed on another layer of the circuit board. The vias are connected to traces on the circuit board by way of an exit structure that includes two flag portions and associated angled portions that connect the flag portions to circuit board traces. In an alternate embodiment, the circuit board traces that leave the differential signal vias are disposed in one layer of the circuit board above a wide ground strip disposed on another layer of the circuit board.

Abstract: There is provided an LED lamp unit comprising an LED lamp, a protective component for an LED lighting circuit, a circuit section and a case part, characterized in that the circuit section has a metal plate which is embedded in the case part with its surface partially exposed, a lead of the LED lamp is electrically connected to the exposed surface of the metal plate, and the protective component for the LED lighting circuit is connected to the metal plate at an opposite side to a side where the lead of the LED lamp is connected.

Abstract: Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrate or on at least one intervening release layer and patterned to form metal traces. A stressable material, exhibiting an at least partially tensile stress state, may be deposited on the metal traces in a localized region. A portion of the substrate or a portion of the intervening release layer underneath the metal traces may be removed by etching, causing the metal traces to curl upward resulting in the spring contacts. The spring contacts may be used as compliant electrical contacts for electrical devices, such as integrated circuits or carrier substrates. The compliant electrical contacts may also be used for probe cards to test other electrical devices.

Abstract: Provided is a system adopting a differential signaling system including a low frequency signaling line arranged to be adjacent to a pair of differential signaling lines in parallel to each other, for transmitting a signal having a frequency which is smaller than a frequency of a signal to be transmitted through the pair of differential signaling lines, in which a transmission end of the low frequency signaling line is connected to a ground pattern through a first capacitive element, and a reception end of the low frequency signaling line is connected to the ground pattern through a second capacitive element. Thus, it is possible to provide, easily and at a low cost, a differential signaling system in which a common mode noise is eliminated without increasing the number of pins.

Abstract: Disclosed is a printed wiring board comprising an insulating layer having a rectangular flat shape and provided with fibers in the layer, the direction of the fiber in the layer being almost parallel to any side of the rectangle, a reference potential layer disposed on one surface side of the insulating layer, a plurality of wiring patterns for signal transmission disposed on the other surface side of the insulating layer so as to have nearly similar angles respectively with respect to the direction of the fiber in the insulating layer, and a pad portion to mount a semiconductor device, disposed on the other surface side of the insulating layer to conduct the plurality of wiring patterns.

Abstract: A circuit board having at least one through hole and including a first and a second wiring layer, an insulation layer, and a conductive through hole structure is provided. The insulation layer is disposed between the first and second wiring layers. The through hole located in the insulation layer extends from the first wiring layer to the second wiring layer. The conductive through hole structure includes at least one first pad, at least one second pad, and a conductive pattern. The first pad partially covers the edge of one opening of the through hole and connects the first wiring layer. The second pad partially covers the edge of the other opening of the through hole and connects the second wiring layer. The conductive pattern connects the first and second pads and partially covers the sidewall of the through hole.

Abstract: A method of connecting signal lines between an integrated circuit (IC) die and a carrier or external circuit, and corresponding apparatus. Techniques for adjusting magnetic coupling between terminated signal lines include splitting a return path for termination current and disposing one nearby on either side of the terminated signal line, creating two small termination current loops conducting in opposite directions; using separate terminating impedances, which may be unequal, to control current in each of the loops; and arranging major axes of the termination current loops for a signal to be perpendicular to those of the isolation-target signal. Capacitive coupling adjustments include routing ground potential termination current return connections nearby the signal connection to shield it from the isolated signal line, using dual overlapping connections to shield each return path, and adjusting dielectric material proximity to the signal paths.

Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41.

Abstract: A printed circuit board includes multiple layers on which electrically conductive traces reside, where at least two of the electrically conductive traces each has a first portion formed on one layer of the printed circuit board and a second portion formed on another layer of the printed circuit board. The printed circuit board also includes a thru-hole via that includes at least two electrically conductive portions electrically isolated from each other, such that each of the electrically conductive portions connects electrically to both the first and second portions of a corresponding one of the electrically conductive traces.

Abstract: A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. A pair of differential signal vias in a circuit board are surrounded by an opening that is formed within a ground plane disposed on another layer of the circuit board. The vias are connected to traces on the circuit board by way of an exit structure that includes two flag portions and associated angled portions that connect the flag portions to circuit board traces. In an alternate embodiment, the circuit board traces that leave the differential signal vias are disposed in one layer of the circuit board above a wide ground strip disposed on another layer of the circuit board.

Abstract: A flexible circuit comprises a flexible substrate having first and second opposing surfaces. The flexible substrate can include multiple layers. A plurality of electrical traces can be mounted on either or both surfaces of the flexible substrate. A plurality of electrical components can also be mounted on either or both surfaces of the flexible substrate. A plurality of tooling cutouts is recessed in the sides of the flexible circuit. The tooling cutouts can have various shapes, such as, but not limited to, semi-circular, multiple straight edges, a single or multiple curved edges, etc. The cutouts are used to position and hold the flexible circuit in at least one other device.

Abstract: A wiring board includes: an insulating base; a plurality of conductive wirings; and bumps formed on the conductive wirings, respectively. The conductive wirings can be connected with electrode pads of a semiconductor element via the bumps. The conductive wirings include a connection terminal portion at an end portion opposite to the other end portion where the bumps are formed, and at the connection terminal portion, the conductive wirings can be connected with an external component. The conductive wirings include first conductive wirings and second conductive wirings, on which the bumps are formed respectively at a semiconductor element mounting region. The first conductive wirings extend from the bumps to the connection terminal portion. The second conductive wirings extend beyond the semiconductor element mounting region from the bumps but do not reach the connection terminal portion.

Abstract: Some embodiments of the invention effectively shield signal traces on a substrate without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention provide improved power delivery without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention are described in the claims.

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract: A system and method for minimizing the effects of non-uniform dielectric properties includes forming traces on printed circuit boards (PCB) where the fibers within the printed circuit boards are non-rectangular with respect to the rectangular edges of the circuit board. The orientation of the traces with respect to the fibers substantially minimizes the effects of non-uniform dielectric properties of the PCB.

Abstract: A PCB is provided that is suitable for use in applications where EMI control is of interest. The PCB includes circuitry that communicates with an edge connector having edge traces located on its surface. Additionally, embedded traces are disposed within the dielectric material of the PCB, and each embedded trace electrically connects an edge trace with a corresponding median trace located on a surface of the PCB. An embedded ground layer substantially disposed within the dielectric material defines an area within the dielectric material through which the embedded traces pass. Finally, one or more vias are provided that extend through the dielectric material of the PCB and are filled with a conductive material. The vias are electrically connected to the embedded ground layer and configured to electrically communicate with an associated module. In this way, a structure is implemented that facilitates control of electromagnetic radiation emitted by the PCB circuitry.

Abstract: An extendable enclosure for circuit cards provides the capability for a customer to purchase a low cost system up-front, but still allow for growth.

Abstract: A conducting device for a display device is disclosed. It comprises one or more non-conducting base lines formed in predetermined locations on a substrate layer, and one or more conducting line structures formed over the non-conducting base lines on the substrate layer, wherein the non-conducting base lines raise the conducting line structures in height for increasing a cross-sectional area thereof for reducing a resistance of the conducting line structures.

Abstract: A rack has a plurality of LEDs arranged on the front surface thereof correspondingly to respective units. The rack is provided with an LED lighting circuit which lights these LEDs, on the back of a display section and an input section. The LED lighting circuit has an LED lighting control section and a memory. The LED lighting control section acquires correspondence relation information indicating correspondence between servers and apparatuses from the input section, and stores the information in the memory. When a server is selected, the LED lighting circuit lights some of the plurality of LEDs based on the correspondence relation information stored in the memory.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: A circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated therefrom by a common interim dielectric layer. An electrical assembly including the circuitized substrate as part thereof and a method of making the circuitized substrate are also included. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.

Abstract: A flexible substrate comprises a film, a first insulating resin layer on a front face of the film, a second insulating resin layer on a rear face of the film, a front-sided wiring pattern embedded in the first insulating resin layer, and a rear-sided wiring pattern embedded in the second insulating resin layer. A surface of the front-sided wiring pattern is flush with a surface of the first insulating resin layer, and a surface of the rear-sided wiring pattern is flush with a surface of the second insulating resin layer. A part of at least one of the front-sided wiring pattern and the rear-sided wiring pattern is dented toward a part of the other of the at least one of the front-sided wiring pattern and the rear-sided wiring pattern such that a portion of the front-sided wiring pattern and a portion of the rear-sided wiring pattern are jointed to each other to form a junction.

Abstract: A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

Abstract: An apparatus having n-number of working cross-connects for cross-connecting an n-bit input signals arriving from a plurality of input paths on a per-bit basis; n-number of first logic circuits for calculating the exclusive-ORs of each said n-bit and applying outputs to a standby cross-connect for providing outputs; n-number of second logic circuits for calculating the exclusive-ORs of said output signals from each of said working cross-connects and from the single standby cross-connect; and third logic circuits for selecting output signals of said working cross-connects and outputs of the second logic circuits. The apparatus detects the occurrence of an abnormality in working cross-connects by monitoring the outputs of the second logic circuits, identifies the faulty cross-connect by successively turning off one of the n-inputs to the first and second logic circuits, and select outputs from the second logic circuits instead of from the faulty cross-connect by using the third logic circuits.

Abstract: A high-frequency circuit comprises a substrate having an electronic component on an obverse side thereof, a first ground pattern formed on almost an entire reverse side of the substrate, a microstrip line formed on the obverse side of the substrate, and a bias line connected to the electronic component on the obverse side of the substrate and formed continuously on the obverse side and the reverse side of the substrate so as to cross the microstrip line on the reverse side of the substrate in plan view so as to supply a bias voltage to the electronic component, wherein the first ground pattern is formed so as to circumvent the bias line formed on the reverse side of the substrate, a portion of the first ground pattern that circumvents the bias line on the reverse side of the substrate is continuously formed on the obverse side of the substrate as a second ground pattern so as to divide the microstrip line in two parts, and a chip jumper is arranged to bridge the two divided parts of the microstrip line over t

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: An electronic assembly is described, having a substrate and contacts on the substrate which are spaced and arranged in a manner that allows for a more dense arrangement of contacts but still allows for routing of traces between the contacts.

Abstract: According to one embodiment, a printed circuit board (PCB) is disclosed. The PCB includes a first functional unit block (FUB) and differential traces coupled to the first FUB. The first FUB transmits high-speed serial data. The differential traces carry the high-speed serial data from the first FUB. In addition, the differential traces crossover on the same layer of the PCB while maintaining a constant impedance.

Abstract: An interconnect architecture in which a substrate such as a printed circuit board includes multiple conductive layers separated by one or more interposed insulating layers, the conductive layers being adapted to receive a high density array of interconnect elements such as a ball grid array (BGA). In certain preferred embodiments, a printed circuit board may provide a very low resistance interconnect forming the drain and source terminals of a lateral power MOSFET device incorporating a high density array of alternating source and drain interconnect elements, such as a BGA. In such embodiments, source and drain currents may be routed on different conductive layers separated by one or more interposed insulating layers. The upper conductive layer may include laterally non-conductive regions accommodating conductive columns that are connected to the lower conductive layer.

Abstract: An improved method for reducing timing skew for signals, for example clock signals, that propagate along a circuit board, for example, a memory module, is disclosed. At least one signal trace of a plurality of traces provided on the printed circuit board (PCB) is routed in both a horizontal and a vertical direction such that its path length is substantially the same as the path length of another of said plurality of traces.

Abstract: A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

Abstract: In one embodiment, a dummy via is created in a circuit board. The dummy via is positioned and coupled to a portion of a transmission line. This portion of the transmission line is further coupled to a signal lead of a connector, which creates additional capacitance to lower the impedance of the connector.

Abstract: A circuit board includes a substrate and electrical contacts to mate with a slot connector. The contacts include a first set of contacts that are associated with the communication of power and second set of contacts that are associated with the communication of signals and are not used to communicate power. Adjacent contacts of the first set have a first spacing, and adjacent contacts of the second set have a second spacing different from the first spacing. The circuit board has a retention profile to engage a retention mechanism of the slot connector. A housing of the slot connector may be made from a material that has a thermal conductivity of at least 0.27 W/m·K, and the slot connector housing may include fins that are formed on the slot connector to conduct heat away from circuitry of the circuit board.

Abstract: According to one embodiment, a printed circuit board (PCB) is disclosed. The PCB includes a first functional unit block (FUB) and differential traces coupled to the first FUB. The first FUB transmits high-speed serial data. The differential traces carry the high-speed serial data from the first FUB. In addition, the differential traces crossover on the same layer of the PCB while maintaining a constant impedance.

Abstract: A microelectronic device includes a microelectronic die having an interfacial metal layer deposited over an active surface thereof to perform a signal distribution function within the device. The microelectronic die is fixed within a package core to form a die/core assembly. One or more metallization layers may then be built up over the die/core assembly as part of a packaging scheme. The interfacial metal layer can be applied either before or after the die is fixed within the package core. In one approach, the interfacial layer is applied during wafer-level processing.

Abstract: A technique has been developed whereby crosstalk induced in a first electrical connection by current flow at an adjacent second electrical connection is at least partially cancelled by an opposing crosstalk signal induced at an inductive coupling between electrical traces extending from or toward the first and second electrical connections, respectively. Crosstalk cancellation is provided by orienting the electrical traces such that current flow through the second electrical connection and respective electrical trace induces an opposing crosstalk signal at the inductive coupling. In some configurations, an inductive coupling between electrical traces includes essentially parallel portions of the traces and an aperture in a voltage plane. In some configurations, cancellation of crosstalk induced by multiple adjacent electrical connection is provided. Crosstalk inducing electrical connections include pins, solder bumps, leads, wires, edge connectors, etc.

Abstract: An LED lamp apparatus comprises LED, a circuit member, and a case member. The case member has an LED seat for holding the LED. The circuit member has metal plates embedded in the case member. The metal plates have LED connection members exposed from the case member. The LED connection members have been resistance welded respectively to leads of the LED.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Abstract: A terminal body for use in combination with a circuitboard having edge conductor pads and being formed from a stamped metal blank so as to provide a first main longitudinally extending spring contact which is curved back on itself and inwardly toward the center of the terminal and a pair of stabilizing contacts which oppose and straddle the main contact. All of the contacts are sufficiently resilient to permit the circuitboard of thickness T to be inserted between them, the stabilizing contacts ensuring a firm grip on the circuitboard and non-intermittent contact between the main terminal contact and the circuitboard pad.

Abstract: An interconnected mesh plane system includes at least a pair of adjacent metal layers separated by dielectric, each layer having a plurality of spaced power, ground, and signal conductors extending in the same direction, with the conductors of one layer of the pair transverse to the conductors of the other layer, and with conductors of one layer connected to corresponding conductors of the other layer. The width of at least one signal conductor is increased to reduce signal loss, and the width of spaces between such a signal conductor and adjacent power and/or ground conductors is increased to provide a predetermined desired characteristic impedance of a transmission line that includes such a signal conductor.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.