Abstract: A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.

Abstract: An approach to form a semiconductor structure with a multiple layer phase change material stack and four electrodes that functions as an integrated switch device. The semiconductor structure includes a sidewall spacer that is on two opposing sides of the multiple layer phase change material stack contacting an edge of each layer of the multiple layer phase change material stack. The semiconductor structure includes a pair of a first type of electrode, where each of the pair of the first type of electrode abuts each of the sidewall spacers on the two opposing sides of the multiple layer phase change material stack. A pair of a second type of electrode, where each of the second type of electrode abuts each of two other opposing sides of the multiple layer phase change material stack and contacts a heater material on outside portions of the multiple layer phase change material stack.

Abstract: A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.

Abstract: The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.

Abstract: In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers.

Abstract: Embodiments of the present invention provide a computer system, a voltage resistance controlling apparatus, and a method that comprises at least two electrodes on proximal endpoints; a first layer disposed on the at least two electrodes, wherein the first layer is a made of a metal-oxide; a second layer disposed on the second layer, wherein the second first layer is made of an electrically conductive metal-oxide; a forming contact disposed on the second layer, wherein a combination of the forming contact disposed on the first layer disposed on the second layer operatively connects the at least two electrodes; and a computer system operatively connected to the forming contact, wherein the computer system is configured to apply a predetermined voltage to the first layer and the second layer respectively and display an overall resistance increase using a user interface.

Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

Abstract: Provided are processing and an electronic device including the same. The processing apparatus includes a bit cell line comprising bit cells connected in series, a mirror circuit unit configured to generate a mirror current by replicating a current flowing through the bit cell line at a ratio, a charge charging unit configured to charge a voltage corresponding to the mirror current as the mirror current replicated by the mirror circuit unit is applied, and a voltage measuring unit configured to output a value corresponding to a multiply-accumulate (MAC) operation of weights and inputs applied to the bit cell line, based on the voltage charged by the charge charging unit.

Abstract: Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.

Abstract: A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

Abstract: A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: The generation of “fingerprints”, also called challenge-response pairs (CRPs) of Physically Unclonable Functions (PUFs), can often stress electronic components, leaving behind traces that can be exploited by crypto-analysts. A non-intrusive method to generate CRPs based on Resistive RAMs may instead be used, which does not disturb the memory cells. The injection of small electric currents (magnitude of nanoAmperes) in each cell causes the resistance of each cell to drop abruptly by several orders of magnitudes through the formation of temporary conductive paths in each cell. A repeated injection of currents into the same cell, results in an almost identical effect in resistance drop for a single cell. However, due to the small physical variations which occur during manufacturing, the cells are significantly different from each other, in such a way that a group of cells can be used as a basis for PUF authentication.

Abstract: A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.

Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: A method of programming a nonvolatile memory device including a plurality of memory cells is provided. Each of the plurality of memory cells includes a reversible resistance device. A target memory cell is selected from among the plurality of memory cells. A target resistance state for the reversible resistance device of the target memory cell is determined. A resistance state of the reversible resistance device of the target memory cell is read. The read resistance state is compared with the target resistance state. One of a positive program operation and a negative program operation is performed for the reversible resistance device of the target memory cell when the read resistance state is different from the target resistance state.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.

Abstract: A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be formed over a conductive substrate by converting at least a portion of the conductive substrate to CEM.

Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.

Abstract: A resistive memory device is provided. The resistive memory device includes a bitline, a source line, a memory cell electrically connected to the bitline and the source line by a first switch, a first transistor electrically connected to the bitline, a second transistor electrically connected to the source line, a gate voltage generator configured to generate a first gate voltage that is provided to a gate electrode of the first transistor, and configured to generate a second gate voltage that is provided to a gate electrode of the second transistor and a second switch that provides the first and second gate voltages to the gate electrodes of the first and second transistors.

Abstract: A method of erasing vertical NAND strings from a source side of the vertical NAND strings includes applying a relatively high erase voltage to a source line, applying a relatively low voltage or 0 V to bit lines, applying a first drain-select-level voltage that is less than the erase voltage to one of the first drain-select-level electrically conductive layers, and applying a second drain-select-level voltage that is greater than the first drain-select-level voltage and not greater than the erase voltage to one of the second drain-select-level electrically conductive layers.

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.

Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

Abstract: A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.

Abstract: A memory device includes a cell array including a memory cell that includes a variable resistance element, a reference resistor configured to provide a resistance varying according to an adjustment code, and a read circuit configured to read data that is stored in the memory cell, based on a resistance of the variable resistance element and the resistance of the reference resistor. The memory device further includes a reference adjustment circuit configured to obtain a first calibration code corresponding to a temperature variation, and a second calibration code corresponding to a process variation, and perform an arithmetic operation on the obtained first calibration code and the obtained second calibration code, to obtain the adjustment code.

Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

Abstract: A Magnetoresistive Random Access Memory (MRAM) device is tested using a high repetition test that detects one or more low-likelihood failures, such as a failure to properly switch between a high or low resistive state. A series of write and read operations are performed for a large number of test cycles at high frequency. A first tier measurement is used to determine if a switching failure occurred, e.g. by comparing the read signal to target level(s) after each operation. When a switching failure event is detected, a second tier measurement is used to measure and store switching performance parameters, for example, the value of the read signal, while the MRAM device is in a failure state. The high frequency testing may be paused during the second tier measurements. Additional performance parameters may be measured during the second tier measurements.

Abstract: A magnetic memory device includes: a memory cell array including a plurality of lines arranged parallel to one another at predetermined intervals and extending in one direction, and a plurality of memory cells connected to the plurality of lines and arranged in a matrix along an extending direction of the plurality of lines and along an arrangement direction of the plurality of lines, each of the plurality of memory cells including a magnetoresistance effect element; a selection circuit connected to the plurality of lines and configured to select non-adjacent lines that are not adjacent to one another, from the plurality of lines; and a controller connected to the selection circuit and configured to cause the selection circuit to select the non-adjacent lines and allow a write current to flow through the non-adjacent lines simultaneously in writing data on the memory cell array.

Abstract: Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the th

Abstract: Provided is a phase-change memory (PCM) module including a PCM device including a bit line and a word line, a memory controller configured to output a command related to an operation of the PCM device, and an interference mitigation part located between the memory controller and the PCM device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.

Abstract: The present disclosure includes apparatuses, methods, and systems for predicting and compensating for degradation of memory cells. An embodiment includes a memory having a group of memory cells, and circuitry configured to, upon a quantity of sense operations performed on the group of memory cells meeting or exceeding a threshold quantity, perform a sense operation on the group of memory cells using a positive sensing voltage and perform a sense operation on the group of memory cells using a negative sensing voltage, and perform an operation to program the memory cells of the group determined to be in a reset data state by both of the sense operations to the reset data state.

Abstract: A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.

Abstract: A resistive random-access memory (ReRAM) includes a hybrid memory cell. The hybrid memory cell includes: (a) a left resistance-switching device comprising a first terminal and a second terminal, (b) a right resistance-switching device comprising a first terminal and a second terminal, wherein the first terminal of the right resistance-switching device is connected to the first terminal of the left-resistive switching device at an internal node, and (c) a transistor comprising a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of the transistor is connected to the left resistance-switching device and the right resistance-switching device at the internal node.

Abstract: A nonvolatile memory device includes: a memory cell array in which a plurality of memory cells are arranged at intersections between a plurality of word-lines and a plurality of bit-lines; and a word-line select circuit configured to, in response to a first global word-line select signal, start reading a target memory cell connected to a target word-line and provide a reading result of the target memory cell to a sensing line through at least one adjacent word-line that is adjacent to and coupled to the target word-line.

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells.

Abstract: A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: An operating method for improving the performance of a selector device is provided, including: determining and applying a direct current (DC) or alternating current (AC) operating voltage and a limit current of the selector device, so that the selector device circulates until a off-state resistance is reduced; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is reduced to a minimum value; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased to a maximum value; and adjusting the operating voltage and the limit current, and performing DC or AC operation pulsed operation on a selector.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

Abstract: A nano-oscillator device includes a switching element configured to be switched to an ON state at a threshold voltage or above and switched to an OFF state below a holding voltage; and a load element connected to the switching element in series. In the nano-oscillator device, vibration characteristics are implemented by using a switching element and a load element connected thereto in series. Also, the oscillation frequency of the output waveform of the oscillator may be adjusted in real time according to a gate voltage by using a field effect transistor serving as a load element. Using a synchronization characteristic in which the oscillation frequency and phase are locked with respect to an external input, it is possible to implement a computing system based on a network in which a plurality of oscillator devices are coupled.

Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

Abstract: A neural network circuit includes: a storage portion that includes memristors; D/A converters; drive amplifiers; I/V conversion amplifiers; A/D converters; and offset correctors. The offset corrector includes a first latch circuit, a second latch circuit, a subtractor that subtracts latch data, and a controller. In performing a bias setting operation, the controller controls a bias application amplifier to output the bias voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output a reference voltage, and also cause the first latch circuit to latch the output data. In performing a normal operation, the controller controls the bias application amplifier to output the reference voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output the signal voltage, and also cause the second latch circuit to latch the output data.

Abstract: A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.