Diodes Patents (Class 365/175)
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Patent number: 8154908Abstract: A nonvolatile semiconductor storage device includes: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires.Type: GrantFiled: February 10, 2011Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Katsuaki Isobe, Hideo Mukai
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Patent number: 8144494Abstract: A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state.Type: GrantFiled: January 10, 2011Date of Patent: March 27, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Satoru Takase
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Patent number: 8139398Abstract: A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a composite compound having at least two types of cation elements, at least one type of the cation element is a transition element having a ādā orbit in which electrons have been incompletely filled, and the shortest distance between the adjacent cation elements is 0.32 nm or less.Type: GrantFiled: March 21, 2011Date of Patent: March 20, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Kubo, Takahiro Hirai, Shinya Aoki, Robin Carter, Chikayoshi Kamata
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Patent number: 8134860Abstract: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.Type: GrantFiled: December 16, 2010Date of Patent: March 13, 2012Assignee: Intel CorporationInventor: Guy Wicker
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Publication number: 20120051132Abstract: Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Gurtej S. Sandhu, Bhaskar Srinivasan
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Publication number: 20120044757Abstract: Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for those memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal of a first diode and to the N-terminal of a second diode. At least one of the diodes can be a polysilicon diode fabricated using standard CMOS processes with P+ and N+ implants in two ends. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon substrate as a program selector. The memory cells can be used to construct a two-dimensional memory array with the N-terminals of the first diodes and the P-terminals of the second diodes in a row connected as wordline(s) and the resistive elements in a column connected as a bitline.Type: ApplicationFiled: February 14, 2011Publication date: February 23, 2012Inventor: Shine C. Chung
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Patent number: 8120951Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.Type: GrantFiled: May 22, 2008Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8116109Abstract: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: GrantFiled: March 29, 2011Date of Patent: February 14, 2012Inventors: Daniel R. Shepard, Thomas A. Langdo, Arthur J. Pitera
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Patent number: 8102694Abstract: A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.Type: GrantFiled: June 25, 2007Date of Patent: January 24, 2012Assignee: SanDisk 3D LLCInventors: S. Brad Herner, Mark H. Clark, Tanmay Kumar
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Patent number: 8102699Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.Type: GrantFiled: December 13, 2010Date of Patent: January 24, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Haruki Toda
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Patent number: 8098521Abstract: A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.Type: GrantFiled: March 31, 2005Date of Patent: January 17, 2012Assignee: Spansion LLCInventors: Michael A. VanBuskirk, Colin S. Bill, Zhida Lan, Tzu-Ning Fang
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Patent number: 8094477Abstract: A semiconductor storage device includes a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series, and a control circuit selectively driving the first and second wirings. The control circuit applies a first voltage to the selected first wiring and applies a second voltage to the selected second wiring to apply a certain potential difference to a selected memory cell positioned at a intersection between the selected first and second wirings, and brings at least one of nonselected first wirings into a floating state.Type: GrantFiled: July 28, 2009Date of Patent: January 10, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Maejima
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Patent number: 8089801Abstract: The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be electrically charged or discharged by current flowing through the gated p-n diode. An array of memory cells formed by the disclosed semiconductor memory device is proposed. Furthermore, an operating method and a method for producing the disclosed semiconductor memory device and array are described.Type: GrantFiled: October 9, 2008Date of Patent: January 3, 2012Assignee: Suzhou Oriental Semiconductor Co., Ltd.Inventors: Peng-Fei Wang, Yi Gong
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Patent number: 8077495Abstract: A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.Type: GrantFiled: December 5, 2006Date of Patent: December 13, 2011Assignee: Spansion LLCInventors: Swaroop Kaza, Sameer Haddad
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Patent number: 8072793Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Each memory cell comprises a diode and a plurality of memory elements each comprising one or more metal-oxygen compounds, the diode and the plurality of memory elements arranged in electrical series along a current path between a corresponding word line and a corresponding bit line.Type: GrantFiled: September 4, 2008Date of Patent: December 6, 2011Assignee: Macronix International Co., Ltd.Inventors: Ming-Daou Lee, Erh-Kun Lai, Kuang Yeu Hsieh
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Patent number: 8072795Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.Type: GrantFiled: October 28, 2009Date of Patent: December 6, 2011Assignee: Intermolecular, Inc.Inventors: Yun Wang, Prashant Phatak, Tony Chiang
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Patent number: 8072801Abstract: A method of forming a diode comprises the steps of forming an extraction region of a first conductivity type, forming an active region of a second conductivity type that is opposite the first conductivity type, and forming an exclusion region of the second conductivity type to be adjacent the active region. The active region is formed to be adjacent to the extraction region and along a reverse bias path of the extraction region and the exclusion region does not resupply minority carriers while removing majority carriers. At least one of the steps of forming the exclusion region and forming the extraction region includes the additional step of forming a barrier that substantially reduces the flow of the carriers that flow toward the active region, but does not rely on a diffusion length of the carriers to block the carriers.Type: GrantFiled: May 27, 2010Date of Patent: December 6, 2011Assignee: EPIR Technologies, Inc.Inventors: Silviu Velicu, Christoph H. Grein, Sivalingam Sivananthan
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Patent number: 8072791Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.Type: GrantFiled: June 25, 2007Date of Patent: December 6, 2011Assignee: SanDisk 3D LLCInventors: S. Brad Herner, Mark H. Clark, Tanmay Kumar
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Publication number: 20110292723Abstract: The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state.Type: ApplicationFiled: July 14, 2010Publication date: December 1, 2011Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMYInventors: Deyuan Xiao, Xiaolu Huang, Jing Chen, Xi Wang
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Patent number: 8064246Abstract: A structure includes an electrically conductive material possessing spontaneous magnetization (āfree magnetā) not in contact with an electrically resistive material possessing spontaneous magnetization (āpinned magnetā), and a spacer having free electrons to transfer spin between the electrically resistive material and the electrically conductive material. During operation, an existing direction of magnetization of the free magnet is changed to a new direction of magnetization, by a spin current generated by transfer of heat between at least the spacer and the pinned magnet. Thereafter, the new direction of magnetization of the free magnet is sensed. Many such structures are fabricated to have an easy axis of magnetic anisotropy in the free magnet, to implement memories that write data by transferring heat. Several such structures are fabricated to have an easy plane of magnetic anisotropy in the free magnet, to implement oscillators that generate an oscillating signal, on transfer of heat.Type: GrantFiled: December 8, 2010Date of Patent: November 22, 2011Inventor: John Casimir Slonczewski
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Publication number: 20110273930Abstract: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.Type: ApplicationFiled: October 14, 2010Publication date: November 10, 2011Applicant: Macronix International Co., Ltd.Inventors: Kuo-Pin Chang, Hang-Ting Lue
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Patent number: 8054667Abstract: A multilevel one-time programmable memory device includes a plurality of memory cells, wherein each of the plurality of memory cells includes: a first electrode to which a first voltage is applied, a second electrode to which a second voltage is applied and a plurality of fuse lines performing a fusing operation according to a voltage difference between the first electrode and the second electrode. The plurality of fuse lines are connected to each other between the first electrode and the second electrode. In addition, at least one of the first electrode and the second electrode is formed such that the first electrode and the second electrode have different valid line lengths from each other therebetween so that the plurality of fuse lines have different resistances from each other.Type: GrantFiled: December 9, 2009Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-ki Min, Hoon-sang Oh
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Publication number: 20110267880Abstract: A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Steven SWEI, David B. Scott
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Patent number: 8050079Abstract: A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit.Type: GrantFiled: October 13, 2009Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Song, Ho-Jung Kim, Sang-Beom Kang
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Patent number: 8036014Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a fixed sequence of voltage pulses across the memory cell of increasing pulse height to change the resistance state from the lower resistance state to the higher resistance state. The fixed sequence of voltage pulses cause increasing current through the phase change memory element until change to the higher resistance state occurs, and after the change the voltage pulses in the fixed sequence causing a voltage across the phase change memory element less than the threshold voltage.Type: GrantFiled: November 6, 2008Date of Patent: October 11, 2011Assignees: Macronix International Co., Ltd., International Business Machines CorporationInventors: Ming-Hsiu Lee, Matthew J. Breitwisch, Chung Hon Lam
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Patent number: 8027190Abstract: A command processing circuit for generating internal command signals corresponding to a plurality of unit internal command signals sequentially applied during a plurality of command cycles, the command processing circuit includes a first command latching unit configured to latch a first unit internal command signal applied in a first command cycle and a second command latching unit configured to latch a second unit internal command signal in response to the first unit internal command signal latched in the first command latching unit in a second command cycle after the first command cycle, and output an internal command signal corresponding to the first unit internal command signal and the second unit internal command signal.Type: GrantFiled: June 23, 2009Date of Patent: September 27, 2011Assignee: Hynix Semiconductor Inc.Inventor: Yong-Bok An
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Patent number: 8023312Abstract: A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.Type: GrantFiled: November 5, 2007Date of Patent: September 20, 2011Assignee: Sharp Kabushiki KaishaInventors: Shinobu Yamazaki, Yasunari Hosoi, Nobuyoshi Awaya, Shinichi Sato, Kenichi Tanaka
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Resistance-change random access memory device including memory cells connected to discharge elements
Patent number: 8023320Abstract: A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.Type: GrantFiled: November 13, 2009Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-jin Kim, Kwang-ho Kim, Young-kug Moon, Byung-gil Choi -
Publication number: 20110222337Abstract: Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.Type: ApplicationFiled: December 29, 2009Publication date: September 15, 2011Applicant: University of Florida Research Foundation, Inc.Inventors: Jerry G. Fossum, Zhichao Lu
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Patent number: 8004876Abstract: A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.Type: GrantFiled: August 30, 2002Date of Patent: August 23, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gregory S. Snider, Philip J. Kuekes, R. Stanley Williams
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Patent number: 8004873Abstract: A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively.Type: GrantFiled: February 20, 2009Date of Patent: August 23, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Haruki Toda
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Patent number: 7995384Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.Type: GrantFiled: August 15, 2008Date of Patent: August 9, 2011Assignee: Macronix International Co., Ltd.Inventors: Tien-Fan Ou, Wen-Jer Tsai, Jyun-Siang Huang
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Patent number: 7995374Abstract: A memory cell comprises a variable resistance film; a first conductive film having one surface contacted with one surface of the variable resistance film; and a second conductive film having one surface contacted with another surface of the variable resistance film. A width of the first conductive film or the second conductive film in a direction orthogonal to a direction that a current flows in the first conductive film or the second conductive film is smaller than a width of the variable resistance film in a direction orthogonal to a direction that a current flows in the variable resistance film. The width of the first conductive film and the second conductive film is smaller than a width of the first line and the second line in a direction orthogonal to a direction that a current flows in the first line and the second line.Type: GrantFiled: November 13, 2009Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Komura, Mitsuru Sato, Kenichi Murooka, Motoya Kishida
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Patent number: 7995369Abstract: This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.Type: GrantFiled: December 11, 2008Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Minami, Ryo Fukuda, Takeshi Hamamoto
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Patent number: 7995371Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.Type: GrantFiled: July 26, 2007Date of Patent: August 9, 2011Inventors: Darrell Rinerson, Julie Casperson Brewer, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, Lawrence Schloss
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Patent number: 7995372Abstract: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively.Type: GrantFiled: March 13, 2009Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Haruki Toda
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Patent number: 7994536Abstract: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.Type: GrantFiled: February 19, 2008Date of Patent: August 9, 2011Assignee: Qimonda AGInventors: Rolf Weis, Thomas Happ
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Patent number: 7990754Abstract: A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2?V3<V5 and V5<V4?V1 are satisfied and (V1?V4)<VF or (V3?V2)<VF is satisfied when V5=(V1+V2)/2 is a fifth voltage V5.Type: GrantFiled: May 15, 2008Date of Patent: August 2, 2011Assignee: Panasonic CorporationInventors: Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii
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Patent number: 7989791Abstract: Provided are a diode structure and a memory device including the same. The diode structure includes: a first electrode; a p-type Cu oxide layer formed on the first electrode; an n-type InZn oxide layer formed on the p-type Cu oxide layer; and a second electrode formed on the n-type InZn oxide.Type: GrantFiled: March 17, 2008Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-soo Kang, Stefanovich Genrikh, Young-soo Park, Myoung-jae Lee, Seung-eon Ahn, Chang-bum Lee
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Patent number: 7986575Abstract: A memory cell array is formed by arranging memory cells at intersections of plural first wirings and plural second wirings, and a rectifying element and a variable resistive element are connected in series in the memory cell. The variable resistive element has at least a first resistance value and a second resistance value that is higher than the first resistance value. The control circuit selectively drives the first wirings and the second wirings. The control circuit can perform a short-circuit failure countermeasure program operation. In the short-circuit failure countermeasure program operation, the variable resistive element of the memory cell whose rectifying element is in a short-circuit failure state is programmed from the first resistance value to the second resistance value.Type: GrantFiled: March 30, 2009Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Tsuneo Inaba
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Publication number: 20110157960Abstract: Nonvolatile memory devices are provided including a memory cell array having a plurality of stacked memory layers and a rectifier configured to select memory cells constituting each memory layer sharing a word line or a bit line with another adjacent memory layer. The nonvolatile memory devices including a word line driving unit configured to drive a first word line, connected to a first memory cell of a first memory layer to be read, at a first voltage level and drive a second word line, connected to a second memory cell of a second memory layer sharing a first bit line connected to the first memory cell, at a second voltage level. The nonvolatile memory device further includes a bit line biasing unit configured to bias the first bit line at the second voltage level and bias a second bit line, connected to a third memory cell of a third memory layer sharing the first word line, at the first voltage level. Related methods and systems are also provided herein.Type: ApplicationFiled: December 21, 2010Publication date: June 30, 2011Inventor: Shoichi Kawamura
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Patent number: 7969777Abstract: A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.Type: GrantFiled: December 1, 2008Date of Patent: June 28, 2011Assignee: T-RAM Semiconductor, Inc.Inventors: Hyun-Jin Cho, Farid Nemati
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Patent number: 7961534Abstract: A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.Type: GrantFiled: September 5, 2008Date of Patent: June 14, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hee Bok Kang, Suk Kyoung Hong
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Patent number: 7952909Abstract: Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device includes: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.Type: GrantFiled: November 5, 2007Date of Patent: May 31, 2011Assignee: Sharp Kabushiki KaishaInventors: Kohji Inoue, Yasunari Hosoi, Shigeo Ohnishi, Nobuyoshi Awaya
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Patent number: 7943926Abstract: A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.Type: GrantFiled: February 28, 2007Date of Patent: May 17, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-Jae Lee, In-Kyeong Yoo, Eun-Hong Lee, Jong-Wan Kim, Dong-Chul Kim, Seung-Eon Ahn
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Patent number: 7944742Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.Type: GrantFiled: August 24, 2010Date of Patent: May 17, 2011Assignee: Seagate Technology LLCInventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
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Patent number: 7940558Abstract: An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.Type: GrantFiled: December 19, 2008Date of Patent: May 10, 2011Assignee: Qimonda AGInventor: Stefan Slesazeck
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Patent number: 7936580Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions.Type: GrantFiled: October 20, 2008Date of Patent: May 3, 2011Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
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Patent number: 7936585Abstract: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.Type: GrantFiled: July 13, 2009Date of Patent: May 3, 2011Assignee: Seagate Technology LLCInventors: Wei Tian, Insik Jin, Venugopalan Vaithyanathan, Haiwen Xi, Michael Xuefei Tang, Brian Lee
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Patent number: 7936586Abstract: The semiconductor storage apparatus includes a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires, and a control circuit configured to control charging to the first wire. The control circuit charges the first wire connected to a selected memory cell up to a first potential, and then set the first wire in a floating state. Then it charges another first wire adjacent to the first wire connected to the selected memory cell to a second potential. The potential of the first wire connected to the selected memory cell is thereby caused to rise to a third potential by coupling.Type: GrantFiled: August 20, 2009Date of Patent: May 3, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Hiroshi Maejima, Yuri Terada