Abstract: MOS transistors each having different ON withstanding voltages that are drain withstanding voltages when gates thereof are turned on are formed on the same substrate. One of the MOS transistors having the lower ON withstand voltage is used as a memory element. Using the fact that the drain withstanding voltage is low when a gate thereof is turned on, a short-circuit occurs in a PN junction between a drain and the substrate of the one of the MOS transistors having the lower ON withstand voltage to write data.

Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspo

Abstract: A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of the first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract: The invention relates to a method for determining a set of programming conditions for a given type of charge-trapping non-volatile memory device, comprising the steps of: (a) selecting different sets of programming parameters to be applied to the corresponding number of non-volatile memory devices of said type, (b) programming said number of non-volatile memory devices by means of the sets of programming parameters, (c) determining an actual spatial charge distribution of the charge trapping layer of each of the programmed devices, (d) determining the influence of at least one of the programming parameters on the spatial charge distribution, (e) determining an optimised value for at least one of the programming parameters, (f) entering each optimised value in said sets of programming parameters and repeating steps b) to e) at least once.

Abstract: A nonvolatile semiconductor memory comprises: a semiconductor substrate; a first gate electrode formed on a surface of the semiconductor substrate through a first gate insulating film; a second gate electrode formed on the surface of the semiconductor substrate through a second gate insulating film and being adjacent to the first gate electrode through an insulating film; a charge trapping film formed at least in a trap region surrounded by the semiconductor substrate, the first gate electrode and the second gate electrode; and a tunnel insulating film formed between the charge trapping film and the second gate electrode. In one of programming and erasing, electrons are injected into the charge trapping film from the second gate electrode through the tunnel insulating film by Fowler-Nordheim tunneling.

Abstract: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

Abstract: A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM includes a gate that contacts the channel layer and the charge reserving layer.

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract: Provided are a gate stack, a capacitorless dynamic random access memory (DRAM) including the gate stack and methods of manufacturing and operating the same. The gate stack for a capacitorless DRAM may include a tunnel insulating layer on a substrate, a first charge trapping layer on the tunnel insulating layer, an interlayer insulating layer on the first charge trapping layer, a second charge trapping layer on the interlayer insulating layer, a blocking insulating layer on the second charge trapping layer, and a gate electrode on the blocking insulating layer. The capacitorless DRAM may include the gate stack on the substrate, and a source and a drain in the substrate on both sides of the gate stack.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract: A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device.

Abstract: The present invention is a method of undertaking a procedure on a memory-diode, wherein a memory-diode is provided which is programmable so as to have each of a plurality of different threshold voltages. A reading of the state of the memory-diode indicates the so determined threshold voltage of the memory-diode.

Abstract: Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.

Abstract: A semiconductor device comprising: a first well region which is formed at a surface portion of a semiconductor substrate and to which a first voltage is applied; a gate insulating film which is formed on the first well region; a gate electrode which is formed on the gate insulating film and has a polarity different from a polarity of the first well region and to which a second voltage is applied; and an element isolating region which is formed at a surface portion of the first well region to surround a region within the first well region that is opposed to the gate insulating film, wherein a capacitance is formed between the region within the first well region surrounded by the element isolating region and the gate electrode.

Abstract: A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer formed between the gate and the trapping layer, a high-Dit material layer formed between the Si substrate and the trapping layer, and a second oxide layer formed between the high-Dit material layer and the trapping layer, wherein an interface trap density (Dit) between the high-Dit material layer and the Si substrate is in a rang from 1011 cm?2eV?1 to 1013 cm?2eV?1.

Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Abstract: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.

Abstract: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.

Abstract: A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.

Abstract: A non-volatile memory cell and method of fabrication are provided. The non-volatile memory cell includes a substrate of a first conductivity type, a first dopant region of a second conductivity type in the substrate, a second dopant region of the first conductivity type in the first dopant region, a first isolation region overlaying a portion of the substrate, the first dopant region, and the second dopant region, a second isolation region overlaying another portion of the substrate, the first dopant region, and the second dopant region, a contact region of the first conductivity type in the second dopant region, the contact region extending between the first isolation region and the second isolation region and being more heavily doped than the second dopant region, a gate dielectric atop the first isolation region and a portion of the contact region, and a gate conductor atop the gate dielectric.

Abstract: A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association with 2x threshold voltages, the x-bit information being able to be read from each memory cell by applying a read voltage to the corresponding word line; a row decoder connected to the word lines to supply voltages to the word lines to operate the memory cells; and a sense amplifier device connected to the bit lines to read data stored in the memory cells and to hold the read data and data written to the memory cells, wherein the x-bit information corresponding to a certain threshold voltage differs from that corresponding to the adjacent threshold voltage by only 1 bit, 2x?1 of the read voltages are each set for a pair of adjacent threshold voltages, and applying any of the read voltages to the word line determines the x-bit infor

Abstract: A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

Abstract: Embodiments relate to a method for measuring a threshold voltage of a flash device including inputting a voltage and a pulse width. The dependence of threshold voltage on the applied voltages and the pulse width may be determined by using a threshold voltage measuring equation, and equations regarding a plurality of device variables included within the threshold voltage measuring equation.

Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.

Abstract: This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which transmits data with reversed polarities from each other; a first transfer gate provided between the first bit line and the first sense node; a second transfer gate provided between the second bit line and the second sense node; a latch circuit provided between the first and the second sense nodes; a write signal line activated when the data is written or restore to the cell; and a gate circuit connecting the write signal line to the first bit line and the first sense node to the second bit line, or connecting the write signal line to the second bit line and the second sense node to the first bit line, when the data is written or restore.

Abstract: This disclosure concerns a memory including a memory cell including a floating body in an electrically floating state and storing data according to the number of majority carriers in the floating body; a word line connected to a gate of the memory cell; a first bit line connected to the memory cell to transmit the data; a second bit line transmitting reference data used to detect the data stored in the memory cell; a first sense node and a second sense node transmitting the data stored in the memory cell and the reference data, respectively; a first short-circuiting switch provided between the first sense node and the second sense node; and a first flip-flop applying a load current to the memory cell during a data read operation and amplifying a potential difference generated between the first sense node and the second sense node by turning off the first short-circuiting switch

Abstract: A semiconductor memory element that stores data as a resistance difference. The memory element comprises a MIS transistor, a two-terminal variable resistor element, and a fixed resistor element. The MIS transistor has a gate. The two-terminal variable resistor element is connected between the gate of the MIS transistor and a first power-supply terminal. The variable resistor element has a resistance that changes in accordance with a current flowing in the variable resistor element or the direction in which the current flows and that remains unchanged when the current is made to stop flowing. The fixed resistor element is connected between the gate of the MIS transistor and a second power-supply terminal.

Abstract: An TMR-type MRAM comprising a transistor for selection; a first connecting hole; a first wiring (write-in word line); a second insulating interlayer covering a first insulating interlayer and the first wiring; a TRM device formed on the second insulating interlayer; a second wiring (bit line) formed on a third insulating interlayer; and a second connecting hole formed through the second insulating interlayer and connected to the first connecting hole, in which an end face of an extending portion of the other end of the TRM device is in contact with the second connecting hole.

Abstract: Secondary electron injection (SEI) is used for programming NVM cells having separate charge storage areas in an ONO layer, such as NROM cells. Various combinations of low wordline voltage (Vwl), negative substrate voltabe (Vb), and shallow and deep implants facilitate the process. Second bit problems may be controlled, and retention and punchthrough may be improved. Lower SEI programming current may result in relaxed constraints on bitine resistance, number of contacts required, and power supply requirements.

Abstract: Each memory cell of an EPROM contains two MOSFETs and a data of each memory cell is read out by detecting a current difference between the two MOSFETs by using a differential amplifier. In such constitution as described above, even when the data is erased by irradiating an ultraviolet ray, a stable output of the differential amplifier can be obtained and, therefore, confirmation of an initialized state can be facilitated. Specifically, a channel width WA of one of the two MOSFETs constituting the memory cell is formed narrower than a channel width WB of the other. By such arrangement as described above, in an initialized state in which the ultraviolet ray is irradiated, a data signal current value IHA of the MOSFET having the channel width WA becomes smaller than a data signal current value IHB flowing in the MOSFET having the channel width WB. Accordingly, the output of the differential amplifier is fixed in accordance with a current magnitude relation of IHA<IHB, to thereby define a data “0”.

Abstract: A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line. Methods for accessing a memory core cell also are described.

Abstract: A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

Abstract: First active regions and second active regions intersecting the first active regions at a right angle are defined on the surface of a semiconductor substrate, and diffusion regions are formed in the first and second active regions to interpose an intersecting region therebetween. Then, a gate structure is formed linearly to extend over the intersecting region at a non-zero angle with respect to the first and second active regions. Further, terminals to be connected to metal interconnects are provided on the diffusion regions at a non-zero angle with respect to the first and second active regions, respectively. Consequently provided is a nonvolatile semiconductor memory having a simple gate structure capable of storing 4-bits of information in one memory cell.

Abstract: A semiconductor integrated circuit device is provided, which includes a semiconductor layer formed via an embedded insulation film on a substrate and an FBC (Floating Body Cell) which stores data by accumulating a majority carrier in a floating channel body formed on the semiconductor layer.

Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract: A row of floating-body single transistor memory cells is written to in two phases.

Abstract: A nonvolatile memory includes at least a first electrode (71) and a second electrode (72) provided on a substrate, the first and second electrodes being separated from each other, and a conductive organic thin film (73) for electrically connecting the first and second electrodes. The conductive organic thin film (73) has a first electric state in which it exhibits a first resistance, and a second electric state in which it exhibits a second resistance. A first threshold voltage for a transition from the first electric state to the second electric state, and a second threshold voltage for a transition from the second electric state to the first electric state are different from each other, and either the first electric state or the second electric state is maintained a voltage in a range between the first threshold voltage and the second threshold voltage.

Abstract: A memory device includes a coupling capacitor and a field-effect transistor. The coupling capacitor is formed from (1) a first dopant region in a second dopant region on a substrate, (2) a gate dielectric atop the first dopant region, and (3) a first gate conductor atop the gate dielectric. The coupling capacitor has the first gate conductor coupled to a second gate conductor of the field-effect transistor. A voltage can be applied to the second dopant region to isolate the coupling capacitor from the substrate by reverse biasing a PN junction formed between the first dopant region and the second dopant region.

Abstract: Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a first level and indicative of a second program state when the read current is at a second level. The read current is ineffective to produce a change in program state. A first voltage pulse is used during a first write mode if a change from a second program state to a first program state is desired. A second voltage pulse is used during a second write mode if a change from the first program state to the second program state is desired.

Abstract: A nonvolatile memory apparatus which includes a control circuit, plural terminals including a clock, command and other terminals, a converter circuit, and plural of nonvolatile memory cells. The clock terminal receives a clock signal, the command terminal receives commands including a read and program commands, and the control circuit reads out operation steps from a program memory to be executed to control an operation of the received command. In an operation in response to the read command, the control circuit controls reading data in parallel from ones of the nonvolatile memory cells, converting parallel type data to serial type data by the converter circuit, and serially outputting data via the other terminal except the command terminal in response to the clock signal.

Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Abstract: A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line. Methods for accessing a memory core cell also are described.

Abstract: Cross point memory array using multiple modes of operation. The invention is a cross point memory array that uses a read mode to determine the resistive state of a memory plug, a first write mode to cause the memory plug to change from a first resistive state to a second resistive state, and a second write mode to cause the memory plug to change from the second resistive state back to the first resistive state.

Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.

Abstract: A memory cell has two diffusion areas in a substrate with a channel therebetween. The memory cell also includes a trapping dielectric layer at least over the channel, a gate at least above the trapping dielectric layer, and an implant in the substrate adapted to provide maximal band-to-band tunneling during erasure of charge stored in the trapping dielectric layer.

Abstract: A NAND stack array (95′) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.