Global Word Or Bit Lines Patents (Class 365/185.13)
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Patent number: 8780605Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.Type: GrantFiled: January 7, 2013Date of Patent: July 15, 2014Assignee: SanDisk 3D LLCInventors: Tianhong Yan, George Samachisa
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Patent number: 8773884Abstract: A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat.Type: GrantFiled: December 16, 2013Date of Patent: July 8, 2014Inventor: Seiji Narui
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Patent number: 8767470Abstract: Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.Type: GrantFiled: August 2, 2012Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventor: Tomoharu Tanaka
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Patent number: 8760925Abstract: Plural memory-strings are arranged in each memory-blocks, the memory-strings extending perpendicular to a substrate. Each memory-string includes plural memory-transistors and dummy-transistors connected in series. The drain-side select gate line and source-side select gate line are supplied with a voltage from the control circuit through the transfer-transistors when corresponding one of the memory blocks is selected. The drain-side select gate line and source-side select gate line are set in a floating state by the transfer-transistors that are rendered non-conductive when corresponding one of the memory-blocks is not selected. The dummy word-line is supplied with a voltage from the control circuit through a first transfer-transistor that are rendered conductive when corresponding memory block is selected. The dummy word-line is supplied with a voltage through a second transfer transistor different from the first transfer-transistor when corresponding memory-block is not selected.Type: GrantFiled: August 30, 2012Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Xu Li
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Patent number: 8760940Abstract: A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line.Type: GrantFiled: December 11, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Shao-Yu Chou
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Patent number: 8755225Abstract: A memory device comprises a main memory array having a plurality of bit lines, and a select array having a plurality of transistors coupled to the bit lines. Wherein one of the plurality of transistors is electrically programmed to a threshold voltage greater than a threshold voltage of another one of the plurality of transistors.Type: GrantFiled: May 8, 2012Date of Patent: June 17, 2014Assignee: Macronix International Co., Ltd.Inventor: Chung-Kuang Chen
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Patent number: 8730731Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including a matrix of memory cells; a plurality of local bit lines divided into at least two local bit line groups arranged to be alternately connected with at least two global bit lines and coupled with the memory cells; a plurality of bit line selection drivers respectively connected to the local bit lines; an internal boosted voltage generator configured to generate at least two internal boosted voltages having different levels; and a power transmitter configured to respectively transmit the at least two internal boosted voltages to at least two bit line selection driver groups, into which the plurality of bit line selection drivers are classified according to arrangement of the local bit lines. Accordingly, repair efficiency can be increased and near-far compensation can be more correctly performed.Type: GrantFiled: January 15, 2010Date of Patent: May 20, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Jung Kim, Young Sun Song
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Patent number: 8730755Abstract: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.Type: GrantFiled: May 14, 2013Date of Patent: May 20, 2014Assignee: Intel CorporationInventors: Raymond W. Zeng, DerChang Kau
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Patent number: 8730734Abstract: The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.Type: GrantFiled: January 21, 2013Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventor: Dzung H. Nguyen
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Publication number: 20140133236Abstract: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicant: MOSAID Technologies IncorporatedInventors: Hong Beom PYEON, Jin-Ki KIM
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Patent number: 8724385Abstract: A semiconductor memory has main bit lines paralleled by fixed potential lines in an alternating arrangement. Each main bit line is switchably connected to two sub-bit lines. The memory cells connected to one of the two sub-bit lines are placed below the main bit line. The memory cells connected to the other one of the two sub-bit lines are placed below an adjacent fixed potential line. The fixed potential lines prevent parasitic capacitive coupling between the main bit lines and thereby speed up read access to the memory cells without taking up extra layout space.Type: GrantFiled: October 17, 2011Date of Patent: May 13, 2014Assignee: Lapis Semiconductor Co., Ltd.Inventor: Tatsuru Shinoda
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Patent number: 8724390Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.Type: GrantFiled: September 26, 2011Date of Patent: May 13, 2014Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Shuo-Nan Hung, Ji-Yu Hung, Shih-Lin Huang, Fu-Tsang Wang
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Patent number: 8724424Abstract: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.Type: GrantFiled: July 3, 2013Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nakamura, Kenichi Imamiya
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Patent number: 8717825Abstract: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.Type: GrantFiled: December 20, 2011Date of Patent: May 6, 2014Assignee: STMicroelectronics S.R.L.Inventor: Cesare Torti
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Patent number: 8705293Abstract: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.Type: GrantFiled: October 20, 2011Date of Patent: April 22, 2014Assignee: SanDisk Technologies Inc.Inventors: Min She, Yan Li, Kwang-Ho Kim, Siu Lung Chan
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Publication number: 20140098611Abstract: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Micron Technology, Inc.Inventor: Toru Tanzawa
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Patent number: 8693231Abstract: A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.Type: GrantFiled: June 13, 2012Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Akira Goda, Seiichi Aritome
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Patent number: 8693278Abstract: Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines.Type: GrantFiled: March 7, 2012Date of Patent: April 8, 2014Inventor: Noriaki Mochida
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Publication number: 20140092684Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.Type: ApplicationFiled: December 5, 2013Publication date: April 3, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Takashi MAEDA
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Patent number: 8687422Abstract: A method and device are provided for operating in a special mode using a special mode enable register. In one example, a memory device includes registers in volatile memory and a memory array. At least one of the registers may include a special mode bit that controls a special mode of operation of the memory device.Type: GrantFiled: January 24, 2012Date of Patent: April 1, 2014Assignee: Micron Technologies, Inc.Inventors: Theodore T. Pekny, Victor Y. Tsai
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Patent number: 8681553Abstract: A memory array includes a plurality of sense amplifiers and a first switch module. The plurality of sense amplifiers is connected respectively to a plurality of global bit lines. The plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array. The memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines. The first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines. The first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines.Type: GrantFiled: June 25, 2013Date of Patent: March 25, 2014Assignee: Marvell World Trade Ltd.Inventors: Pantas Sutardja, Winston Lee
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Patent number: 8681565Abstract: A main bit line is disposed between a reference main bit line and core main bit lines. A selection transistor disposed between a sub bit line connected to a cell and the main bit line can switch between a conductive state and a non-conductive state independently of other selection transistors. A dummy main bit line can be set to ground potential by a shield grounding section, and can be used as a shield line of the reference main bit line.Type: GrantFiled: December 10, 2012Date of Patent: March 25, 2014Assignee: Panasonic CorporationInventors: Takanori Ueda, Masayoshi Nakayama, Kazuyuki Kouno
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Patent number: 8675418Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.Type: GrantFiled: August 31, 2010Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Shau-Wei Lu, Robert Lo, Kun-Hsi Li
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Patent number: 8665625Abstract: A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers.Type: GrantFiled: July 3, 2013Date of Patent: March 4, 2014Assignee: Elpida Memory, Inc.Inventor: Seiji Narui
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Patent number: 8649217Abstract: According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.Type: GrantFiled: March 13, 2012Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takuji Kuniya, Katsunori Yahashi
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Patent number: 8644082Abstract: An erase operation of a memory apparatus is controlled by, inter alia, selecting one or more memory cell blocks to be erased among a plurality of memory cell blocks, performing an erase operation on the selected one or more memory cell blocks in response to an erase command, performing a first soft program operation on the selected one or more memory cell blocks if the erase operation is determined as passed, and performing a second soft program operation on the selected one or more memory cell blocks if the first soft program operation is determined as passed.Type: GrantFiled: August 27, 2011Date of Patent: February 4, 2014Assignee: SK Hynix Inc.Inventor: Kwang Ho Baek
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Patent number: 8638630Abstract: A device includes a plurality of restoring circuits each provided for an associated one of local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones of the local bit lines, data that is or are read out from a memory cell or cells connected to the remaining one or ones of the local bit lines, and restore, through the remaining one or ones of the local bit lines, the data into the memory cell or cells connected to the remaining one or ones of the local bit lines.Type: GrantFiled: September 15, 2012Date of Patent: January 28, 2014Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Yasutoshi Yamada
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Patent number: 8633465Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.Type: GrantFiled: February 8, 2012Date of Patent: January 21, 2014Assignee: Peking UniversityInventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
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Patent number: 8630115Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.Type: GrantFiled: August 5, 2011Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventors: Luigi Pascucci, Paolo Rolandi
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Patent number: 8625349Abstract: A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.Type: GrantFiled: November 13, 2009Date of Patent: January 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kutsukake, Kenji Gomikawa, Mitsuhiro Noguchi, Kikuko Sugimae, Masato Endo, Takuya Futatsuyama, Koji Kato, Kanae Uchida
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Patent number: 8619472Abstract: A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has a structure in the same manner as the word lines. The source pass word line is provided between a source select line and a word line. The source pass word line has a structure in the same manner as the word lines. A program voltage is applied to a selected word line associated with a selected memory cell block. A ground voltage is applied to drain pass word lines and source pass word lines. Word lines associated with unselected memory cell blocks are set to a floating state.Type: GrantFiled: October 25, 2011Date of Patent: December 31, 2013Assignee: SK hynix Inc.Inventor: Hee Youl Lee
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Publication number: 20130336064Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Takashi MAEDA
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Patent number: 8611153Abstract: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state.Type: GrantFiled: February 17, 2012Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventor: Toru Tanzawa
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Patent number: 8605532Abstract: Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.Type: GrantFiled: November 17, 2011Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Yasutoshi Yamada
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Patent number: 8593865Abstract: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder that selects one of the memory blocks in response to an input address and generates a first control signal and a second control signal, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors that connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal, and a plurality of ground transistors that supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction.Type: GrantFiled: September 20, 2011Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Su-yong Kim, Doogon Kim
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Patent number: 8593881Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: GrantFiled: November 22, 2011Date of Patent: November 26, 2013Assignee: Spansion Israel LtdInventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Patent number: 8589766Abstract: Systems and methods are disclosed for remapping codewords for storage in a non-volatile memory, such as flash memory. In some embodiments, a controller that manages the non-volatile memory may prepare codeword using a suitable error correcting code. The controller can store a first portion of the codeword in a lower page of the non-volatile memory may store a second portion of the codeword in an upper page of the non-volatile memory. Because upper and lower pages may have different resiliencies to error-causing phenomena, remapping codewords in this manner may even out the bit error rates of the codewords (which would otherwise have a more bimodal distribution).Type: GrantFiled: February 24, 2010Date of Patent: November 19, 2013Assignee: Apple Inc.Inventors: Daniel J. Post, Kenneth Herman
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Patent number: 8587998Abstract: A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.Type: GrantFiled: January 6, 2012Date of Patent: November 19, 2013Assignee: Macronix International Co., Ltd.Inventor: Shuo-Nan Hung
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Patent number: 8582390Abstract: The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.Type: GrantFiled: May 7, 2012Date of Patent: November 12, 2013Assignee: Micron Technology, Inc.Inventors: Xiaojun Yu, Jin-man Han
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Patent number: 8582363Abstract: A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.Type: GrantFiled: January 31, 2011Date of Patent: November 12, 2013Assignee: Aplus Flash Technology, Inc.Inventor: Peter Wung Lee
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Patent number: 8576627Abstract: At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.Type: GrantFiled: July 7, 2011Date of Patent: November 5, 2013Assignee: Micron Technology, Inc.Inventor: Satoru Tamada
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Patent number: 8559227Abstract: A nonvolatile memory device includes a plurality of global word lines, a plurality of transistors configured to transfer voltages of the global word lines to a plurality of local word lines inside a cell block, and a voltage control unit configured to supply a first negative voltage to a global word line of the plurality of global word lines and configured to charge a bulk region of the plurality of transistors with a second negative voltage.Type: GrantFiled: July 7, 2011Date of Patent: October 15, 2013Assignee: Hynix Semiconductor Inc.Inventors: Lee-Hyun Kwon, In-Sou Wang, Myung-Jin Park
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Patent number: 8547755Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.Type: GrantFiled: December 7, 2012Date of Patent: October 1, 2013Assignee: Macronix International Co., Ltd.Inventors: Yi-Fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen Long Chang, Chun-Hsiung Hung
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Patent number: 8526232Abstract: A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.Type: GrantFiled: April 12, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jun Min, Hoi-Ju Chung
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Patent number: 8526231Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.Type: GrantFiled: July 7, 2011Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Kyu Lee, Tea-Kwang Yu, Bo-Young Seo
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Patent number: 8520445Abstract: A memory device includes a block switch for transferring operating voltages, supplied to global lines, to local lines coupled to a memory cell array in response to the voltage level of a block selection signal and a negative voltage transfer circuit for transferring a negative voltage as the block selection signal in order to couple the global lines and the local lines when the operating voltage has a negative level and to disconnect the global lines and the local lines from each other when the block selection signal is disabled.Type: GrantFiled: August 31, 2011Date of Patent: August 27, 2013Assignee: SK Hynix Inc.Inventor: Min Gyu Koo
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Patent number: 8520421Abstract: According to one embodiment, a semiconductor associative memory device comprises a retrieval block having retrieval word strings arranged in a column direction, each of the retrieval word strings includes memory cells arranged in a row direction between a word input terminal and a word output terminal, each of the memory cells having a first input terminal, a second input terminal, and an output terminal, wherein in each retrieval word string, the second input terminal of one of the memory cells is used as the word input terminal, and each of other memory cells is connected to the output terminal of adjacent memory cell by the second input terminal, wherein the first input terminals of the memory cells in the same column are connected.Type: GrantFiled: March 16, 2012Date of Patent: August 27, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Atsuhiro Kinoshita
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Patent number: 8508969Abstract: A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.Type: GrantFiled: June 26, 2012Date of Patent: August 13, 2013Assignee: Elpida Memory, Inc.Inventor: Seiji Narui
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Patent number: 8503214Abstract: A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.Type: GrantFiled: February 25, 2011Date of Patent: August 6, 2013Assignee: Renesas Electronics CorporationInventor: Yasuo Kobayashi
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Publication number: 20130176786Abstract: Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated.Type: ApplicationFiled: September 14, 2012Publication date: July 11, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Min JEON, Weonho PARK, Byoungho KIM