Abstract: Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.

Abstract: Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.

Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.

Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

Abstract: A semiconductor memory device includes a first memory string including a first select transistor, a first memory cell, a first select element, a second memory cell, and a second select element in series, a second memory string including a second select transistor, a third memory cell, a third select element, a fourth memory cell, and a fourth select element in series, and a control circuit. The control circuit is configured to set the second select transistor to an on state, and to set the third select element and the fourth select element to an off state, when reading data of the first memory cell.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: A variety of applications can include a high voltage switch configured to translate supply voltages or other voltages to specific magnitudes in memory devices, with the high voltage switch designed to provide enhanced lifetime of components of the high voltage switch. A high voltage switch can include a high voltage diode coupled to an output node and to a gate of a high voltage transistor coupled to the output node. The high voltage diode can provide feedback of an output voltage to the gate of the high voltage transistor to relieve Fowler-Nordheim stress on the dielectric coupled to the gate in the transistor, where large shifts in threshold voltage of the transistor could otherwise result from the Fowler-Nordheim stress. The high voltage diode can be structured using a high voltage field effect transistor. Additional devices, systems, and methods are discussed.

Abstract: A built-in self-test (BIST) circuit and a BIST method for Physical Unclonable Function (PUF) quality check are provided. The BIST circuit may include a PUF array, a readout circuit coupled to the PUF array, and a first comparing circuit coupled to the readout circuit. The PUF array may include a plurality of PUF units, wherein each of the PUF units includes a first cell and a second cell. The readout circuit may be configured to output an output bit from the first cell and output a parity bit from the second cell. The first comparing circuit may be configured to compare an output string with a parity string to generate a parity check result, wherein the output string includes output bits respectively read from selected PUF units of the PUF units, and the parity string includes parity bits read from the selected PUF units.

Abstract: A semiconductor device includes first, second, third, and fourth active regions provided in an substrate, each of which includes a central portion, first and second portions provided at opposite sides of the central portion in a first direction, and third and fourth portions provided at opposite sides of the central portion in a second direction orthogonal to the first direction. An end portion of the first portion of the first active region faces a side portion of the fourth portion of the fourth active region, an end portion of which faces aside portion of the second portion of the second active region. An end portion of the second portion of the second active region faces a side portion of the third portion of the third active region, an end portion of which faces a side portion of the first portion of the first active region.

Abstract: A memory card includes a plurality of interconnection terminals aligned in a row direction and a column direction on a substrate. Each of the plurality of interconnection terminals has a first-axis length equal to no more than 1.2 time that of a second-axis length thereof. A non-volatile memory device is disposed on the substrate. The non-volatile memory device is electrically connected to at least one interconnection terminal corresponding thereto from among the plurality of interconnection terminals.

Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation.

Abstract: A storage device is provided. The storage device includes a memory device including a memory cell array configured to store metadata and main data and a storage controller configured to access the memory device and control the memory device, wherein the storage controller is configured to read data from the memory device at a speed adaptively varying to a first read speed or a second read speed according to a state of the memory device, the second read speed being faster than the first read speed.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor, a second memory cell transistor, and a first select element that connects the first memory cell transistor and the second memory cell transistor in series, a second memory string including a third memory cell transistor, a fourth memory cell transistor, and a second select element that connects the third memory cell transistor and the fourth memory cell transistor in series, and a control circuit. The control circuit is configured to set the second select element to an off state while setting the first select element to an on state when reading data of the first memory string.

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.

Abstract: A semiconductor structure includes a first-conductivity-type well located in a semiconductor substrate, a semiconductor active area region located adjacent to the a first-conductivity-type well, a first transistor including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, such that the transistor is located on the semiconductor active area region, and a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well.

Abstract: A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Abstract: A semiconductor memory device includes a first conductive layer, a first and a second semiconductor layer opposed to the first conductive layer, a first and a second electric charge accumulating portion disposed between the first conductive layer and the first and the second semiconductor layer, and a first and a second bit line electrically connected to the first and the second semiconductor layer. A distance from a center position of the first conductive layer to the second semiconductor layer is smaller than a distance from the center position of the first conductive layer to the first semiconductor layer. When a read operation is executed on a first memory cell including the first electric charge accumulating portion and a second memory cell including the second electric charge accumulating portion, a voltage of the second bit line is larger than a voltage of the first bit line.

Abstract: Embodiments described herein relate to a method for manufacturing a 1.5T SONOS flash memory. First, a first polysilicon gate layer is deposited and formed on a semiconductor substrate, then a formation area of a memory gate is defined on the first polysilicon gate layer, polysilicon in the formation area of the memory gate is etched away, and etching is stopped on a gate oxide layer. Next, an ONO layer and a second polysilicon gate layer are sequentially deposited, chemical mechanical polishing is performed on the second polysilicon gate layer, the ONO layer remaining on the top of the first polysilicon gate layer is cleaned away, and then gate structures of a logic device and a 1.5T SONOS device are formed at the same time.

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.

Abstract: A variety of applications can include a high voltage switch configured to translate supply voltages or other voltages to specific magnitudes in memory devices, with the high voltage switch designed to provide enhanced lifetime of components of the high voltage switch. A high voltage switch can include a high voltage diode coupled to an output node and to a gate of a high voltage transistor coupled to the output node. The high voltage diode can provide feedback of an output voltage to the gate of the high voltage transistor to relieve Fowler-Nordheim stress on the dielectric coupled to the gate in the transistor, where large shifts in threshold voltage of the transistor could otherwise result from the Fowler-Nordheim stress. The high voltage diode can be structured using a high voltage field effect transistor. Additional devices, systems, and methods are discussed.

Abstract: A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals.

Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.

Abstract: This application relates to a method and apparatus for processing a new read-write-operation instruction added to an instruction set to maximize the performance of processing-in-memory (PIM). The read-write-operation instruction performs reading and writing on an operation result of the PIM by returning the operation result of the PIM to a computer system and, at the same time, writing the operation result to a destination address. An instruction processor in PIM includes a response data selector and a finite state machine to process the read-write-operation instruction. The response data selector includes a selector configured to select one of a response data signal and an operation result, and a three-phase buffer configured to allow or disallow response data. The finite state machine of the instruction processor outputs a response permission signal and a response selection signal for controlling the buffer and the selector.

Abstract: Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

Abstract: A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.

Abstract: A display device can include a substrate provided with a first subpixel, a first electrode including a first sub electrode provided on the first subpixel, an organic light emitting layer including first and second organic light emitting layers arranged on the first sub electrode and a second organic light emitting layer arranged on the second sub electrode, a second electrode arranged on the organic light emitting layer, and an auxiliary electrode arranged between the first organic light emitting layer on the first sub electrode and the second organic light emitting layer on the first sub electrode, wherein the auxiliary electrode is connected with the second electrode. Therefore, although the first subpixel has a two-stack structure, the organic light emitting layer can emit light in accordance with a voltage of one-stack, whereby overall power consumption can be reduced.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source line formed over a substrate. The semiconductor device may include a channel pattern including a connection part disposed over the source line, and pillar parts protruding from the connection part in a first direction. The semiconductor device may include a well structure protruding from the connection part in the first direction and spaced apart from the source line. The semiconductor device may include a source contact structure protruding from the source line in the first direction and passing through the connection part. The semiconductor device may include a gate stack disposed between the source contact structure and the well structure and enclosing the pillar parts over the connection part.

Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.

Abstract: A semiconductor memory device includes a plurality of bit lines extending in a first direction, and arranged in a second direction intersecting with the first direction, a page buffer high-voltage circuit divided into a plurality of page buffer high-voltage regions arranged in the first direction, each of the plurality of page buffer high-voltage regions including a plurality of page buffer high-voltage elements, each page buffer high-voltage element coupled to one of the plurality of bit lines, and a contact pad unit including a plurality of contact pads, each contact pad coupled to one of the plurality of page buffer high-voltage elements. The contact pad unit is arranged, in the first direction, between two of the plurality of page buffer high-voltage regions.

Abstract: Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.

Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

Abstract: A CAM device includes a cell array including a plurality of CAM cells, a search line driving circuit connected to the cell array through a plurality of search lines, and a match line sensing circuit connected to the cell array through a plurality of match lines. Each of the CAM cells includes a first half CAM cell connected to a first match line and a second half CAM cell connected to a second match line different from the first match line. The first match line connected to the first half CAM cell is precharged in a first phase, and the second match line connected to the second half CAM cell is precharged in a second phase after the first phase. Thus, power consumption of the CAM device is reduced and delay is minimized.

Abstract: A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.

Abstract: A memory device comprises a plurality of stacks of bit lines alternating with insulating strips over an insulating layer on a substrate, and a plurality of vertical gate structures disposed between the stacks. Vertical channel structures and memory elements are disposed between outside surfaces of the vertical gate structures and sidewalls of insulating strips in the stacks of bit lines. The vertical channel structures provide channels between adjacent bit lines in the stacks. A plurality of word line transistors is disposed over and connected to respective vertical gate structures. A plurality of word lines is disposed over and connected to the word line transistors. The memory device comprises circuitry connected to the bit lines to apply bit line and source line voltages to the bit lines.

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.

Abstract: High-efficiency control technology for non-volatile memory. A non-volatile memory has single level cells (SLCs) and multiple level cells (e.g., MLCs or TLCs) and is controlled by a controller. According to the controller at the device end, a host allocates a system memory to provide a host memory buffer (HMB). The controller at the device end uses the HMB to buffer write data issued by the host, and then flushes the write data from the HMB to multi-level cells of the non-volatile memory without passing single level cells of the non-volatile memory to reduce write amplification problems due to the frequent use of the single-level cells.

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

Abstract: A memory is disclosed. A memory cell comprises three gate structures sequentially arrayed between a first source-drain region and a second source-drain region. A first gate structure and a third gate structure are formed by superposition of a first gate dielectric layer, a floating gate, a second gate dielectric layer and a polysilicon control gate, so that two memory bits and two control gates are formed. A second gate structure is located between the first gate structure and the third gate structure and serves as a select gate. Erasing and programming operations on the two memory bits formed by the floating gates are realized by FN tunneling. During erasing and programming, the first source-drain region and the second source-drain region are grounded, so that the memory bits can be selected and then erased or programmed only by controlling voltages of the first control gate, the select gate and the second control gate. An operation method of a memory is further disclosed.

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.