Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of a drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, and, when it is judged by the verify operation on the drain side select gate that the threshold voltage of the drain side select gate has not reached the certain value, repeatedly executing a programming operation for setting a threshold voltage of a drain side dummy cell connected to the drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, until the threshold voltage of the drain side dummy cell has reached the certain value.

Abstract: A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is programmed to at least a second threshold voltage to indicate the particular data value. The second threshold voltage is greater than the first threshold voltage.

Abstract: A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a memory according to a first technique and determining a second read threshold voltage of the set of storage elements of the memory according to a second technique. The first read threshold voltage is different from the second read threshold voltage, and the first technique is different from the second technique.

Abstract: An apparatus, system, and method are disclosed for managing erase operations for a data storage medium. A method includes determining whether a use threshold for one or more non-volatile storage cells is satisfied. A method includes performing a default erase operation for the one or more storage cells in response to determining that the use threshold is not satisfied. A method includes performing an extended erase operation for the one or more storage cells in response to determining that the use threshold is satisfied. An extended erase operation may include a greater number of erase pulse iterations than a default erase operation.

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

Abstract: In a method of reading data in a nonvolatile memory device including data cells and monitoring cells. A first read operation applies a first read voltage to the data cells and monitoring cells. If a read fail occurs, a second read operation is performed using a read voltage level determined according to a number of ON-cells among the monitoring cells.

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Abstract: Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.

Abstract: According to one embodiment, a method for operating a nonvolatile semiconductor memory device, the device includes a memory unit having a memory string, and a control unit. The memory string includes a plurality of transistors and has a first group being part of the transistors, a adjusting transistor connected next to the first group, and a second group including transistors connected to a side opposite the first group with respect to the adjusting transistor. The method includes rewriting the threshold values of the transistors of the first group, and then performing control so as to set a first threshold value for adjustment to the adjusting transistor to adjust an amount corresponding to relative variations in the threshold values of the transistors of the second group, the relative variations being caused by the rewrite of the threshold values of the transistors of the first group.

Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.

Abstract: A semiconductor memory device includes: a plurality of memory cells coupled in series between a bit line and a source line; and a bit line control voltage supply unit configured to provide a control voltage to the bit line according to an operation mode, wherein the bit line control voltage supply unit provides a control voltage having a ground voltage level to the bit line during a soft programming operation.

Abstract: Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.

Abstract: Subject matter disclosed herein relates to techniques to use a memory device. A method includes receiving a memory instruction comprising at least one parameter representative of at least one threshold voltage value and a read command to read at least one cell of the memory device. The method further includes detecting at least one voltage value from the at least one cell. The method further includes comparing the at least one voltage value to the at least one threshold voltage value. The method further includes determining at least one logical value of the at least one cell in response to the comparison of the at least one voltage value to the at least one threshold voltage value.

Abstract: A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes.

Abstract: An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

Abstract: A method for multiple step programming programs data to an even page of memory cells. The even page of memory cells is read into a page buffer and the uncertain data is removed. An odd page of memory cells is programmed and the data from the even page data from the page buffer is reprogrammed to the even page of memory cells without the uncertain data.

Abstract: Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage VDD for digital value “1” and ground voltage VSS for digital value “0” are connected to the two input nodes of the two non-volatile elements respectively after configuration. The digital signal either VDD or VSS passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.

Abstract: A semiconductor memory system can include a memory device having a memory cell array that includes a plurality of memory cells. A memory controller can be configured to perform domain transformation on data written to and/or read from the plurality of memory cells to provide domain-transformed data and configured to perform signal processing on the domain-transformed data to output processed data or a control signal.

Abstract: An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up table based on the plurality of reads and (v) set the threshold value in response to the calibration value.

Abstract: A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced.

Abstract: A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural memory cells operative to store data nonvolatilely in accordance with plural different threshold voltages; and a control unit operative to, in data write to the memory cell, execute write loops having a program operation for changing the threshold voltage of the memory cell and a verify operation for detecting the threshold voltage of the memory cell after the program operation, the control unit, in data write for changing one threshold voltage of the plural threshold voltages, executing the verify operation, when the number of write loops to the memory cell becomes more than a certain defined number, using a condition that can pass the verify operation easier than that when the number of write loops is equal to or less than the certain defined number.

Abstract: A semiconductor memory device and a method of operating the same include a circuit group configured to apply a program maintaining voltage between the program prohibition voltage and the program permission voltage to bit lines connected to programmed memory cells to prevent a decrease in threshold voltage.

Abstract: Memory devices and bulk storage devices configured to program a memory cell to a target threshold voltage representing a data pattern of more than one bit and read the data pattern of more than one bit of the memory cell in a single read operation by generating a signal that is representative of an actual threshold voltage of the memory cell.

Abstract: A method for adaptive voltage range management in non-volatile memory is described. The method includes establishing an adaptive voltage range for a memory element of an electronic memory device. The memory element includes at least two states. The adaptive voltage range comprises a lower state and an upper state. The method also includes establishing an adjustment process to implement a first adjustment of an abode characteristic of a first state and to implement a second adjustment of an abode characteristic of a second state in the adaptive voltage range in response to a trigger event, wherein the first adjustment of an abode characteristic of the first state is different from the second adjustment of an abode characteristic of the second state.

Abstract: A method of programming selected memory cells to a plurality of target states comprises applying a first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to at least one target state, applying a program voltage to the selected memory cells, and applying a second verification voltage lower than the first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to the at least one target state, wherein the second verification voltage is provided in a specified program loop and subsequent program loops. The second verification voltage is set such that a number of slow bits in the at least one target state is different from the number of slow bits in another target state.

Abstract: The present invention provides for a solution benefiting from providing for a method and system to reduce the impact of read disturbance while providing improved system performance through optimized activities with minimal impact to overhead. The present invention provides for a highly effective early page migration mechanism, prior to a manufacturer's endurance limit and without a forced block migration, to reduce read disturbance associated with traditional NAND-based memory architectures, in part by identifying a block counter value, determining a block threshold value and early migrating one or more pages of data from the original block location upon the satisfaction of certain criteria.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.

Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

Abstract: Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells programmed to the first number of data states and determining changes in threshold voltage for memory cells at each data state of a second number of data states by searching threshold voltage data of memory cells programmed to the second number of data states within a range of threshold voltages, wherein the range is shifted from a previous range based on the changes in threshold voltage for memory cells programmed to the first number of data states.

Abstract: Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit configured to perform one or more reading operations on a set of memory cells to determine an upper bound of the threshold voltages of the set of memory cells. The device may further include a parameter adjustment unit configured to adjust one or more operational parameters for the set of memory cells based, at least in part, on the determined upper bound of the threshold voltages. Other techniques and devices are also provided.

Abstract: Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a bit line, a source line, and a sense circuit. The memory cell array includes memory strings which include memory cells connected in series and stacked above a semiconductor substrate. The bit line is coupled to one of the memory strings and is capable of transferring data. The source line is coupled to one of the memory strings. When data is read, a read current flows from a bit line into the source line. The sense circuit is coupled to the bit line and senses read data. An operation timing of the sense circuit is determined on the basis of a current flowing through the source line.

Abstract: A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.

Abstract: An operating method of a semiconductor device that includes a plurality of memory cell blocks, comprising selecting one of the memory cell blocks in response to a program command, performing a pre-program operation and a pre-erase operation so that threshold voltages of memory cells included in the selected memory cell block are distributed between a first positive voltage and a first negative voltage, supplying a program permission voltage to a first group of bit lines and supplying a program inhibition voltage to a second group of bit lines, wherein the first group and the second group are mutually exclusive, and supplying a positive program voltage to a selected word line coupled to memory cells.

Abstract: A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and erase operations. Such operations change a distribution of the data values stored in the memory group.

Abstract: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.

Abstract: Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.

Abstract: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.

Abstract: An erase method of a semiconductor device includes performing an operation comprised of supplying an erase pulse to erase the memory cells of a memory block, performing an erase verify operation for detecting memory cells of the memory block having threshold voltages dropped to a target erase voltage, from among the memory cells, performing a pre-program operation on the memory cells having the threshold voltages dropped to the target erase voltage, if, as a result of the erase verify operation, the memory block comprises memory cells having the threshold voltages higher than the target erase voltage and the memory cells having the threshold voltages dropped to the target erase voltage, and repeating the operation of supplying an erase pulse, the erase verify operation, and the pre-program operation until the threshold voltages of all the memory cells drop to the target erase voltage.

Abstract: A semiconductor memory device and a method of operating the same results in reduced programming time. The semiconductor memory device includes advanced circuitry that enables reductions in programming and verification times, leading to a substantial reduction in the total time required to program the device.

Abstract: A method includes performing a read operation that reads data from a group of analog memory cells using at least one read threshold, to produce readout results. A detection is made that the read threshold is set in a restricted range that causes the readout results not to reflect the read threshold. The data is reproduced from the group of the memory cells while compensating for the read threshold that is set in the restricted range.

Abstract: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition.

Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.

Abstract: A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows.

Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.

Abstract: Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions.

Abstract: In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP.

Abstract: Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method determines an access speed for a page request. The access speed is a number of clock cycles used to access a memory device of a group of memory devices. The page request is a request to access a memory page mapped to the memory device. Different page requests are selectively scheduled to access different memory devices in parallel. The different page requests access the different memory devices in a same number of clock cycles.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.