Abstract: An in-memory multiply and accumulate circuit includes a memory array, such as a NOR flash array, storing weight values Wi,n. A row decoder is coupled to the set of word lines, and configured to apply word line voltages to select word lines in the set. Bit line bias circuits produce bit line bias voltages for the respective bit lines as a function of input values Xi,n on the corresponding inputs. Current sensing circuits are connected to receive currents in parallel from a corresponding multimember subset of bit lines in the set of bit lines, and to produce an output in response to a sum of currents.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

Abstract: A trimmable sense amplifier for use in a memory device is disclosed.

Abstract: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.

Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

Abstract: One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell. Other methods and systems are also disclosed.

Abstract: An integrated circuit (10) comprises a plurality of non-volatile memory cells (14) and a charge distribution ramp rate control circuit (11). Each memory cell of the array (12) includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor (62,116,144) having a first plate electrode coupled to at least one terminal of the plurality of terminals, and a second plate electrode. The charge distribution ramp rate control circuit further includes a bandgap generated current source (58,106,136) for providing a reference current to determine a ramp rate of a voltage at the at least one terminal.

Abstract: A non-volatile memory having boost structures. Boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.

Abstract: A method for operating non-volatile memory having boost structures. The boost structures are provided for individual NAND strings and can be individually controlled to assist in programming, verifying and reading processes. The boost structures can be commonly boosted and individually discharged, in part, based on a target programming state or verify level. The boost structures assists in programming so that the programming and pass voltage on a word line can be reduced, thereby reducing side effects such as program disturb. During verifying, all storage elements on a word line can be verified concurrently. The boost structure can also assist during reading. In one approach, the NAND string has dual source-side select gates between which the boost structure contacts the substrate at a source/drain region, and a boost voltage is provided to the boost structure via a source-side of the NAND string.

Abstract: The present memory device includes first and second electrodes, an active layer; and a passive layer, the active and passive layers being between the first and second electrodes, with at least one of the active layer and passive layer being a doped a sol-gel.

Abstract: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the voltage difference between the first voltage and the second voltage is large enough for the electrons injected into the floating gate of the memory cells to be removed via the select gate. (b) A switchover operation is performed so that the first voltage is applied to the even-numbered select gates of each memory row and the second voltage is applied to the odd-numbered select gates of each memory row such that the electrons injected into the floating gates of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.

Abstract: Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

Abstract: Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity.

Abstract: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

Abstract: Flash memory devices having control circuitry to decrease the magnitude of a source voltage of a first polarity during an erase period to increase the magnitude of a control gate voltage of a second polarity applied during the erase period.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.

Abstract: The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material.

Abstract: A flash memory device is disclosed in which an erase voltage is applied to a well containing flash memory transistors during an erase operation. The well is then discharged toward ground, first by one discharge circuit which discharges the well until the voltage on the well is lower than a snap-back characteristic of a transistor employed in another well discharge circuit. After the well voltage is below the snap-back characteristic of the transistor, the well is discharged by the other discharge circuit.

Abstract: Embodiments of the present invention are directed to an improved EEPROM (electrically erasable programmable read-only memory) in which the memory cells can be selectively erased. The EEPROM comprises a first memory cell having a first control gate and a first source, and a second memory cell having second control gate and a second source. If the first and second control gates are configured to receive a control gate voltage, the first source is configured to receive a first source voltage, and the second source is configured to receive a second source voltage different from the first source voltage so as to erase one of the first and second memory cells and to preserve another of the first and second memory cells.