Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connected to the plurality of bit line select gates. The NAND flash memory also includes a plurality of load devices connected to the plurality of bit lines, respectively. The plurality of load devices are configured to provide load current during read operations.

Abstract: Memories, memory controllers, and computing systems and their methods of operation are disclosed. In some embodiments, a method of accessing a memory includes accessing a first bit line corresponding to a sense amplifier and accessing a second bit line corresponding to the sense amplifier. In some embodiments, a memory controller includes a second memory configured to store data of a second data type. In some embodiments, a method includes operating a memory in a second mode in response to receiving an input to change the operation of the memory from a first mode to the second mode.

Abstract: Methods, systems, apparatus, and program products that can write auditable traces of a data wipe to a storage device are disclosed herein. One method includes performing, by a processor, a set of overwrite operations of a data wipe on a storage device, generating a set of auditable traces for the data wipe, and writing the set of auditable traces to the storage device. Systems, apparatus, and computer program products that include hardware and/or software that can perform the methods for writing auditable traces of a data wipe to a storage device are also disclosed herein.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in the nonvolatile memory to spaces. The write management area is a unit of an area which manages the number of write. The address translation unit translates a logical address of write data into a physical address of a space corresponding to the write data. The write unit writes the write data to a position indicated by the physical address in the nonvolatile memory. The control unit controls the spaces individually with respect to the nonvolatile memory.

Abstract: An information processing device include: a memory; and a processor coupled to the memory and configured to: receive an access request directed to an access target and sets the access request in any one of a plurality of pending entries each of which includes latency information; issue a command that corresponds to the access request; control issuance of the command on a basis of the latency information of the any one of the pending entries; set a value that indicates latency for the access request in the latency information of the any one of the pending entries; and subtract a predetermined value from the latency information of the any one of the pending entries for each unit of time.

Abstract: In one embodiment, a processing device is coupled to memory components to monitor host read operations and host write operations from a host device coupled to the plurality of memory components. The processing device schedules, using a variable size internal command queue, a predetermined proportion of back-end processing device read and write operations as internal management traffic proportional to a number of the host read operations and a number of the host write operations. The processing device then executes a subset of the host read operations and the host write operations. Following execution of the subset of the host read operations and the host write operations, the processing device executes an internal management traffic operation based on the predetermined proportion.

Abstract: A memory device such as a page mode NAND flash including a page buffer, and an input/output interface for I/O data units having an I/O width less than the page width supports continuous page read with non-sequential addresses. A controller controls a continuous page read operation to output a stream of pages at the I/O interface. The continuous read operation includes responding to a series of commands to output a continuous stream of pages. The series of commands including a first command and a plurality of intra-stream commands received before completing output of a preceding page in the stream. The first command includes an address to initiate the continuous page read operation, and at least one intra-stream command in the plurality of intra-stream commands includes a non-sequential address to provide the non-sequential page in the stream of pages.

Abstract: Exemplary methods, apparatuses, and systems include receiving a read operation directed to an aggressor location. An integrity scan of a victim location of the aggressor location is performed to determine an error value for the victim location. Data from the aggressor location is copied to a cache in response to determining the error value for the victim location satisfies a first error value threshold. The cache is a different type of memory from the aggressor location.

Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.

Abstract: The abstract of the disclosure was objected to because of informality (e.g. format, reference to figures, etc.). See MPEP § 608.01 (b). Please amend the abstract to recite: Non-volatile memory device may include at least an array of memory cells. The non-volatile memory cells may include associated decoding and sensing circuitry and a memory controller. Methods for checking the erasing phase of a non-volatile device may include performing a dynamic erase operation of at least a memory block and storing in a dummy row at least an internal block variable of the dynamic erase operation and/or a known pattern.

Abstract: The programming techniques include the step of providing a memory device that includes a plurality of memory cells that are divided into at least two groups including a first group and a second group. The first group includes memory cells that are coupled to full select gate drains (SGDs), and the second group includes memory cells that are coupled to partial SGDs. The method continues with the step of applying a programming voltage to a selected word line that includes at least one memory cell of the first group and at least one memory cell of the second group. Simultaneous to the application of the programming voltage, the method continues with applying voltages to bit lines coupled to memory cells. The voltages being determined based on if the memory cells are of the first group or are of the second group.

Abstract: Techniques for reducing write amplification in solid state storage are disclosed. A storage device includes single-level cell (SLC) and multi-level cell (MLCs) portions. A controller may allocate for storage in the SLC portions a sequential closed block pool for sequential data and a random closed block pool for random data. Responsive to certain conditions, the controller may relocate the sequential and random data from the respective sequential and random closed block pools to the MLC portions. The sequential data are relocated prior to the random data. Delaying relocation of random data reduces valid count at the relocation time, reducing write amplification and improving random reads.

Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

Abstract: A fan system and a monitoring method are provided. The fan system includes a fan device and a controller. The fan device includes a fan unit, a detector, and a memory. The detector detects an operating state of the fan unit during operation to obtain operating raw data corresponding to the operating state. The memory records the operating raw data and stores a data protocol. The controller provides a monitoring request to allow the memory to provide the operating raw data and a data protocol to the controller, converts the operating raw data into operating state data through the data protocol, and provides an early warning notification signal according to the operating state data. When the operating raw data is provided to the controller, the operating raw data stored in the memory is erased.

Abstract: Systems and methods are disclosed for using a color changing surface to display a status of a storage device. In certain embodiments, a storage includes a display-less enclosure, non-volatile memory, memory configured to store firmware, and control circuitry. The control circuitry can be configured to determine an available space in the non-volatile memory, determine a first color corresponding to the available space based on a mapping of ranges of available space to corresponding colors, apply a voltage to the electrochromic material to change the color changing surface to the first color, and cease application of the voltage to the electrochromic material, wherein the color changing surface retains the first color after cessation of the voltage.

Abstract: Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

Abstract: A memory device includes a cell string, a peripheral circuit and a control logic. The cell string includes a select transistor and a plurality of memory cells, and further includes a plurality of dummy cells, wherein the plurality of dummy cells are coupled in series between the select transistor and the plurality of memory cells. The peripheral circuit configured to perform a dummy program operation on the plurality of dummy cells. The control logic configured to control the peripheral circuit so that the plurality of dummy cells have different threshold voltage distributions during the dummy program operation.

Abstract: The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.

Abstract: The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access. A method for retrieving data from the memory component is also disclosed.

Abstract: A memory device having an improved threshold voltage distribution includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform an erase operation on the memory block; and control logic configured to: control the peripheral circuit to suspend the erase operation in response to a suspend command received from an external source, determine an erase state of the plurality of memory cells by using a plurality of erase state verify voltages in response to a resume command received subsequently to the suspend command, and determine a level of an erase voltage to be applied to the memory block and an erase voltage applying time for which the erase voltage is to be applied based on the determination result.

Abstract: A semiconductor memory device includes first conductive layers stacked on a substrate; second conductive layers stacked on the substrate and apart from the first conductive layer in a direction; third conductive layers stacked on the substrate and electrically connected to the first and second conductive layers; first insulating layers arranged in the direction to sandwich the first conductive layers; second insulating layers arranged in the direction to sandwich the second conductive layers; slit regions that sandwich the third conductive layers; and memory pillars disposed on the first and second insulating layers. The slit region is disposed between an end portion of one of the first insulating layers and an end portion of one of the second insulating layers.

Abstract: Apparatus, media, methods, and systems for data storage systems and methods for improved recovery after a write abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.

Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.

Abstract: A semiconductor memory device capable of smoothing the number of cycles of programming/erasing between blocks is provided. The semiconductor memory device includes: a memory cell array; an address translation table defining a relationship between logical address information and physical address information; an invalid block table managing the physical address information for identifying to-be-erased blocks of the blocks; a free block table managing the physical address information used for identifying erased usable blocks; an erasing element for erasing the blocks; a controller. When an erasing command and first logical address information are received from environment, the controller erases the block of the physical address information selected from the invalid block table, and rewrites the address translation table in a manner that the physical address information selected from the free block table corresponds to the first logical address information received from the external environment.

Abstract: During a power-on self-test (POST), the BIOS of an information handling system may read a percentage remaining of a persistent memory device. If the percentage remaining satisfies a threshold, the BIOS may provide a message recommending that the persistent memory device be replaced, or automatically swapping the namespaces between two sets of persistent memory devices based on the write endurance remaining threshold.

Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes: a host interface configured to receive a format request from a host, and output an internal format request including initial logical unit information; and a flash translation layer configured to initialize a map table for storing information on mapping between logical and physical unit numbers according to the initial logical unit information.

Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.

Abstract: An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a control signal, wherein the control signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the control signal for providing the boosted intermediate voltage; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.

Abstract: Methods for classifying data in a storage device are provided. A data classifier module in a controller calculates a placement factor of one or more streams of data associated with one or more logical block addresses based on a metadata update and recency count table. The data classifier module then classifies the one or more streams of data associated with one or more logical block addresses as hot, warm, or cold streams of data. Hot streams of data are routed to hot open memory blocks, warm streams of data are routed to warm open memory blocks, and cold streams of data are routed to cold open memory blocks. Routing streams of data to hot, warm, or cold open memory blocks results in more efficient garbage collection procedures and the reduction of block erasures.

Abstract: A system and method for controlling a SSD in response to a power failure event of a main power supply to the SSD. The method includes receiving and storing write commands and associated data payloads for execution on the SSD in volatile memory, detecting the power failure event on the SSD, supplying backup power to the SSD during the power failure event, and executing one or more write commands stored in the volatile memory by storing the associated data payloads in a non-volatile memory on the SSD using the backup power. In response to the execution, removing the one or more write commands from the cache such that one or more unexecuted write commands and the associated data payloads remain in the cache, and storing a list of the one or more unexecuted write commands, but not the associated data payloads, in non-volatile memory using the backup power.

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

Abstract: An electronic apparatus including flash memory and a flash controller is provided. The flash controller is coupled to the flash memory and used to manage data access to the flash memory. The flash controller includes a timer, memory and a microcontroller coupled to the timer and the memory. The timer is used to generate clock interrupts. The memory is used to retain for a predetermined period of time a list of entries of data programmed into the flash memory. Upon each clock interrupt, the microcontroller is used to write an entry of data being programmed into the flash memory to update the list of entries.

Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.

Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.

Abstract: A memory device and an operating method of the memory device is disclosed. The memory device includes a memory cell array including a plurality of memory blocks. The memory device further includes a peripheral circuit for performing an erase voltage application operation, a first erase verify operation, and a second erase verify operation on a selected memory block among the plurality of memory blocks. The memory device also includes a control logic for setting a start erase voltage of an erase operation, based on a result of the first erase verify operation, and controlling the peripheral circuit to perform the second erase verify operation when it is determined that the first erase verify operation on the selected memory block has been passed.

Abstract: The memory device includes multiple stacked layers of memory cells. Each of the layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The first memory cells and the second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer. Gate conductor layers in the same memory cell layer are integral with each other.

Abstract: The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.

Abstract: A RAID-enabled solid state drive (SSD) including: a controller connected to a plurality of channels; a plurality of flash chip groups, each including a plurality of flash chips coupled to the plurality of channels, the plurality of flash chips including: a plurality of non-parity flash chips; and i parity flash chips, wherein the controller is configured to write data to the plurality of flash chip groups such that within each of the plurality of flash chip groups only i or less flash chips of the plurality of flash chips are allowed to be written to at the same time, where i is an integer equal to 1 or more.

Abstract: A method of programming a flash memory device includes selecting a first wordline of a plurality of wordlines to select a selected wordline, the selected wordline corresponding to a target memory cell and performing a programming loop. The programming loop includes applying a program voltage to the selected wordline and performing a verification to the target memory cell. The verification includes applying a pre-pulse voltage to the selected wordline, applying a plurality of pass voltages to unselected wordlines of the plurality of wordlines, after applying the pre-pulse voltage, applying a series of incremental verifying voltages to the selected wordline, and after applying the pre-pulse voltage, applying a floating voltage to a second wordline of the plurality of wordlines. The second wordline being adjacent to the selected wordline is programmed after the selected wordline.

Abstract: Embodiments are directed towards apparatuses, methods, and systems for a codeword distribution manager to divide a codeword into portions to be written to individual storage units and read from the corresponding different individual storage units to reduce a raw bit error rate (RBER) related to storage of the codeword. In embodiments, the codeword distribution manager is included in a memory controller and the plurality of individual storage units are coupled to the memory controller and include individual memory die or individual pages of a memory die. In embodiments, the codeword is a single codeword and includes encoded data and an error correction code. In some embodiments, the codeword includes a low density parity data check code (LDPC). Additional embodiments may be described and claimed.

Abstract: There is disclosed a technique for use in optimizing write operations for flash devices. A system having a plurality of flash based solid state drives receives a write request to overwrite existing data stored on the solid state drives with new data. The write request data is formatted using a write granularity having a first size and the solid state drives are configured with a write granularity having a second size. Corresponding existing data is retrieved. The new data and the existing data are subdivided into multiple corresponding subunits where each subunit has a size equal to the second size. Each new data subunit is compared with each corresponding existing data subunit to identify which new data subunits include modified data. The new data subunits identified as having modified data are written to corresponding locations on the solid state drives.

Abstract: The memory controller includes a register allocator for dividing one super block into a plurality of unit areas, a plurality of first counters each corresponding to a respective one of the plurality of unit areas, wherein each of the plurality of first counters increments a count value when a corresponding unit area is read accessed, a second counter corresponding to the super block, wherein the second counter increments a count value when a count value of any of the first counters reaches a first threshold value, and a command generator for generating a command for performing a read reclaim operation when the count value of the second counter reaches a second threshold value.

Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.