Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.

Abstract: A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.

Abstract: A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Abstract: Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one particular exemplary embodiment, the techniques may be realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections that provides access to the memory module, a second set of interface connections that provides access to the memory module, and memory access circuitry that provides memory access signals to the memoory module for selecting between a first mode wherein first and second portions of the memory core are accessible through the first and second sets of interface connections, respectively, and a second mode wherein both the first and second pertions of the memory core are accessible through the first set of interface connections.

Abstract: The present invention relates to a nonvolatile semiconductor memory, that is, a flash memory and especially to a NAND type flash memory device capable of selectively controlling data input/output units by an address control. In the NAND type flash memory device, a memory cell array is divided into a plurality of blocks, and a data input/output path is selectively controlled by a predetermined data rate option and introduced addresses to perform data input/output operations at a ×8 or ×16 speed in one chip.

Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Abstract: There is provided a control circuit which instructs, using a control signal, validation and invalidation of operations of an input/output interface circuit suitable for a bus such as the IIC bus and maintains an output element included in the input/output interface circuit to the OFF stage without relation to voltage change at the external terminal corresponding to the input/output interface circuit in response to invalidation of operation due to the control signal. Accordingly, a semiconductor device which can be used flexibly with a simplified structure and prevents erroneous output in the output circuit corresponding to the IIC bus can be obtained.

Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner, data is read from a magnetoresistive memory module in both row and column directions.

Abstract: A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.

Abstract: Disclosed is a virtual dual-port synchronous RAM device, system, and method, wherein the design requires minimal hardware cost compared with a dual-port RAM architecture or the traditional architecture used with a single-port RAM. Disclosed is a read/write memory device including means to accept signals from a first host and a second host, the first host having a first clock and the second host having a second clock, the signals including a first clock signal and a second clock, a clock switching means for switching between the first clock signal and the second clock signal, a single-port random access memory (RAM) module for storing data, and a RAM clock for synchronizing the clock signals with the RAM module.

Abstract: A semiconductor memory device having a bank for storing a data and a port as a data I/O terminal includes a global data bus for flowing an appearing current corresponding to the a data; a plurality of first transceivers, in response to the inputted instruction, for delivering the data between a bank to the global data bus; a plurality of first switching blocks, each for selectively connecting the global data bus to each of the plurality of first transceivers; a plurality of second transceivers, in response to the inputted instruction, for delivering the data between a port and the global data bus; and a plurality of second switching blocks, each for selectively connecting the global data bus to each of the plurality of the second transceivers.

Abstract: An integrated memory circuit and corresponding method for segmenting bit lines are provided, where the integrated memory circuit includes a sense amplifier, a layered bit line in signal communication with the sense amplifier, several segment pass transistors in signal communication with the layered bit line, several segmented bit lines, each in signal communication with a corresponding one of the several segment pass transistors, respectively, several memory cell pass transistors in signal communication with one of the several segmented bit lines, and a plurality of memory cell capacitors, each in signal communication with a corresponding one of the plurality of memory cell transistors, respectively; and where the corresponding method for segmenting bit lines includes receiving a memory cell address, activating a memory cell pass transistor with a wordline corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a segmented bit line through the memory cell tra

Abstract: In a read operation, for example, 32 sense amplifiers read 32 pieces of data in a group. After that, the read data is outputted on a 4-bit unit basis. A memory cell array operates at a low frequency which is ? of an actual data output frequency. On the other hand, in a write operation, data is transferred from the outside to a semiconductor memory device bit by bit every cycle. Consequently, by providing a number of latches of a pipeline in a write access path, the writing operation is enabled even at a high frequency. Specifically, at the time of reading, a memory array operates at a low frequency which is ? of a data output frequency. At the time of writing, data is written every clock.

Abstract: An integrated circuit including operational circuitry operable in response to at least one control signal asserted to an external node from an external source, and test circuitry coupled to the external node and the operational circuitry. In response to data asserted to the external node from an external source, the test circuitry enters a test mode in which it tests, configures, or reconfigures the operational circuitry. The test circuitry also asserts to the operational circuitry each control signal received at the external node (or an amplified or translated version thereof). Other aspects of the invention include test circuitry for use in a circuit having an access node and methods for performing on-chip testing, configuration, and control of operational circuitry within a chip in response to test data and at least one control signal asserted from an external source to an external node.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.

Abstract: A memory architecture for a disk drive system in which (Synchronous Random Access Memory) SRAM and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. The SRAM is an “on-board” memory component, meaning that it is embodied on an integrated circuit that also includes a hard disk controller (HDC) and other disk drive components, while the DRAM is located on a separate integrated circuit externally, i.e., “off-board,” of the integrated circuit containing the SRAM. The SRAM includes a random access (RA) block that provides all RA functions, while the DRAM includes a direct memory access (DMA) block that provides all DMA functions.

Abstract: A method of writing data bits to a memory array. In one method embodiment, a first input is received. This causes an application of high power, via a sense line, to an addressed bit in the memory array and causes a write operation to be applied to the addressed bit. A second input is received. This causes an application of low power, via said sense line, to the addressed bit and causes a read operation on the addressed bit. The sense line is used to read and write the addressed bit.

Abstract: A semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data in which the operation of one cell in a pair cell can be checked. At normal operation time data can be read from or written to a desired cell by activating two word lines at a time. On the other hand, at operation test time data can be read from or written to only one cell in a pair cell by activating a desired word line.

Abstract: A single bit line, pulse-operated memory cell. The memory cell includes a first and second inverter, write access and feedback-control transistors, and read access transistor and read buffer transistors. The output of the first inverter is connected to the input of the second inverter and the output of the second inverter is connected to the input of the first inverter through the channel of the feedback-control transistor. The write access and feedback-control transistors are opposite types, and their gates are connected together so that when the feedback control transistor is on the write-access transistor is off and visa versa. Writing the cell thus avoids contending the with the on-transistor of the second inverter. The output of the cell is sensed by the gate of the buffer transistor and coupling the output of the buffer transistor through the read access transistor to the read output line.

Abstract: A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

Abstract: A test device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices. A quadrilateral active area is disposed in the scribe line region, with four equilaterals and four vertex angles. Parallel first and second deep trench capacitors are disposed in the quadrilateral active area. The first deep trench capacitor has a first surface aligned with a second surface of the second deep trench capacitor. The first and second vertex angles of the four vertex angles have a diagonal line essentially perpendicular to the first and second surfaces. The first and second vertex angles are a predetermined distance from the first surface and the second surface respectively.

Abstract: A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Abstract: A semiconductor chip is provided, with which presence of dead pins can be easily noticed and a process for controlling the potential at dead pins can be performed easily. An input/output controller (IOC) for coordinating the input/output of signals through individual pins (PN1 to PN8) includes an input/output buffer (BFa) and the input/output buffer (BFa) includes a switch (SW4a) and a switch (SW4b). A setting memory (STMa) for storing settings for control of the input/output of signals in the input/output buffer (BFa) contains a memory table and the memory table contains an item about the dead pin potential control process so that a power-supply potential (Vdd) or a ground potential (GND) can be applied to the dead pins, i.e. the fourth pin (PN4) and the fifth pin (PN4).

Abstract: A spare column on which spare memory cells are arranged is provided in a memory cell array. In the memory cell array, address assignment can be altered so that sub-word lines selected collectively according to the same row address is divided into the right and left halves. The alteration in assignment can be realized by disconnecting a fuse element incorporated in a SD generating circuit. Even in a case where a plurality of defective memory cells are concentrated on the same memory cell row, the number of defective memory cells in a select unit corresponding to row address can be altered by alteration in address assignment so as to be reduced as a result of distribution; thereby enabling increase in number of chips that can be saved with spare memory cells. Accordingly, improvement on saving rate for defective chips can be realized without increasing the number of spare memory cells.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

Abstract: Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory module for storing data thereon. The memory module comprises a memory component having a first set of interface connections for providing access to a memory core of the memory component and a second set of interface connections for providing access to the memory core of the memory component. The memory module also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interconnects of a synchronous dynamic random access memory device. The synchronous flash memory device, however, comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory. In one embodiment, the synchronous non-volatile memory device has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal, and a chip select connection (CS#) to receive a chip select signal.

Abstract: A semiconductor memory device employs a power supply system in which a first power supply voltage supplied to a cell area is separated from a second power supply voltage supplied to a peripheral circuit area. Particularly, during a wafer burn-in test operation mode, the first power supply voltage supplied to the cell area is higher than the second power supply voltage supplied to the peripheral circuit area. If a wafer burn-in test operation is performed under the second power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be shut off.

Abstract: An electronic system includes a memory module configured to operate in multiple modes. The memory module includes at least one connection configured to perform different functions when the memory module is operating in different modes. In one embodiment, the memory operates in a normal mode and an SPD mode. While in SPD mode, the connection performs one or more SPD functions, such as operating as an SMBus interface connection. In normal mode, the connection serves a function associated with normal operation of the module, such as addressing functions.

Abstract: A memory module includes a memory device, a connector, a plurality of lines coupling the memory device and the connector, and termination circuitry coupled to at least a subset of the lines. A method for terminating a memory bus includes providing at least two expansion sockets coupled to the memory bus; interfacing two expansion memory modules including termination circuitry with the expansion sockets; and disabling the termination circuitry for one of the expansion memory modules.

Abstract: A semiconductor memory has a data signal path and a control device in order to supply functional elements of the data signal path with control signals. Programmable delays are connected into the signal lines providing the control signals, so that the time relationships between the control signals can be set reversibly via a soft set register or irreversibly via fuses. This enables simple adaptation of the internal control signal timing to fluctuations in the fabrication process or after conversion of the configuration to a new fabrication process.

Abstract: A growable multibank DRAM macro is achieved with a flexible multibank interface which can be grown without redesign and without change of appearance/behavior to the customer. The interface is preferably characterized by the presence of bank select inputs (pins) which permit selection of one or more banks of the macro. The banks preferably each have respective row decode circuitry and respective limited repair redundancy.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output cell data read from the memory cell array, a test mode setting circuit which sets a test mode to monitor a plurality of timing signals which control input/output operation timing of the cell data, and switch circuits connected to the plurality of input/output terminals. The switch circuits simultaneously output the plurality of timing signals from the plurality of input/output terminals in the test mode.

Abstract: A flash memory array structure that has independently operating memory arrays. In one embodiment, a flash memory device comprises a poly silicon layer, a first metal layer and a second metal layer. The poly silicon layer has a plurality of word lines formed therein. The word lines are coupled to rows of memory cells. The first metal layer has a plurality of local bit lines formed therein. The local bit lines are coupled to columns of memory cells. The second metal layer has a plurality of global bit lines formed therein. The global bit lines are selectively coupled to the plurality of local bit lines. The global bit lines are further selectively bisected during manufacture to form a first bank and a second bank of memory cells. The first and second banks allow concurrent memory operations to be performed on the flash memory device.

Abstract: A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line contacts in the memory regions simultaneously. The memory deices and test may have the same alignment shift between bit line contacts and bit line due to use of the same masks and process. Thus, alignment of bit lines and bit line contacts in the memory region is determined according to two resistances (R1 and R2) detected by the test device.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.