Abstract: A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

Abstract: A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.

Abstract: A semiconductor device includes a shifted write signal generation circuit, a shifted address generation circuit and a bank address latch circuit. The shifted write signal generation circuit is configured to shift a write signal based on a mode signal to generate a shifted write signal. The shifted address generation circuit is configured to shift an internal address based on the mode signal to generate a shifted internal address. The bank address latch circuit is configured to latch and store the internal address based on the write signal, configured to latch and store the shifted internal address based on the shifted write signal, and configured to generate a write bank address from the stored internal address and the stored address of the shifted internal address.

Abstract: A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword.

Abstract: A data sensing device and a data sensing method thereof are provided. The data sensing device includes a compensation signal generator, a weighting operator and an arithmetic operator. The compensation signal generator receives a basic input signal and a plurality of reference weighting values, and generates a compensation signal according to the basic input signal and the reference weighting values. The weighting operator has a plurality of memory cells, performs a writing operation on the memory cells according to the weighting values based on address information, and the weighting operator generates an output signal by the memory cells by receiving a plurality of input signals. The arithmetic operator performs an operation on the output signal and the compensation signal to generate a compensated output signal.

Abstract: A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.

Abstract: According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. The fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

Abstract: An electrically programmable fuse circuit, a programming method for electrically programmable fuse, and a state detection method for electrically programmable fuse are provided. The electrically programmable fuse circuit includes a plurality of fuse cells connected in series, wherein in each of the plurality of fuse cells, one terminal of the fuse cell is connected with a first programming terminal corresponding to the fuse cell, and the other terminal of the fuse cell is connected with a second programming terminal corresponding to the fuse cell via a transistor. Reliability of electrically programmable fuses may be improved.

Abstract: A circuit includes a bit line, a power node having a first power voltage level, a reference node having a reference voltage level, a pass gate coupled between the bit line and the power node, and a driver coupled between the bit line and the reference node. The pass gate couples the bit line to the power node responsive to a first signal, and the driver couples the bit line to the reference node responsive to a second signal. The first signal is based on the first power voltage level, and the second signal is based on a second power voltage level between the reference voltage level and the first power voltage level.

Abstract: Techniques are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages using binary data from the memory, wherein the gap is estimated using statistical characteristics of at least one of two adjacent memory levels of the memory; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels and the gap; and updating the read threshold voltage with the adjusted read threshold voltage. Pages of the memory are optionally read at multiple read threshold offset locations to obtain disparity statistics, which can be used to estimate mean and/or standard deviation values for a given memory level. The gap is optionally estimated using the mean and/or standard deviation values.

Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Abstract: The invention relates to a device (100) for the individualized monitoring of the feed conversion ratio of poultry comprising: a weighing station (30) comprising side walls and a front wall defining an available internal volume able to contain a bird, a bird identification means (40), able to identify one bird positioned in the available internal volume of the weighing station (30) and to provide identification information of the bird, a bird weighing means (10), able to measure the weight of one bird positioned in the available internal volume of the weighing station (30) and to provide weight information of the bird, a feeder (50) containing poultry feed, coupled to a feed weighing means (20) able to measure the weight of the feed contained in the feeder (50) and to provide weight information of the feed, wherein said feeder (50) comprises a dispensing area (51), wherein said dispensing area (51) is accessible only to one bird positioned in the available internal volume of the weighing station (30), and a

Abstract: A method for self-terminated writing with quasi-constant voltage drop across resistive-type memory cell is provided. The method comprises: creating a writing voltage and a writing current flowing through a resistive memory cell; reproducing the writing current to generate a reproduced writing current; flowing the reproduced writing current through a dummy circuit to generate a dummy writing voltage; adding the dummy writing voltage and a reference voltage to generate a reference writing voltage, wherein the dummy writing voltage slightly and proportionally increases during writing; and adjusting the writing voltage and the writing current according to the reference writing voltage so that a voltage drop across the resistive memory cell keeps constant or slightly increases during writing. When the reproduced writing current reaches a predetermined target current value, a termination signal is issued.

Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.

Abstract: A non-volatile memory device includes a page buffer and a control logic. The page buffer includes a plurality of latch sets that latches first results of a plurality of first read operations according to a plurality of read signals. The first read operations identify a single page datum from among a plurality of page data of selected memory cells included in a plurality of memory cells. The control logic selects a portion of the read signals by comparing the first results of the first read operations, and resets remaining read signals that are not selected. The page buffer stores second results of second read operations according to the selected read signals, and third results of third read operations according to the reset remaining read signals.

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Abstract: A method of providing a keyboard input on a touchscreen display of a mobile communication device. The method comprises receiving a plurality of keywords indexed to completion action recommendations by a client keyboard application executing on a mobile communication device, where the completion action recommendations define suggestions for completing a partial keyboard input string, storing the keywords indexed to completion action recommendations on the device, searching the stored keywords by the client keyboard application based on an identity of the application executing on the device that is associated with a keyboard input, based on a current location of the device, and based on at least one word in the partial keyboard input string, and providing a prompt associated with the completion action recommendation found based on the search of the stored keywords on the touchscreen of the device, whereby inputting data via the keyboard to the application executing is promoted.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a memory device including a plurality of memory blocks configured with a plurality of pages, the memory device performing a read operation in units of pages; and a memory controller configured to control the memory device to perform the read operation, wherein the memory device is controlled such that a first initial turn-on time of a turn-on voltage for a first selected page among the plurality of pages and a second turn-on time of the turn-on voltage for subsequently selected pages are different from each other.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes configuring a first interface to exchange data over two primary wires of a serial bus in accordance with a first I3C protocol, and configuring a second interface to communicate over at least one secondary wire in accordance with a second I3C protocol. In one example, the first data is encoded in a sequence of symbols representing signaling state of the two primary wires. A recovered clock signal may be derived from transitions between symbol transmission intervals in the first interface may be used to control double data rate communication through the second interface.

Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes one or more resistive storage cells each structured to exhibit different resistance values for storing data; at least one reference resistance transistor to produce a reference resistance value; a reference resistance adjustment block coupled to the at least one reference resistance transistor and structured to supply a signal to the at least one reference resistance transistor that can cause an adjustment in the resistance value of the reference resistance transistor; and a data sensing block coupled to the one or more resistive storage cells and the at least one reference resistance transistor, the data sensing block structured to sense resistance values of a resistive storage cell selected among the one or more resistive storage cells and the at least one reference resistance transistor and to compare the sensed resistance values to determine data of the selected resistive storage cell.

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

Abstract: A memory device includes a write port, a read port, source lines, bit lines, and word lines orthogonal to the bit lines. The memory device also includes memory cells that can be arrayed in columns that are parallel to the bit lines and in rows that are orthogonal to the bit lines. The memory cells are configured so that a write by the write port to a first memory cell in a column associated with (e.g., parallel to) a first bit line and a read by the read port of a second memory cell in a column associated with (e.g., parallel to) a second, different bit line can be performed during overlapping time periods (e.g., at a same time or during a same clock cycle).

Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.

Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.

Abstract: Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.

Abstract: Examples herein relate to linear transformation accelerators. An example linear transformation accelerator may include a crossbar array programmed to calculate a linear transformation. The crossbar array has a plurality of words lines, a plurality of bit lines, and a memory cell coupled between each unique combination of one word line and one bit line, where the memory cells are programmed according to a linear transformation matrix. The plurality of word lines are to receive an input vector, and the plurality of bit lines are to output an output vector representing a linear transformation of the input vector.

Abstract: A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.

Abstract: Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.

Abstract: A decoding method is provided. The method includes selecting a target word line among a plurality of word lines; respectively reading a plurality of target memory cells of the target word-line by using different X read voltage sets to obtain corresponding X Gray code summation sets; calculating a Gray code count summation difference of the Gray code count summations at the same sequence position respectively in N?1 Gray code count summations between every pair of adjacent Gray code summation sets of the X Gray code summation sets, so as to obtain X?1 Gray code count summation difference sets corresponding to all pairs of the Gray code summation sets; and deciding N?1 optimized read voltages from X*(N?1) read voltages belonging to the X read voltage sets according to the X?1 Gray code count summation difference sets.

Abstract: Instant messaging, also known as chat, is integrated with electronic mail in a user interface that provides for automatic completion of recipient names or addresses, such as email addresses or chat addresses, as a user types characters of the name or address when addressing a message. The automatic completion feature displays a list of matches, which are names or addresses in, for example, the user's online contact list, that match the characters the user types. The matches list may contain names or addresses for multiple different communication methods. The user may then select one of the names or addresses to compose a message to be sent to the selected name or address. A user interface is then provided for composing a message to be sent to the selected name or address using the communication protocol associated with the selected name or address.

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

Abstract: Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of a flip flop of the memory device. After causing the fail point, the DQS signal is shifted in a positive direction relative to the clock. A transition edge of an internal write signal (IWS) is centered in a DQS period, such as a write preamble. The IWS indicates that a write command is to be captured. Moreover, centering the transition edge includes selectively delaying the IWS in the negative direction.

Abstract: According to one embodiment, a memory device includes a memory area; and a control circuit, in response to a first command, configured to read out data from the memory area without outputting the data to a data line, subsequently, in response to a second command, configured to output the data to the data line, if the first command is not received after receiving an active command, in response to the second command, configured to output the data read out from the memory area to the data line.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.

Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.

Abstract: Methods and devices for gating an internal data strobe from an input buffer of a memory device. The gating function occurs after a write operation ceases but before an external controller stops driving an external data strobe that is used to generate the internal data strobe. The methods and devices use local counters to count how many pulses have occurred on the data strobe during a write operation. When the local counters indicate that an expected number of cycles for the write operation have elapsed, the local counters indicate that the write operation has completed. This indication causes gating circuitry to cut off the internal data strobe from writing circuitry.

Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

Abstract: A method of operating a tracking circuit of a memory device includes charging a node of the tracking circuit to a first predetermined voltage level, the first node being electrically coupled with a first load device. A first plurality of tracking cell transistors are activated to discharge the first node toward a second predetermined voltage level. A reset signal is generated based on a signal at the first node. The reset signal may correspond to a waiting period for reading a memory cell of the memory device.

Abstract: Processing visual cues to improve understanding of an input is described herein, including receiving a visual cue, the visual cue including visual media of a target; storing a list of words representing the target; and updating a probable words dictionary to include the list of words.

Abstract: A memory system includes a first memory bank, a first path selector, a second memory bank, a second path selector, and a sensing device. The first memory bank includes a plurality of first memory cells. The second memory bank includes a plurality of second memory cells. The first path selector includes a plurality of input terminals coupled to the first memory cells through a plurality of first bit lines, and two output terminals. The second path selector includes a plurality of input terminals coupled to the second memory cells through a plurality of second bit lines, and two output terminals. The sensing device is coupled to the output terminals of the first bank selector and the second bank selector, and senses the difference between currents outputted from two of the reference current source, and the terminals of the two bank selectors according to the required operations.

Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

Abstract: Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.

Abstract: A sense amplifier may be provided. The sense amplifier may include an amplification circuit and/or a cell current control circuit. The amplification circuit may be configured to compare a voltage level of a signal line with a level of a read voltage. The cell current control circuit may be configured to decrease the voltage level of the signal line based on an output signal.

Abstract: Large lists of domain-specific terms are classified as a particular kind of linguistic object, e.g., lexical answer type T versus canonical answer E, based on features from a domain-specific corpus which have been found to distinguish between the linguistic objects. The distinguishing features can be identified in the corpus based on sets of the linguistic objects derived from question-and-answer pairs. A classifier can be trained using the distinguishing features, and the classification carried out using that classifier. The distinguishing features can include one or more syntactic features or one or more lexical features. The linguistic objects (the T and E training sets) can be extracted from the question-and-answer pairs automatically via text analysis if manually curated lists are not available. The classified terms can be included in a domain-specific lexicon which facilitates a deep question answering system to yield an answer to a question.

Abstract: Large lists of domain-specific terms are classified as a particular kind of linguistic object, e.g., lexical answer type T versus canonical answer E, based on features from a domain-specific corpus which have been found to distinguish between the linguistic objects. The distinguishing features can be identified in the corpus based on sets of the linguistic objects derived from question-and-answer pairs. A classifier can be trained using the distinguishing features, and the classification carried out using that classifier. The distinguishing features can include one or more syntactic features or one or more lexical features. The linguistic objects (the T and E training sets) can be extracted from the question-and-answer pairs automatically via text analysis if manually curated lists are not available. The classified terms can be included in a domain-specific lexicon which facilitates a deep question answering system to yield an answer to a question.

Abstract: An aspect of auto-completion of text entered by a user includes configurable data collection components that collect from software applications text data and metadata representing an initial state of each of the applications and text data and metadata representing changes to the state of one or more of the applications. A central text matching component receives and stores the text data and metadata. A sending component sends text entered by the user in a text-entry field and any metadata associated with it to the central text matching component. A comparison component compares the entered text and associated metadata to the stored text data and metadata and locates matching text strings. A weighted ordering component ranks the matching text strings using the metadata and its configuration settings. A completion component completes the entered text at the text-entry field based on a selection of one of the located matching text strings.

Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.

Abstract: Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.