Abstract: A nonvolatile memory, such as a write-once memory, includes a memory cell array that has first memory cells and at least one second memory cell. The memory also includes a first writing circuit that is capable of writing data to the first memory cells and the second memory cell, a second writing circuit, and a verify circuit which is capable of confirming whether the data is normally stored in the first memory cells. When the writing of data to one of the first memory cells fails, the second writing circuit is arranged to assign an address of the one of the first memory cells to the second memory cell. The first memory cells and the second memory cell are arranged to irreversibly change their electrical resistance when the data is stored in them. The first memory cells and the second memory cell include an organic compound layer interposed between a pair of electrodes.

Abstract: A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.

Abstract: A refresh control circuit and a method for refreshing control of a semiconductor memory device are described. The refresh control circuit includes a sense amplifier control circuit configured to generate a sense amplifier driving signal by selectively applying a first delay time and a second delay time (first delay time+third delay time) in response to a sense amplifier enable signal and a refresh command signal (or refresh fail detect signal), and a sense amplifier driver configured to output a sense amplifier driving voltage by applying the first delay time or the second delay time according to a mode.

Abstract: Display data is read out from a display memory in parallel, and is temporarily held in a first shift register located near to the display memory. The display data is serially read out and transferred from the first shift register in one bit unit to a second shift register located near to an display data latch, in synchronism with a shift clock signal outputted from a shift clock controlling circuit. The display data held in the second shift register is outputted in parallel to the display data latch in accordance with a display data read signal. Thus, it is possible to reduce the increase of the number of the wiring lines extending from the display memory to the display data latch, as well as the increase of the chip area, both of which would be caused by the increase of the display segments. It is also possible to reduce the limitations related to the arrangement of the interior of the microcomputer.

Abstract: Microcircuit chip packages mounted modules are connected together by lossy strip transmission lines parallel to a ground plane without termination. The transmission line segments are designed to have a total resistance R.sub.L which is within the range between two-thirds and two times the characteristic impedance Z.sub.o of the transmission line. Reflections are prevented from causing signal problems by maintaining R.sub.L above the minimum value. Similarly, the maximum value is intended to prevent deterioration of the wave shape.