Abstract: Techniques are disclosed relating to compressing database keys. A computer system may receive a request to write a database record to a storage medium. The database record may include a database key and a corresponding data value. The computer system may compress the database key by replacing a portion of the database key with particular data that identifies a location of a reference database key and an amount of similarity determined between the database key and the reference database key. The computer system may write the database record to the storage medium. The database record may include the compressed database key and the corresponding data value.

Abstract: Memory devices may perform read operations and write operations with different bit error correction rates to satisfy a bit error correction rate. However, improving the bit error correction rate of the memory device using a single type of read command and/or write commands may result in longer read and write commands. Moreover, using longer read and write commands may result in undesirable higher memory power consumption and may reduce memory throughput. Accordingly, memory operations are described that may use combination of commands with increased bit error correction capability and reduced bit error correction capability. For example, the read operations may use multiple (e.g., at least two) sets or groupings of read commands and the write operations may use multiple (e.g., at least two) sets or groupings of write commands.

Abstract: The present disclosure provides a display substrate which includes: a plurality of pixel units, at least one of which includes a light emitting diode and a drive circuit. The light emitting diode includes a cathode; the display substrate further includes an auxiliary electrode layer including at least one auxiliary electrode. The auxiliary electrode is disposed in at least one of the pixel units. The auxiliary electrode is electrically connected with the cathode of the light emitting diode which is located in the same pixel unit as the pixel unit that the auxiliary electrode is located in, and the auxiliary electrode covers at least a portion of the drive circuit in the pixel unit that the auxiliary electrode is located in. The auxiliary electrode is made of an opaque conductive material, so as to block light irradiated at the portion of the drive circuit that is covered by the auxiliary electrode.

Abstract: A video sequence may be generated that animates user interactions across a number of different user interfaces for an application. Visual representations of the user interfaces can be combined together into an image that acts as a canvas or background for the video sequence. A record of user interactions with the user interfaces can be mapped to locations on the canvas, and the video sequence can be generated that incrementally animates user actions as they move between different containers or controls in the user interfaces. The animation may show individual users or aggregated user groups represented by graphics that move across the user interfaces to form a path represented by connectors and arcs.

Abstract: In one aspect, an apparatus includes a memory repair controller coupled to a memory. The memory repair controller may be configured to provide repair information to cause the memory to disable one or more faulty locations in the memory, and the memory repair controller can be disabled after providing the repair information.

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.

Abstract: Provided are a solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus. A memory part is formed using an SRAM serving as an ADC memory, and an ADC code is written into and read from the memory part under control of a reading part. In the SRAM, a power gating transistor is additionally provided to both of a power supply node (between a power supply and a virtual power supply node) and a ground node (between a virtual reference potential node and a reference potential) for the purposes of blocking the shoot-through currents from the bit cells during the writing operation. The power gating transistors are controlled by the reading part so as to operate as either a weak current source or switch.

Abstract: An integrated grid cell on an integrated circuit (IC) is disclosed. The integrated grid cell corresponds to at least one of an integrated one-grid cell and an integrated two-grid cell. The integrated grid cell includes various polysilicon layers, metal-0 oxide diffusion (M0OD) layers, and a metal-0 polysilicon (M0PO) layer. The polysilicon layers, the M0OD layers, and the M0PO layer are formed such that potential differences are created between one or more polysilicon layers and one or more M0OD layers. Such potential differences between the one or more polysilicon layers and the one or more M0OD layers lead to formation of various parasitic capacitors between the one or more polysilicon layers and the one or more M0OD layers. The parasitic capacitors correspond to decoupling capacitors that mitigate a dynamic IR drop and a supply noise associated with the IC.

Abstract: A semiconductor memory device includes a logic circuit disposed on a substrate having a cell region and a peripheral region outside the cell region; a source plate defined over the logic circuit; a slit separating the source plate into a cell source plate in the cell region and a dummy source plate in the peripheral region; and a memory cell array defined on the cell source plate. The dummy source plate is maintained at a constant voltage independent of operations of the memory cell array and the logic circuit.

Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.

Abstract: A nanotube spectrometer array includes: a substrate including block receivers; photodetectors arranged in an array with each photodetector including: a single wall carbon nanotube disposed on the substrate in a block receiver and disposed laterally along the block receiver; a source electrode on the single wall carbon nanotube; a drain electrode on the single wall carbon nanotube, such that the source and drain electrodes are separated from each other by a photoreceiver portion of the single wall carbon nanotube; and a gate electrode disposed on the substrate such that substrate is interposed between the gate electrode and the single wall carbon nanotube. The single wall carbon nanotube in each photodetector is a different chirality so that each photodetector absorbs light with a maximum photon absorptivity at a difference wavelength that is based on the chirality of the single wall carbon nanotube of the photodetector.

Abstract: Techniques are disclosed relating to compressing database keys. A computer system may receive a request to write a database record to a storage medium. The database record may include a database key and a corresponding data value. The computer system may compress the database key by replacing a portion of the database key with particular data that identifies a location of a reference database key and an amount of similarity determined between the database key and the reference database key. The computer system may write the database record to the storage medium. The database record may include the compressed database key and the corresponding data value.

Abstract: An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first low-voltage junction formed in the substrate, and a second low-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first low-voltage junction and the second low-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third low-voltage junction formed in the substrate, and a fourth low-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third low-voltage junction and the fourth low-voltage junction.

Abstract: An electronic system may include one or more units of processing circuitry configured to implement a main intellectual property (IP), a checker IP, and an error detection circuit. The main IP includes a first data path and a first control signal path. The checker IP includes a second control signal path. The error detection circuit is configured to detect an error of data by performing error correction code (ECC) decoding of output data that is output by the main IP to the error detection circuit through the first data path, and detect an error of a control signal based on a first signal that is output by the main IP to the error detection circuit through the first control signal path, and a second signal that is output by the checker IP to the error detection circuit through the second control signal path.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.

Abstract: A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.

Abstract: A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.

Abstract: Methods, systems, and devices for cell voltage accumulation discharge are described. One or more sections of a bank of ferroelectric memory cells may be coupled with one or more access lines. By activating one or more switching components, one or more sections (that may include a memory array and/or a driver) of memory cells may be isolated. When isolated, a voltage may be applied across an access line associated with the section to activate an access device of each memory cell. By activating a switching component of a respective memory cell, a capacitor of the memory cell may be discharged and then the isolated section may be coupled with the plurality of access lines.

Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.

Abstract: Examples of the present disclosure relate to a device, method, and medium storing instructions for execution by a processor for refreshing memory blocks of solid state memory through a temperature compensated refresh rate. Techniques discussed herein include a solid state memory to store data and a temperature sensor to identify a temperature of the solid state memory. The memory device with solid state memory also includes a memory controller that periodically refreshes memory blocks of the solid state memory at an adjustable refresh rate, wherein memory controller is to adjust the adjustable refresh rate based on the temperature of the solid state memory.

Abstract: A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a first logical distance value between a first physical unit and a second physical unit among the physical units, and the first logical distance value reflects a logical dispersion degree between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit; and performing a data merge operation according to the first logical distance value, so as to copy valid from a source node to a recycling node.

Abstract: A vehicular device includes: a function processing unit that executes an application software; a volatile memory that temporarily stores a backup data; and a backup processing unit that copies the backup data from the volatile memory to a non-volatile memory when an event for terminating an operation occurs. The function processing unit and the backup processing unit execute processes independently, and are accessible to a same memory space in the volatile memory, respectively. The function processing unit reads out the backup data from the volatile memory and reboots the application software when an event for maintaining an activation occurs while the backup processing unit is storing the backup data from the volatile memory to the non-volatile memory.

Abstract: A layout structure of a bit line sense amplifier in a semiconductor memory device includes a first bit line sense amplifier which is connected to a first bit line and a first complementary bit line, and is controlled via a first control line and a second control line. The first control line is connected to a first node of the first bit line sense amplifier and the second control line is connected to a second node of the first bit line sense amplifier, and the first bit line sense amplifier includes at least one pair of transistors configured to share any one of a first active region corresponding to the first node and a second active region corresponding to the second node.

Abstract: A set of rotary joint components containing stationary part(s) and rotatable part(s) repositionable with respect to each other. The stationary part has a stationary base with means for holding a stationary carrier into a circular-shaped form. The stationary carrier holds at least a stationary transmitter coupler of a contactless data link, such as a strip line. The stationary carrier is made of sheet metal or plastic material, and therefore can easily be prepared on a plane work bench before it is bent to a ring shape.

Abstract: A dispersed storage and task (DST) processing unit receives a data access request corresponding to a data segment. Range availability information is obtained for a plurality of DST execution units of the DST network. A subset of the plurality of DST execution units is selected based on the range availability information and a threshold number corresponding to the data access request. Execution unit access requests are generated and sent to the subset of the plurality of DST execution units corresponding to a plurality of slices of the data segment, wherein the execution unit access requests include address information that is based on the range availability information.

Abstract: In certain aspects, an apparatus includes a plurality of phase generators configured to generate a first plurality of local oscillator (LO) phase signals, wherein the plurality of phase generators includes a first set of phase generators and a second set of phase generators. The apparatus also includes a duty cycle generator coupled to the plurality of phase generators, wherein the duty cycle generator is configured to receive the first plurality of LO phase signals and to generate a second plurality of LO phase signals by converting a duty cycle of each of the first plurality of LO phase signals. The first set of phase generators is located adjacent to a first side of the duty cycle generator and the second set of phase generators is located adjacent to a second side of the duty cycle generator, the second side being opposite the first side.

Abstract: A storage system includes a plurality of storage nodes. The storage node includes: one or more storage devices which respectively provide a storage area; and one or more control software which read/write requested data from/into the corresponding storage device according to a request from a higher-level device, wherein each of the control software retains predetermined configuration information required for reading/writing requested data from/into the corresponding storage device according to a request from the higher-level device, wherein a plurality of the control software are managed as a redundancy group, and the configuration information retained in each of the control software belonging to the same redundancy group is synchronously updated, and wherein the plurality of control software configuring the redundancy group are each deployed in respectively different storage nodes so as to distribute a load of each of the storage nodes.

Abstract: A graphene structure is provided. The graphene structure comprises a substrate layer and at least two graphene layers disposed on the substrate. The at least two graphene layers comprises a gate voltage tuned layer and an effective graphene layer and the effective graphene layer comprises one or more graphene layers. A magnetoresistance ratio of the graphene structure is determined by a difference in a charge mobility and/or a carrier density between the gate voltage tuned layer and the effective graphene layer. The charge mobility and/or the carrier density of the gate no voltage tuned layer is tunable by a gate voltage applied to the graphene structure. A magnetic field sensor comprising the graphene structure is also provided.

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

Abstract: A retention mechanism of a dual-body computing system, including a bracket coupled to a first body of the computing system, the bracket translates along a first direction, wherein a cable assembly is attached the bracket; and springs coupled to the bracket to facilitate translating of the bracket along the first direction, wherein, as the bracket progresses from a first state to a second state based on a positioning of each body of the dual-body computing system, the first and the second springs exert an increasing force on the bracket to maintain a level of tension on the cable assembly; wherein, as the bracket progresses from the second state to the first state based on the positioning of each body of the dual-body computing system, the first and the second springs exert a decreasing force on the bracket to retract the cable within one of the bodies of the computing system.

Abstract: A set of rotary joint components containing stationary part(s) and rotatable part(s) repositionable with respect to each other. The stationary part has a stationary base with means for holding a stationary carrier into a circular-shaped form. The stationary carrier holds at least a stationary transmitter coupler of a contactless data link, such as a strip line. The stationary carrier is made of sheet metal or plastic material, and therefore can easily be prepared on a plane work bench before it is bent to a ring shape.

Abstract: A computer system identifies high-value information in data streams. The computer system receives a filter graph definition. The filter graph definition includes a plurality of filter nodes, each filter node including one or more filters that accept or reject packets. Each respective filter is categorized by a number of operations, and the one or more filters are arranged in a general graph. The computer system performs one or more optimization operations, including: determining if a closed circuit exists within the graph, and when the closed circuit exists within the graph, removing the closed circuit; reordering the filters based at least in part on the number of operations; and parallelizing the general graph such that the one or more filters are configured to be executed on one or more processors.

Abstract: A magnetic device may include a composite free layer that includes a first sub-layer comprising at least one of a Co-based alloy, a Fe-based alloy, or a Heusler alloy; a second sub-layer comprising at least one of a Co-based alloy, a Fe-based alloy, or a Heusler alloy; and an intermediate sub-layer between the first sub-layer and the second sub-layer. The composite free layer exhibits a magnetic easy axis oriented out of a plane of the composite free layer.

Abstract: Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described.

Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.

Abstract: A system and method for leakage current detection and fault location identification in a DC power circuit is disclosed. The system includes a plurality of DC leakage current detectors positioned throughout the DC power circuit, the DC leakage current detectors configured to sense and locate a leakage current fault in the DC power circuit. Each of the DC leakage current detectors is configured to generate a net voltage at an output thereof indicative of whether a leakage current fault is present at a location at which the respective DC leakage current detector is positioned. A logic device in operable communication with the DC leakage current detectors receives output signals from each DC leakage current detector comprising the net voltage output and locates the leakage current fault in the DC power circuit based on the output signals received from the plurality of DC leakage current detectors.

Abstract: An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a sense circuit may enable a determination of a current impedance state of a non-volatile memory element while avoiding an unintentional change in the state of the non-volatile memory element.

Abstract: Apparatuses and methods for configuring a memory device using configuration commands are provided. A method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode. Accordingly, Applicant respectfully requests withdrawal of the objection to the Abstract of the application.

Abstract: A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.

Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

Abstract: A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations.

Abstract: A transistor substrate includes a plurality of first transistors formed between a power supply wire and a first conductive wire, and a plurality of second transistors formed between the power supply wire and a second conductive wire. A length of a portion of the power supply wire between the plurality of second transistors and a drive signal generation circuit is longer than a length of a portion of the power supply wire between the plurality of first transistors and the drive signal generation circuit, and a total sum of channel widths of second channels included in the plurality of second transistors is wider than a total sum of channel widths of first channels included in the plurality of first transistors.

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

Abstract: A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate and a pixel electrode electrically connected to an output terminal of the AND gate.

Abstract: A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range.

Abstract: A nonvolatile memory block experiences multiple write-erase cycles during which data is subject to a shaping operation prior to storage. In response to a write-erase cycle count reaching a predetermined number, a polling cycle occurs during which shaping is disabled and data is collected that indicates a condition of the block. Subsequently, shaping is reenabled for subsequent cycles.

Abstract: A memory apparatus and methods are provided for preventing read errors on weak pages in a non-volatile memory system. In one example, a method includes identifying a weak page in a non-volatile memory device along a word line, wherein the weak page is partially written with at least some data; buffering data associated with the weak page to a weak page buffer that is coupled in communication with the non-volatile memory device; determining that an amount of data in the weak page buffer has reached a predetermined data level; and writing the data from the weak page buffer into the weak page along the word line in the non-volatile memory device.

Abstract: The present disclosure relates system and method for automatic assignment of power domain and voltage domain to one or more SoC and/or NoC elements based on one or a combination of NoC and/or SoC specification/design, traffic specification, connectivity between SoC hosts that the NoC element in context is a part of, power specification (power domain and voltage domain of each host) of the hosts/SoC, and power profile(s) applicable for the NoC element in context. In another example implementation, power domain and voltage domain can be assigned to each SoC and/or NoC element based on pre-defined constraints and with an objective of reducing/minimizing static power consumption, reducing/minimizing hardware area, or identifying a tradeoff between the two parameters.